Company Public – NXP, the NXP logo, and NXP secure connections for a smarter world are trademarks of NXP
B.V. All other product or service names are the property of their respective owners. © 2018 NXP B.V.
Jerwern Yi
S32 Common Chassis Overview
September 2018 | AMF-AUT-T3219
COMPANY PUBLIC 1COMPANY PUBLIC 1
• Introduction to the S32 Platform
• What is the Common Chassis
• Consistency in Enablement
• Consistency in Safety
• Scalable Security
• Getting Safety Support
Agenda
COMPANY PUBLIC 2
Introduction to the S32 Platform
Performance Arm Safe Secure OTA SW Reuse
COMPANY PUBLIC 3
Connectivity Driver Replacement Body & ComfortPowertrain & Vehicle
Dynamics
Chassis, Safety, Torque
and Energy ManagementVehicle Network Processing
(Gateways, Domain Controllers)
Body Electronics
Edge Nodes
Radar, LIDAR, Vision
Sensor Fusion
• Long term innovator in
chassis and powertrain
control.
• Fail Safe and Fault Tolerant
support for Real-time Control
Applications
• #1 in vehicle networking and
security
• End-to-end portfolio of
networking devices
• Broadest portfolio of
integrated MCU+HV mixed-
signal solutions
• Application specific software
solutions
• #1 in radar processing
• Comprehensive radar, vision
and central processing
portfolio
NXP Automotive Microcontrollers & Processors
ISO 26262 ASIL B/D Integrated Hardware Security Automotive Grade Software & Tools
COMPANY PUBLIC 4
Large Hadron Collider
787
Kernal 2.6.0
Mars Curiosity Rover
Hubble Space Telescope
Space Shuttle
MODERN HIGH
END CAR
Source: Informationisbeautiful.net
The car today contains more
software than any
other embedded system and most
compute applications
contains greater than 100 million lines of code
Today’s Vehicle6X more lines of code
Tomorrow’s Vehicle
Increasing need of scalability,
flexibility and reusability
0
100
200
300
400
500
600
700
2005 2010 2015 2020 2025
Average Lines of Code Per Car
Mill
ions
Source: Strategy Analytics, NXP
Our vehicles are becoming software driven
COMPANY PUBLIC 5
Ease of use with Tools & Software a driving priority
• Tools & SW are a key decision criteria for our customers
• Developers experience NXP SoCs via our Tools and Software
• SW is where our customers spend the most time in development
Reduce Total Cost of Ownership
Differentiate
Shorten
Time to Market
Increase
Ease of Use
Trusted customer Relationship
Application Software
Specialized middleware
Low level drivers
HW
Development Flow
COMPANY PUBLIC 6
Vision/Autonomous MPU
Autonomous MPU
Radar MPU
Networking MPU
Safety/Powertrain MCU
General Purpose MCU
• Automotive ASIL-B to -D vision processor family
• Open, scalable software platform enabling
customization and optimization
• Acceleration for vision processing with optimal
performance per power
• Leading performance per power
• Enables high-resolution radar for
autonomous vehicle applications
• Radar SDK on top of dedicated hardware for
radar and AI functions
• Highest ASIL-D performance in the industry
• Scalable hardware and software to address L2
to L5 functions
• Automotive and Ethernet network acceleration
• High-performance network processing
• Unparalleled integration of high-bandwidth
network interfaces
• Broad portfolio
• Analog Integration
• Production-ready system solutions
• Highest performance safe MCUs in the Industry
• Advanced hardware support for Hypervisors
• ASIL-D functional safety with Fault Tolerance
• Multi-image Over-the-Air updates
Common
Architecture• Compatible base peripheral set
• Consistent boot
• One Safety concept (ASIL-D)
• One Security concept (HSE)
• Common base SDK / MCAL
• Over-the-Air ready
S32: A Platform for efficient automotive software development
COMPANY PUBLIC 7
What is the Common Chassis?
COMPANY PUBLIC 8
Common Chassis: A Common HW and SW Platform
One Common Architecture Base
• Fixed set of Cores and Interconnect
• Consistent Safety Concept & Security
• Compatible Peripheral set
• Consistent Boot
Safety Radar Gateway Vision
Application-specific Support
• Cortex-A/R/M Processors
• Accelerators
• Analog Subsystems
• Peripherals and Memory Interfaces
General
Island
General Purpose Autonomous
ARM
Cortex
Interconnect
Memory
Common Chassis
Braking
Island
ARM
Cortex
Interconnect
Memory
Radar
Island
ARM
CortexMemory
Gateway
Island
ARM
Cortex
Interconnect
Memory
Vision
Island
ARM
Cortex
Interconnect
Memory
Fusion
Island
ARM
Cortex
Interconnect
Memory
Safety
BootSecurity
Peripherals
Common Chassis
Common Chassis Common Chassis Common Chassis Common Chassis
Common Chassis
Interconnect
COMPANY PUBLIC 9
A Common Chassis and consistent ARM ISA approach
• for us to develop consistent:
− IP
− Software
− Tools
− EVBs
− Safety Documentation
− Security Collateral
− Datasheets
− Marketing Presentations
− Training Material
• so a customer can experience:
− Software re-use
− Early enablement
− Easier safety certification
− Reusable PCB design
− Consistent Partner support
− Better quality documentation
… across our portfolio
• enables a common:
− Instruction Set
− Memory map
− Interrupt map
− DMA map
− Fuse map
− Reset structure
− Clock structure
− Safety context
− Security strategy
COMPANY PUBLIC 10
Consistency in Enablement
COMPANY PUBLIC 11
HW Common Chassis
Application
Accelerator
ARM
Compute
Coherency Fabric
MemoryPeripherals HSE SafetyComms
SW Common Chassis
Common Enablement across productsConsistent Software and Tools offering
Hardware
Code Compatible Cores
Consistent Safety Concept
Scalable Security (HSE)
Identical base peripheral set
Code Generation Peripheral/Memory ViewConfigurator Graph Tools
Drivers /
MCAL
Accelerator
LibrariesSafety
LibrarySecurity
LibraryComm
Stacks
Memory
Map
HLOS / RTOS
Autosar
Software EnablementConsistent APIs
Production Quality
Development ToolsSupports all targets
Consistent look and feel
Eco-SystemTools & Software
Safety & Security
Debugger
Debug
Emulation
Driver
Profiler/Optimizer
Software Enablement
Development Tools
COMPANY PUBLIC 12
SW Common Chassis - Middleware
HW Common ChassisAccelerators
PeripheralsMemoryPeripherals HSE SafetyComms
Same Base Enablement (SDK or AUTOSAR)Consistent Software and Tools offering
OTC: OS Task Cache
OSAL: OS Abstraction Layer
RT/HL OS: Real-time / High level OS
NOC: Interconnect (Switch Fabric)
Code Generation Configurator Tools
Libraries
AUTOSAR
Multicore
Debugger
SW Common Chassis - Drivers
LL Drivers
MCAL
Comm
Stacks
Memory
MapBootloader
A53 M7
Compute
Multicore
Profiler
Base Software
Base Design Studio
R52
ComputeM33 M7
Compute
AUTOSAR
HLOS
Security
O
S
A
L Safety
ASIL-DASIL-BHypervisor
Security
Library
Safety
LibraryOTC IFPMIC IF
OTC OptimizerFlash
Programming
New Project
Wizard
Drivers
SOC Specific
RTOSRTOS
AUTOSAR
RTOS
N
O
C
COMPANY PUBLIC 13
Gateway
Vision
RadarVehicle
DynamicsGeneral
Purpose
Common Platform
Reusable Content
Not Reuseable:
1. Unique IP/App
2. Testing
Software Savings from adopting a Common Platform
NXP’s software development effort for the Common Platform:
S32G
40%
60%
S32V
25%
75%
S32R
33%
67%
S32S
42%
58%
S32K
50%
50%
COMPANY PUBLIC 14
Consistent Safety Concept
COMPANY PUBLIC 15
S32 SoC Safety Strategy
Developed as a Safety Element
out of Context (SEooC)
Following an ISO 26262 ASIL-D
Safety Development Process
Supported with complementary
safety collateral
Sensor
processing
ASIL B
Number
crunching
ASIL B to ASIL D
Decision
ASIL D
Protected
Memory
Protected
I/O
Real-time CPUsPerformance
CPUs
Application
specific
accelerators
COMPANY PUBLIC 16
Memory Bus
Main Bus
Coherent Bus
xRDC
xRDCxRDC
SRAM
xRDC
xRDC
DRAM
Security
(HSE)
HS
Comms
xRDC
DMA
DMA
DMA
DMADebug
Trace
xRDCHardware
Software
ECC on SRAM
Logic & Memory
Built-in Self Test
Clock Monitoring
Power Supply Monitoring
Redundant
Peripherals
Peripheral Bus
Timers
Comms
PLLs
FCCU
EIM
RCCU
RGM
SbSW
CMU
CRC
ADC
WDog
POST
STCUTimers
Comms
PLLs
ADC
xRDC xRDC xRDC xRDC
ECC on DRAM
Lockstep DMA with ECC on
memories & integrated CRC
To SoC Island
Delayed Lockstep or Decoupled
Performance Core(s) & INT CTL.
ECC on memories.
RT
Core
Comp
L1 Cache
TCMMPU
RT
Core
MPU
RT
Core
Comp
L1 Cache
TCMMPU
RT
Core
MPU
Delayed Lockstep Real-time Core(s) &
INT CTL.ECC on memories
Safety Feature
S32 HW
Safety
L2 Cache
Perf
Core
MMU
Perf
Core
MMU
L2 Cache
Perf
Core
MMU
Perf
Core
MMU
Comp
COMPANY PUBLIC 17
Scalable but consistent Security
COMPANY PUBLIC 18
Security Enablement
Linux Crypto APIs
Linux Secure Boot
SSL/TLS
IPSec
ISS Crypto API?
HSE Host I/F
MACSec
IPSec
SSL/TLS
Partners
Interconnect
Services
Crypto LibPeripheral Drivers Safety Lib
SWT QSPIFLASH MPU CLOCKs PowerTIMERs Debug
AUTOMOTIVERTOS
SHE+Crypto
ServicesSecure Storage
Secure Bootloader
Lifecycle Management
Scheduler
Connections Server
sICCMailboxes
Host I/F
AutosarCrypto Driver
CSM 4.xCrypto If
Security Library
SecOC
NXP SDK
HSE Host I/F
HSE Driver
HSE Firmware Signing Secure DebugOTC Load Entity Generation
Development Tools
Automotive
Spice
ISO 26262
MISRA
2016
S32 SoC
Hardware Security Engine (HSE)MPU Application Core(s)MCU App Core(s)
Software Enablement
COMPANY PUBLIC 19
In Summary
COMPANY PUBLIC 20
What does the Common Chassis enable
• Accelerates new products to market
• Quality investments amortized over all
products
• Build Software platform enablement just
once and re-use across products
• Software offering moves further up the
stack … not stuck in just platform
enablement.
• Tools offering differentiates the Silicon
instead of just enabling the Silicon
• Documentation (User Manuals, Safety
Manuals) not a re-work for every SoC
For NXP & Partners … For our customers …
• Their software investment can now be re-used across their portfolio of Applications (vs. just within one Application space)
• Same Tools means not having to learn new ways to do development
• Proven Silicon means dealing with less errata or at worst consistent work-arounds
• Focus on what differentiates their application vs. what enables our Si.
• Don’t experience inconsistencies in our documentation
• Get more value-add from NXP with more collateral and software
NXP, the NXP logo, and NXP secure connections for a smarter world are trademarks of NXP B.V. All other product or service names are the property of their respective owners. © 2018 NXP B.V.
www.nxp.com
