Date post:04-Jan-2016
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Tips and Tricks
Tips and Tricks
Using PICmicro® MCUs
Please select the tips you are comfortable with and discuss them rather than even attempting to go through all of them. To go through the examples in detail will take a few hours and in the advanced seminar this section has 1 hour allocated to it.
These examples are primarily for the x12 and x14 architecture , there are additional instructions on the x16 architectures that eliminate the need for some of these tips to be used.
As a suggestion there is a file available tips499.asm available and an tips499.pjt which you can use to learn more about some of the examples. You will need to force the PC to the appropriate example and then the registers in that example can be written to while running the code till the NOP at the end.
Tips and Tricks
Increments and Decrements
AT_FF:
Mention example1 and gloss over 2 and 3 as they operate on FF as opposed to zero.
1. Uses \$ in the goto instruction to eliminate labels, shows smallest code for a 16 bit increment without a skip if non zero instruction
2. Could use only 3 instructions if transition was at 00 as opposed to FF
3. Only useful if FF transition mandatory
Tips and Tricks
Enter with value to be tested in W.
Exits with Carry set if W is in the range [LOVAL to HIVAL], inclusive.
Compare and Swap
Compare the values in registers X and Y. If Y < X, swap them.
movf X,W ;GRAB X.
subwf Y,W ;Y >= X?
addwf X ;OTHERWISE, X = X + (Y-X) = Y,
subwf Y ; AND Y = Y - (Y-X) = X.
4. Note parameter passed W. Good general routine to test if register is within a certain range. Good to use to asses if a temperature measurement is within a predefined range.
5. Compares two numbers and puts them in ascending order. Can be useful when sorting numbers into order for further analysis.
Note the use of the ‘bc’ instruction which is a two word instruction, atest of the carry bit followed by a goto.
Tips and Tricks
Comparisons
Minimum
Enter with three values stored in registers N1, N2, and N3. Exit with min(N1,N2,N3) in MIN, N1-3 unchanged, W scrambled.
movf N1,w
subwf N2,W
movf N1,W
6. Neat way of storing the smallest value in MIN without disturbing any of the three variables.
Tips and Tricks
Enter with 0ABCDEFG in W. Exits with 0GFEDCBA in W.
movwf source ;source = 0ABCDEFG.
swapf source,w ;W= DEFG0ABC.
btfsc source,3 ;If D = 1, invert D and the “0”.
xorlw 0x88 ;After this line, W = 0EFGDABC.
btfsc source,6 ;If A = 1, invert bits A and C.
xorlw 0x05 ;
btfsc source,4 ;If C = 1, invert A and C again.
xorlw 0x05 ;After this line, W = 0EFGDCBA.
btfsc source,2 ;Do the same with E and G.
xorlw 0x50 ;
btfsc source,0 ;
xorlw 0x50 ;After this line, W = 0GFEDCBA.
7. Change made to slide from the April printing. ‘temp’ changed to ‘source’ in the first line of code.
Method to reverse 7 bits of data that may have been rec’d from a USART in LSb and MSb is desired in the software.
Tips and Tricks
Rotate in Place
Rotate without inserting an extra bit from the carry. Easily extended to multi-bit rotates. Enter with ABCDEFGH in REG. Exits with BCDEFGHA in REG, W scrambled.
rlf REG,W
rlf REG
Bit-Copy
Copy bits from one register to the same position in another.
movf SOURCE,W ;The DEST bits in the positions to ;which we’re copying must not change xorwf DEST,W ;between this xorwf instruction and ;the xorwf DEST below.
andlw 00000111B ;A "1" in each bit-position we’re ;copying.. ;this example copies the three LSBs.
xorwf DEST
8. Shows how the carry bit can be well utilised with the instructions
9.
Tips and Tricks
Bit Counter
Count the number of "1" bits in a register. On exit, W contains the number of "1" bits in REG, and REG is scrambled.
rrf REG,W
andlw 0x44
subwf REG
movf REG,W
andlw 0x33
rrf REG
andlw 0x11
rrf REG
swapf REG,W
andlw 0x0F
Tips and Tricks
; Enter with bit number [0-7] in BITNUM. Exits with bit mask in W.
movlw 0x01
btfsc BITNUM,1
movlw 0x04
movwf temp
btfsc BITNUM,0
btfsc BITNUM,2
swapf temp
movf temp,w
Tips and Tricks
Set to zero:
clrf reg
bsf reg,bit
clrf reg ;Set bits
clrf reg ;Set bits
clrf reg
bsf reg,bit1
bsf reg,bit2
bsf reg,bit3
bsf reg,bit4
clrf reg
decfsz reg
bcf reg,unbit1
bcf reg,unbit2
bcf reg,unbit3
Tips and Tricks
ENDIF
ENDIF
Assembler Macro
To Call it use Wait 50 and it will include a wait equivalent to 50 clock cycles.
Tips and Tricks
; NUMBER OF CYCLES TO DELAY IN W.
;
Tips and Tricks
Delay131072: call Delay16384
Delay114688: call Delay16384
Delay98304: call Delay16384
Delay81920: call Delay16384
Delay65536: call Delay16384
Delay49152: call Delay16384
Delay32768: call Delay16384
Delay16384: call Delay2048
Delay14336: call Delay2048
Delay12288: call Delay2048
Delay10240: call Delay2048
Delay8192: call Delay2048
Delay6144: call Delay2048
Delay4096: call Delay2048
Delay2048: call Delay256
Delay1792: call Delay256
Delay1536: call Delay256
Delay1280: call Delay256
Delay1024: call Delay256
Delay768: call Delay256
Delay512: call Delay256
Delay256: call Delay32
Delay224: call Delay32
Delay192: call Delay32
Delay160: call Delay32
Delay128: call Delay32
Delay96: call Delay32
Delay64: call Delay32
Delay48: call Delay32
Delay32: call Delay4
Delay28: call Delay4
Delay24: call Delay4
Delay20: call Delay4
Delay16: call Delay4
Delay12: call Delay4
Delay8: call Delay4
Tips and Tricks
subwf DEST_LO ;Note that the Z flag is
movf SOURCE_HI,W ;invalid after the
skpc ;subtraction.
incfsz SOURCE_HI,W ;
subwf DEST_HI
movf SOURCE,W ;DEST = DEST + SOURCE + CARRY
skpnc ;Carry is valid after the
Tips and Tricks
;CALCULATE NEW_AVERAGE = (255 * OLD_AVERAGE + NEW_SAMPLE)/256.
;ENTER WITH THE NEW SAMPLE IN W. EXITS WITH THE NEW AVERAGE IN W.
AVERAGE:
movf SUMHI,W ;(AND WHILE WE'RE HERE, PUT THE OLD
skpnc ;AVERAGE IN W).
skpc ;AVERAGE FROM THE NEW SUM.
decf SUMHI ;
return ;RETURN.
Tips and Tricks
addwf SOURCE,W ;Carry-out is only valid if SOURCE<255.
skpc ;is valid.
Tips and Tricks
Even Parity
;
Even parity check.
After executing this routine, testing any of bits 1,2,3,4 or 5 will indicate even parity or not
Tips and Tricks
Even Parity
;Enter with input in register X. Branches to "ZERO" or "ONE"
;depending on parity. Doesn’t modify register X. For odd
;parity, replace "GOTO ZERO" with "GOTO ONE", and vice-versa.
;19 words. 5 or 7 cycles, including branch to ZERO or ONE.
SWAPF X,W
XORWF X,W
ANDLW 00001111B
GOTO ZERO
GOTO ONE
GOTO ONE
GOTO ZERO
GOTO ONE
GOTO ZERO
GOTO ZERO
GOTO ONE
GOTO ONE
GOTO ZERO
GOTO ZERO
GOTO ONE
GOTO ZERO
GOTO ONE
GOTO ONE
Tips and Tricks
EQU vs. #define
equ1 equ 5+3 ;MPASM will replace future ;occurrences of "equ1" with the ;value 8.
#define def1 5+3 ;MPASM will replace future ;occurrences of "def1" with the ;string"5+3".
x equ 3*equ1 ;This line is equivalent to "x ;equ 3*8", so x = 24.
y equ 3*def1 ;THIS line, on the other hand, ;is equivalent to "y equ 3*5+3", ;so y = 18.
Tips and Tricks
.... ;doesn’t allow REG to be viewed
MOVWF REG ;in MPLAB Watch Windows.
Method #2:
Method #3:
;accidentally used with a
;correctly, but does generate a
;warning if accidentally used ;with a page-0 register.
Tips and Tricks
HIGH-and-LOW vs. Shift-and-AND
BIGNUM EQU 0x123456
LSB EQU LOW (BIGNUM) ;’LSB’ will always be set to ;0x56.
MSB EQU HIGH (BIGNUM) ;Some versions of MPASM will ;set "MSB" to 0x12; others ;will set it to 0x34.
SAFEMSB EQU (BIGNUM>>16) & 0xFF
;This method will always set ;"SAFEMSB" to 0x12.
Tips and Tricks
; Here, TMR0:PRE must be 01:3 or 02:0
BTFSS TMR0,BIT1
GOTO \$+1
GOTO \$+1
; TMR0 always increments from 02 to ;03 right here. When we reload TMR0, ;we need to add 4 to the reload value
;because the MOVLW/MOVWF takes 2
;cycles and there’s an additional 2-
;cycle synchronization delay. TMR0
;the moment when it would have rolled
;over from 03 to 04.
; and the prescaler divide-by-
; ratio set to divide-by-4.
BTFSS TMR0,BIT0
GOTO \$+1
; or 01:2.
GOTO \$+1
Tips and Tricks
16-Bit Pulse-Width Measurement with 5-Cycle Resolution
; Enter with PULSE_WIDTH_HI:LO set to 0000. Exits ; ; when PORT,PIN goes low.
CHECK_PULSE:
Tips and Tricks
Zero I/O-Pin PICmicro-to- PICmicro Communication
Your Master PICmicro controls the Slave PICmicro's MCLR line. The Master normally keeps the Slave's MCLR line high (out of reset). When the Master wants to send a message, it pulls the Slave's MCLR line low, then pulls it high for a short time before pulling it low, then high again. The "message" is the time between MCLR-low pulses.
Message error-proofing methods:
Redundancy: Send the message two or more times and require that the Slave see consecutive, identical messages before acting on them.
Parity: Send your message, then follow it with a "parity” message that brings the total time-between-MCLR-low-pulses time to some constant value.
Framing: Send a unique-length "start of message" pulse, then your message pulse, then a unique-length "end of message” pulse. The Slave doesn't accept the message unless it sees the "start" and "end" pulses around it.
Tips and Tricks
Fosc/2, Fosc/8, Fosc/32 and Frc(internal RC)
Tad Min. = 1.6 uS for VREF => 3.0V or 3.0uS for VREF < 3.0V
For fastest A/D response, calculate the Tad which is closest to the Minimum value for Tad
Example: VREF = 5.0V, Fosc = 4.0 MHz
For fastest A/D response, select Fosc/8 (2.0 uS).
If Frc is selected, instead of Fosc/8, then Min. time would be 2.0us, but the Max. time would be 6.0us I.e. 3 times slower than the best A/D response time.
For fastest response, select Fosc = 5.0 MHz (Tad = 1.6uS) instead of 4.0Mhz (Tad = 2.0 uS).
Hardware Interfacing
Selection of the Tad clock source is important when trying to get the best response from the A/D. An internal RC derived Tad is provided, but its wide variation makes it less desirable for fast a/d conversions. Using the clock based A/D is fast, consistent and is less prone to variation due to Vdd or temperature changes.
Q: Why have the internal RC. A: For a/d conversions during sleep, Frc is the only clock source available for the a/d conversion.
Q: What happened if the Tad clock selected is faster than the min clock spec for Tad? A: The A/D result cannot be guaranteed, but the conversion will be completed and the ADRES will be loaded.
Q: Can you change clock speeds in the middle of a conversion? A: Yes you can between Oscillator mode, but not between RC and Oscillator modes. Min spec for Tad has to be met for a valid conversion to occur
Tips and Tricks
To start an A/D conversion the GO bit should be set to 1.
Note: ADON and GO bit should not be set in the same instruction
On conversion complete, GO/DONE = 0 & ADIF = 1.
Fastest check of A/D conversion completion:
Bit test ADIF or the GO/DONE bit in “tight loop” .
goto \$-1
3T cycles for interrupt latency
10T cycles for Context Saving + 1T cycle for ADIF check
Total = 14 T cycles
Hardware Interfacing
The GO/DONE bit has to be set for the start of a A/D conversion. Turing on the A/D by setting the ADON bit in the same instruction which starts the A/D conversion, should be avoided. On completion of the A/D conversion, the ADIF bit is set and the GO bit is reset. To get the fastest A/D completion time, it is best to test the GO/DONE or ADIF bit in a tight loop. This would take a max. of 3 Tcy. If interrupts are used then the time taken to respond to the interrupt would include the 3Tcy for the interrupt latency, the 10Tcy for the Context save and finally 1Tcy for the test of the ADIF flag itself to give a total of 14Tcy almost 5 times greater than with the tight loop.
Q: Why have the ADON bit if another bit has to be used to start the A/D conversion? A: the A/D consumes about 500 uA of current, so in battery powered applications where every uA is counted, the A/D can be turned off when not used.
Q: If the tight loop is the fastest way to test the completion of the A/D conversion, why have the interrupt scheme. A: from the time the GO bit is set, the conversion time is about 20uS. In that time, some other operations may be required to be done. So an interrupt scheme is needed. Also when A/D is done in sleep, an interrupt scheme is required to wake the chip up form sleep after the conversion.
Tips and Tricks
Enable or disable A/D Interrupt
Start A/D conversion and goto sleep
On A/D Completion:
If interrupt is enabled then CPU wakes up from sleep
If interrupt is disabled then CPU does not wake up from sleep, but A/D circuit is turned OFF (ADON is still set).
In Crystal mode conversion in sleep is slow since most crystals take 2 mS or more to wake-up
For fast conversion in sleep, use RC oscillator
Hardware Interfacing
The conversion in sleep is offered as a feature to allow the user to do a precision conversion with all processor background digital noise turned off. To accomplish this, the user must use the RC mode for the Tad clock. Set the interrupt scheme for the A/D completion and either enable or disable the A/D interrupt. Start the conversion by setting the GO bit and execute the sleep instruction. On a/d completion, the chip gets a wake-up from sleep. Now if the interrupt is enabled and if the GIE bit was set, then an interrupt is generated and the PC vectors to the interrupt vector. On the other hand if the GIE bit was not set, then the very next instruction is executed after wake-up. If however the A/D interrupt was not set then after A/D completion the chip would not wake-up, however it would turn the A/D OFF to conserve power. The ADON bit would be still set, so the user has to take note of this and clear the ADON bit when the CPU wakes up.
Q: What happens if Frc is nor selected for A/D conversion in sleep. A: the A/D operation is aborted and the A/D is turned OFF, but the ADON bit is still set. CPU does not wake-up from sleep. DON’T DO THIS!!
Tips and Tricks
Direct Modification of PC (or PCL)
For example, to calculate 2^W, where W is in the range [0-7]:
TBL 1,2,4,8,16,32,64,128
assembles to:
ADDLW HIGH (B)+1 - HIGH (C)
ADDLW HIGH (C)+1 - HIGH (D)
ADDLW HIGH (D)+1 - HIGH (E)
ADDLW HIGH (E)+1 - HIGH (F)
ADDLW HIGH (F)+1 - HIGH (G)
ADDLW HIGH (G)+1 - HIGH (H)
Tips and Tricks
XORLW VAL1 ;IF W = VAL1, GOTO CASE1.
BZ CASE1 ;
BZ CASE2 ;
BZ CASE3 ;
BZ CASE4 ;
Tips and Tricks
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