Sampling Mixer for Software Defined Radio Applications using 0.18µm RF

CMOS Technology

by

Matt Davis and Chris Davis

A Final Report Submitted to the Principal Investigator of

NSF Research Experiences for Undergraduates: Cognitive Communications

Virginia Polytechnic Institute and State University

Bradley Department of Electrical and Computer Engineering

Principal Investigator: Dr. Carl Dietrich

Project Mentors: Dr. Kwang-Jin Koh and Hedieh Elyasi

July 2013

i

Table of Contents Abstract ........................................................................................................................................... 1

1. Introduction ............................................................................................................................. 2

2. Basics of Mixer ........................................................................................................................ 4

3. Circuit Design .......................................................................................................................... 8

4. Simulation Results ................................................................................................................... 9

5. Conclusion ............................................................................................................................. 12

5. References ............................................................................................................................. 13

ii

Table of Figures

Figure 1: Ideal SDR Architecture ................................................................................................... 2

Figure 2: Primary Functional Units of Receiver: High Level Diagram.......................................... 3

Figure 3: Theoretical Output Frequency Spectrum of Mixer ......................................................... 4

Figure 4: Graphical Representation of 1 dB Compression Point .................................................... 5

Figure 5: IIP3 Frequency Spectrum Graphical Theory ................................................................... 6

Figure 6: IIP3 and 1dB Compression Point Relationship ............................................................... 7

Figure 7: DSM Simplified Circuit Diagram ................................................................................... 8

Figure 8: Frequency Spectrum: RF Input Power ............................................................................ 9

Figure 9: Frequency Spectrum: IF Output Power ........................................................................... 9

Figure 10: Simulation 1 dB Compression Point ........................................................................... 10

Figure 11: Calculated IIP3 from Simulation ................................................................................. 10

Figure 12: IIP3 Graphical Simulation Result................................................................................ 11

iii

Table of Tables

Table 1: Summary of DSM Simulation Results ........................................................................... 11

1

Abstract

A major aspect of cognitive radio (CR) includes the ability to dynamically adjust transmission

frequency due to various changes in a devices operating environment. The basis of CR is built

upon software-defined radio (SDR) technology. Sampling mixers provide frequency translation

that aid in the analog-to-digital conversion process for SDR, as well as move analog-to-digital

converters (ADC) closer to the antenna input; a major goal to achieve enhanced performance

while maintaining low power consumption and low cost in software defined radios. In this

project, a simple direct sampling mixer has been designed, simulated, and analyzed using

0.18um RF CMOS technology to meet frequency-adaptive carrier demodulation demands.

Proposed sampling mixer simulation results include noise figure (NF) of 15 dB, conversion gain

of 20.5 dB, 1dB compression point -16.67 dBm, third-order intercept point (IIP3) of -5.81 dBm

and power consumption of 3.66 mW.

2

1. Introduction

Software-defined radio (SDR) serves as the current optimal solution to combat the rapid increase

of multiple wireless communication standards and protocols that use several different

modulation schemes, carrier frequencies, and channel bandwidths [1]. Ultimately, software-

defined radio wants to replace as many analog components and hardwired digital VLSI devices

of the transceiver as possible with programmable devices [2]. As a result, the SDR parameters

including standards, protocols, and modulation schemes are all generated or defined by software.

Two primary advantages that this implementation provides include flexibility and adaptability.

Modern technological devices, i.e. mobile devices, consistently change transmission parameters

based on available connections and data-specific transmission. Not only is the idea of flexibility

self-evident given the need to dynamically adjust transmission parameters for different standards,

also innovation and creation of new standards and protocols to further optimize wireless

communication are easily integrated into SDR transceivers without overhead cost of custom

hardware design, unit fabrication/packaging , and hardware installation/replacement. Ideally,

SDR architecture would model a pure Software Radio (SR) consisting of an antenna to an

analog-to-digital converter (ADC) that would sample the radio-frequency (RF) signal and

provide digital representation of information that would be manipulated by software, as seen in

Figure 1.

Rx

A/D SDR Applications

Figure 1: Ideal SDR Architecture

However, due to limitations of current technology, sufficient sampling cannot be achieved by the

ADC to provide an accurate representation of high frequency RF information signals, high

resolution ADC. Therefore, other functional units are required to achieve correct conversion

from analog-to-digital domain.

An important functional unit that aids in this conversion process includes a mixer. To provide

context of a mixer in the transmission process, Figure 2 displays the major functional units

characterized of a modern receiver.

3

LNA

MixerFilter A/D

Rx

LO

RF IF SDR Applications

Figure 2: Primary Functional Units of Receiver: High Level Diagram

A mixer provides necessary frequency translation of desired RF signal, to a lower intermediate-

frequency (IF) signal that can be adequately converted to digital domain for SDR applications.

A mixer architecture gaining wide notoriety in SDR applications include sampling mixers.

Among different architectures of mixers, sampling mixer attracts attention of designers for SDR

application because of it discrete output. Due to discrete time signal processing prior to

digitization, ADC performance is relaxed. Essentially, sampling mixers use submicron CMOS

technology to perform sampling and mixing through “ON/OFF” switches controlled by local

oscillator at the gate of MOSFET (Figure 7). Major benefits of passive direct sampling

architecture include re-configurability by adjustment of either sample/hold capacitors or input

clock frequency, i.e. LO(local oscillator) and capability of mixing, filtering, and decimation for

alleviating ADC requirements[3].

The input signal can be voltage or current domain. In this project we chose charge domain

sampling mixer because of following reasons:

We can achieve higher bandwidth compared to voltage domain because of capacitance

value limitation. Since capacitor and on resistance of switch are behaving as low pass

filter, the value of capacitor cannot be very high.

Since we don’t have limitation on capacitor value, we can increase it to get lower noise.

Mixer switches does not need any DC current which results in low power consumption

and low flicker noise.

The focus of this paper surrounds the design, simulation, and analysis of a passive direct

sampling mixer using 0.18µm RF CMOS technology to meet the broadband frequency

demodulation demands required to more closely realize the ideal SDR architecture explained

before above. The following paper outlines the basic fundamental background theory

surrounding mixer theory and modern mixer performance metrics, followed by a simplified

circuit diagram of simulated DSM architecture, simulation results and analysis of proposed

DSM, and concluding remarks regarding current design and future applicable methods to

improve designed DSM performance.

4

𝑉𝐼𝐹(𝑡) = 𝐴𝑅𝐹 cos 𝜔𝑅𝐹𝑡 ∗ 𝐴𝐿𝑂 cos 𝜔𝐿𝑂𝑡 =1

2𝐴𝑅𝐹𝐴𝐿𝑂[cos(𝜔𝑅𝐹 − 𝜔𝐿𝑂)𝑡 + cos(𝜔𝑅𝐹 + 𝜔𝐿𝑂)𝑡] (1)

2. Basics of Mixer

As mentioned earlier in his paper, the primary function of a mixer is to provide frequency

translation; specifically in context with conducted research, frequency translation from the input

RF signal to the output IF signal appropriate for analog-to-digital conversion process necessary

for SDR applications in the physical layer of a radio receiver. Figure 3 expresses the theoretical

output frequency spectrum of a mixer seen as a result from input signals RF and LO

multiplication.

Figure 3: Theoretical Output Frequency Spectrum of Mixer

As a fundamental result applied to the multiplication of 2 cosine waveforms seen in equation (1),

a mixer has outputs at both 𝜔𝑅𝐹 − 𝜔𝐿𝑂 and 𝜔𝑅𝐹 + 𝜔𝐿𝑂 frequencies.

Modeling a radio receiver, the down converted signal (𝜔𝑅𝐹 − 𝜔𝐿𝑂) stands as the signal of

interest with up-converted (𝜔𝑅𝐹 + 𝜔𝐿𝑂) signal being filtered out in a real-world implementation

setting.

Analyzing the output frequency spectrum in Figure 3, one can observe that the output power of

the down converted signal holds a higher amplitude than input RF signal voltage/power. This

observation serves to express an importance performance metric of the proposed conversion

gain. As expressed before in Figure 2, there are multiple functional blocks the both the RF and IF

information signals travel through before ADC. To keep context, RF signals typically are

received in the µW or potentially nW level, meaning that any attenuation from functional units

could potentially harm the overall performance of the receiver by not providing an adequate

information signal to be converted to the digital domain. Therefore, the overall gain of the mixer

unit stands important in the overall process of a receiver relating the output IF voltage to the

input RF voltage. The term “conversion” gain stems from the fact that the frequency seen at the

output IF terminal potentially could be different from input RF terminal, not reflecting a true

gain correspondence.

5

Another performance metric for evaluating a mixer is Noise Figure (NF). Noise Figure serves as

a way to measure the SNR degradation due to the noise added by the system [4]. Equation 2

highlights the important parameters that define NF.

𝑁𝐹 = 10 log10(𝑆𝑁𝑅𝑖𝑛

𝑆𝑁𝑅𝑜𝑢𝑡) = 10 log10(

1

𝐺𝑚∗

𝑁𝑜𝑢𝑡

𝑁𝑖𝑛) [𝑑𝐵] (2)

The lowest possible value NF that can be achieved is desired.

Linearity among the input RF signal and output IF signal of designed DSM stands as a crucial

metric in mixer performance-evaluation. The high level concept of linearity corresponds to how

much input RF power the mixer can sustain until the operation and corresponding output IF is

non-ideal/non-desirable. Due to the non-linear aspects of circuit elements, i.e. MOSFEETS, the

transistors exhibit an input power threshold that compresses the output power of the circuit,

resulting in undesired behavior and potential distortion of information signal. An important key

term that describes this event includes 1 dB Compression Point. This point is defined as the

input power at which the output power drops by 1dB from the predicted output power based on

the small signal power gain. Figure 4 depicts a graphical representation of the 1dB Compression

Point [5].

Figure 4: Graphical Representation of 1 dB Compression Point

Further describing the figure above, the dotted line represents the ideal linear curve of the input-

power to output-power behavior, where the solid non-linear curve exhibits actual output of

system with respect to input power. Ultimately, the 1 dB Compression point can be thought of as

the self-jamming effect where the output signal of the system under evaluation exhibits nonlinear

behavior as a direct result of the circuit elements, when linear behavior is desired.

Understanding the actual application of the sampling within an SDR receiver reveals another

important key term that must be evaluated and considered within the proposed DSM. At any

given point in time, numerous signals occupy the limited spectrum space, meaning that several

other signals closely spaced to the desired signal are received and processed by the front end RF

6

systems which may not be are desired signal and behave as an interference. Therefore, definition

of the third-order intermodulation intercept point (IIP3) parameter provides more key insight and

characterization of the non-linear behavior of the circuit. By applying an experiment labeled the

two-tone test, IIP3 is measured and quantified. The two-tone test calls for applying two closely

spaced frequency tones which have same amplitude into the input of the designed DSM as seen

in Figure 5 below.

Figure 5: IIP3 Frequency Spectrum Graphical Theory

Applying the basic fundamentals discussed earlier regarding mixer output, one can clearly see

the expected output frequencies of 𝜔𝑠1 = 𝜔𝑅𝐹1 − 𝜔𝐿𝑂 and 𝜔𝑠2 = 𝜔𝑅𝐹2 − 𝜔𝐿𝑂. However, due to

the intermodulation distortion characteristics, third-order intermodulation tones (IM3) can be

seen at frequencies 2𝜔𝑠1 − 𝜔𝑠2 and 2𝜔𝑠2 − 𝜔𝑠1. These signals fall within the frequency range

that cannot be filtered out with added RF circuitry, therefore, having direct effect on the desired

frequency of 𝜔𝑠1.

Another way to find IIP3 is defined as the signal level at which the extrapolated output signal

levels at 𝜔𝑠1 (or 𝜔𝑠2) and 2𝜔𝑠1 − 𝜔𝑠2 (or 2𝜔𝑠2 − 𝜔𝑠1) meet each other. Figure 6 displays the

graphical representation of IIP3 in relation to the previous concept of 1dB compression point.

2𝜔𝑠1 − 𝜔𝑠2 2𝜔𝑠2 − 𝜔𝑠1 𝜔𝑠1 𝜔𝑠2

𝑷𝒐𝒖𝒕(𝒅𝑩𝒎)

𝝎

∆

𝜔𝑅𝐹1 𝜔𝑅𝐹2 𝜔𝐿𝑂

𝐼𝐼𝑃3(𝑑𝐵) = ∆

2+ 𝑃𝑖𝑛𝑝𝑢𝑡 (3)

7

Figure 6: IIP3 and 1dB Compression Point Relationship

Ultimately, 3rd –order intermodulation distortion corrupts the signal since it falls in the same

frequency band as the signal of interest. IIP3 serves as a metric to characterize at which input

power level this distortion will occur.

8

3. Circuit Design

Figure 7 displays simple circuit of the proposed DSM with which simulations and quantitative

analysis were conducted.

Figure 7: DSM Simplified Circuit Diagram

The proposed DSM was designed using process technology 0.18µm RF CMOS.

Transconductance Amplifier (TA) is implemented as an inverter since it is simple, as well as

giving a greater gain and acceptable noise figure by combining the gain of the NMOS transistor

and the gain of the PMOS transistor, compared to single NMOS or PMOS. The TA gain is

evaluated from the following equation:

𝐺𝑚 = 𝑔𝑚𝑛+ 𝑔𝑚𝑝

(4)

Once the signal passes through the TA, the signal is transferred from the voltage domain to the

charge domain.

The transfer of the signal from the voltage domain to the charge domain is important for the

simple reasons of maintaining linearity in the circuit and broadband capabilities. Due to the

filtering effects of the RC components within the circuit the charge domain retains its linearity

over broad frequency range. Where as in the voltage domain the filtering effects cause the

circuit to experience non-linearity, which limits the bandwidth of the circuit.

The high conversion gain of the DSM is a desired result of the system. The conversion gain of

the DSM is evaluated from the following equation:

𝐶𝐺𝑚𝑖𝑥𝑒𝑟 =2

𝜋∗

𝐺𝑚

𝐶𝐿𝑠 (5)

9

4. Simulation Results

Figure 8 shows the RF signal of -25 dBm at 600 MHz in the frequency domain while Figure 9

demonstrates the IF signal at -4 dBm at 125 MHz in the frequency domain. The specified power

difference in dBm level in Figure 9 and Figure 8 reflects the conversion gain of the system.

Figure 8: Frequency Spectrum: RF Input Power

Figure 9: Frequency Spectrum: IF Output Power

Figure 10 is a graphical representation of the 1-dB compression point of the system. As shown

in the graph, the 1-dB compression point of the system is -16.77 dBm; although, the desired

result was -12 dBm.

10

Figure 10: Simulation 1 dB Compression Point

Figure 11 is the frequency domain graph of the 2-tone test performed to calculate the IIP3 value

of the system. The IIP3 was evaluated using the following formula:

Figure 11: Calculated IIP3 from Simulation

Figure 12 is a graphical representation of the IIP3. As shown in the graph the IIP3 point of the

DSM is at -5.81 dBm. Desired result is -3 dBm.

𝐼𝐼𝑃3(𝑑𝐵) = ∆

2+ 𝑃𝑖𝑛𝑝𝑢𝑡 (6)

11

Figure 12: IIP3 Graphical Simulation Result

Table 1 displays a summary of simulation results.

Table 1: Summary of DSM Simulation Results

12

5. Conclusion

A passive direct sampling mixer with 0.18µm RF CMOS technology was designed, simulated,

and analyzed. The simulation results demonstrate that the circuit works in the correct manner.

The DSM functionality of re-configurability was achieved through the clock frequency of the

local oscillator. Notable results include conversion gain, IIP3, and power consumption. Areas to

improve include 1-dB compression point and noise figure.

13

5. References

[1] R. Bagheri, A. Mirzaei, M. E. Heidari, S. Chehrazi, M. Lee, M. Mikhemar, W. K. Tang,

and A. A. Abidi, “Software-defined radio receiver: Dream to reality,” IEEE Commun.

Mag., vol. 44, no. 8, pp.111–118, Aug. 2006.

[2] M. Sadiku and C. Akujuobi, “Software-defined radio: A brief overview,”

IEEE Potentials, vol. 23, no. 4, pp. 14–15, Oct./Nov. 2004.

[3] Y. Morishita, K. Araki, “Design and analysis of direct sampling mixers,” Microwave

Conference Proceedings (APMC), 2011 Asia-Pacific, pp. 375 – 378, Dec. 2011.

[4] Carusone, Tony Chan., David Johns, Kenneth W. Martin, and David Johns. Analog

Integrated Circuit Design. Hoboken, NJ: John Wiley & Sons, 2012. Print.

[5] Razavi, Behzad. RF Microelectronics. Upper Saddle River, NJ: Prentice Hall, 2012.

Print.