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Sapphire NP Platform Review
Daniel Fan
XTOS Apps Training
July 2003 2NPTest Confidential Information
Test Trends
Structural test on DFT Testers Distributed Test strategies Combinational Test Multithreaded Multi-site Test
2003
2004
2005
2006
Cost of ICQuality
High VolumeManufacturing
StructuralTest
Functional Test
EngineeringQualification
DesignValidation
DesignDebug
Device
Ch
aracterization
July 2003 3NPTest Confidential Information
NPTest 3-part Solution to Test Trends
• NPower– 4D ScalableTM ATE architecture, enables a unique
cost of test roadmap
• XTOS– State-of-the-art SW technologies and industry
standards in a PC Windows environment– Strong links to EDA and powerful GUI tools
• Sapphire NP– First NPTest system based on NPower and XTOS– Provides an optimized solution for the transition
from functional to structural test
July 2003 4NPTest Confidential Information
Sapphire NP System
Universal manipulator• Designed for Sapphire by ESMO• Proven with Sapphire
Test Head• Houses all TH instruments• Integrated power bus &
cooling for TH instruments
Integrated HX (in bay)• Cooling for TH instruments
Sapphire Bay• Houses ACPower Distribution, Bulk DC Power & system PC
Load Board Frame, Pull Down & Docking Mechanism
• Designed for Sapphire by inTEST
July 2003 5NPTest Confidential Information
SYSCLK
IFITestheadInterface
PCBDigitalDigital DPSDPS
AnalogAnalog SpecialSpecial
48V DC
SM Bus
Tester per Instrument
• Instruments operate as stand alone testers. Resources on-board
• Lightning fast program load, data collection and communications with the Isochronous Fabric Interface™ (IFI)
– 800MBytes/s around testhead, 250MBytes/s between CPU & Testhead– Picoseconds coherency between digital and analog instruments
• High accuracy clock distribution guarantees timing accuracy
• All instruments have integral self test and diagnostics capability
• Optional 100BaseT for instruments not needing IFI performance– Facilitates 3rd party, or customer instrumentation
• Any instrument fits any slot for unprecedented scalability
Router 100BaseT
July 2003 6NPTest Confidential Information
Sapphire NP Advantage
SapphireDigital Instrument
• Sequence control• APG and Scan• Sequence control• APG and Scan
• Timing generation• Formatting• Pattern memory
• Timing generation• Formatting• Pattern memory
• Pin electronics• Levels• PPMU
• DC-DC Power• DC-DC Power
July 2003 7NPTest Confidential Information
SYSCLK
IFITestheadInterface
PCBDigitalDigital DPSDPS
AnalogAnalog SpecialSpecial
48V DC
SM Bus
Advanced Instrument Synchronization
• Any instrument (digital/analog/DC) can send synchronizing events to any other module– Multiple sync types: “Match”, “Continue,” “Fail” or “End” test….– Test sequence can be driven by digital or analog events … or both!– Test strategy is efficiently mapped to device functionality
• When a sync event is sent, it is associated with a time-stamp– Phase coherence is maintained across all instruments
Router 100BaseT
Sapphire NP Digital Instruments
July 2003 9NPTest Confidential Information
Digital Instrument block diagram
• Number of channels depends on instrument performance
• Built-in resources support high-speed calibration and diags
• TMU per instrument
• PMU per instrument
• PMU per pin• Optional HVPE
per instrument
EEPROM
SM
Bus/Syncinterface
In
Out
Clo
ckd
istr
ibu
tio
n
400MHz
DC
/DC
con
vert
er
48VTMU
PMU
RelayTree
Voltage Ref
DIMM
Mem
ory
Mg
rF
PG
ADIM
MD
IMM
FMT
FMT
Tim
ing
/D
ata
Gen
era
tors
FMT
FMT
Tim
ing
/D
ata
Gen
era
tors
FMT
FMT
Tim
ing
/D
ata
Gen
era
tors
FMT
FMT
Tim
ing
/D
ata
Gen
era
tors
4X
Mem
ory
Mg
rF
PG
ADIM
MD
IMM
4 D
irec
t 4 direct TMUpogosPer Pin Slice
Seq. Memory MgrFPGA
July 2003 10NPTest Confidential Information
Flexible Pattern Generation and Allocation
Timing
Calibration
Fail CaptureMemory
F-DATA
Calibration
Event Sequence MemoryPer Pin
Per Event “On the fly”Calibration
Memory
FAIL DATA
APG
To PEDriver
From PEComp
Timing and FormattingSequence Control
Vector Type Selection
Per Pin
DIMM
DIMM
Pattern Mgr
Pattern DataSelector
LIM
MIMSequencer
DIMM
AddressGenerator
Scan
Main
Subroutine
Analog
JuanaFPGA
IsabelaFPGA
July 2003 11NPTest Confidential Information
Programmable Logic Benefits
• Sapphire Sequence Control and Pattern Manager implemented using high performance FPGAs– Newer technologies support 200MHz opcode
execution rates– Reduces development risks (minimizes need for
custom ASICs)– Shortens time to market for new capability– Enhances flexibility– Facilitates SW upgrades for new options and
capabilities• SCiD non-determinism can be handled using modified
FPGA code
July 2003 12NPTest Confidential Information
Unified Memory Manager
• Unified Memory Manager (UMM) per instrument allocates sea-of-memory to match test program requirements
• Uses industry standard DIMMs– Supports field upgrades
in-line with DIMM roadmap
• FPGA controller for maximum flexibility
Sequence Memory
FunctionalPatterns
Main,Subr
CaptureMemory
Pin ZPin W Pin X Pin Y Pin …Pin …
FunctionalPatterns
Main,Subr
CaptureMemory
FunctionalPatterns
Main,Subr
CaptureMemory
FunctionalPatterns
Main,Subr
CaptureMemory
Scan Memory Pool
Sea of Memory
July 2003 13NPTest Confidential Information
D-4032 Digital Instrument
DUT I/F
PE ICs
Timing GeneratorsFormatters
Sequence ControlAPG
Mem Manager
Bus Communications
DC-DC Power
PMU Module
TMU Module
HVPE
Levels Gen.PPMU
Sea of Mem2Gbit – Standard4Gbit – Upgrade8Gbit - Upgrade
DC Instruments
July 2003 15NPTest Confidential Information
6A-DPS Instrument Key Features
• 8 x 6A-DPS channels in 1 test-head slot• Voltage range: -7V to +7V• Gangable up to 40A per instrument
– 80A across 2 instruments
• Voltage loop regulation with remote sense (high & low sense)
• Range-optimized current measurement– High and Midrange current ranges– IDDQ and Low Current measurement (ILCM)
• Pattern trigger through local sequencer– IDDQ and other measure modes, or VBUMP
• Programmable current clamp modes– Hold at current limit, or Fold
• Internal PMU module for – DPS diagnostics and calibration – Continuity (open/short on power pins)
8 DPS channels
PMU
Bus I/F FPGA(over)
DC/DC (with cold plate)
July 2003 16NPTest Confidential Information
DPS Sequencer Capabilities
• Voltage Force VBUMP
– Switch from any voltage to any voltage, or increment up/down
• Current Measure– Single-shot mode– Average mode
• Number of samples: 2, 4, 8, 16, 32 or 64• Sampling interval: 20us to 1ms
– Scope mode: Up to 2046 measures– Max window width for current measure: 64ms
• GOTO opcode: jump to the specified sequencer line• NOOP opcode: for debug needs• Trigger modes for advancing through sequence:
– Static (CPU)– Dynamic (Pattern control)
• Interleave Vforce and measurement without constraint in one sequence
July 2003 17NPTest Confidential Information
100A-DPS Instrument
• Satisfies most aggressive power requirements of µProcessors and ASICs in the roadmap– Platform scalability across multiple applications and technology
nodes• One 100A instrument contains Two independent 50A DPS
channels– Designed for ganged performance (3V, 100A) per instrument– Uses 1 testhead slot
• Gangable by 2 or by 3 instruments for even higher currents• On-board metrology for calibration and diagnostics
HCDPS 0 HCDPS 1 HCDPS 2 HCDPS 3
50A-DPS 50A-DPS 50A-DPS 50A-DPS 50A-DPS 50A-DPS 50A-DPS 50A-DPS
100A-DPS 100A-DPS 100A-DPS 100A-DPS 200A-DPS 50A-DPS 50A-DPS 50A-DPS 50A-DPS
200A-DPS 100A-DPS 50A-DPS 50A-DPS
200A-DPS 100A-DPS 100A-DPS 200A-DPS 200A-DPS
300A-DPS 50A-DPS 50A-DPS
300A-DPS 100A-DPS
July 2003 18NPTest Confidential Information
HDD, DatacomHDD, Datacom
100BaseT100BaseTMicrocontroller & Automotive ADCsMicrocontroller & Automotive ADCs
HiFi Audio ADCs, DVD ComparatorHiFi Audio ADCs, DVD Comparator
ADSLADSL
STB I/QSTB I/QGigabit E’net,
DVD AFEGigabit E’net,
DVD AFE
Video ADCVideo ADCSTB IFSTB IF
Audio Prod’nAudio Prod’n
CellularBasebandCellularBaseband
Microcontroller & Automotive DACs
HiFi Audio DACs, DVD Comparator
ADSLAudio Prod’n STB IF
Gigabit E’net, DVD AFE
100BaseTHDD, Datacom
Video DAC
STB I/QCellularBaseband
Instrument Coverage by MXSL ApplicationR
esol
utio
n (b
its)
Res
olut
ion
(bits
)
2420
16
12
8
100GHz1GHz100MHz10MHz1MHz100KHz10KHz1KHz 10GHzMaximum Measure Bandwidth
Analog Measure Coverage
Analog Source Coverage
Maximum Update Rate
2420
16
12
8
100GHz1GHz100MHz10MHz1MHz100KHz10KHz1KHz 10GHz
RF tone frequency10MHz 100MHz 1GHz 10GHz
-110dB to +30dBm Multi-port RF 8GHz
QBIX -HA
QBIX -HF
QBIX -HA
QBIX-HF
GBS
UHF-AWG
MIX Option
MIX Option
July 2003 19NPTest Confidential Information
Sapphire Digital Capability Roadmap
2003 2004 2005Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2
Perf
orm
ance
D-4064
100/200/400 Mbps,(64), Single-ended ± 150ps EPA
Microcontrollers, “Lynx DFT”
3.2/6.4Gbps (16/8), Differential, ±20ps EPA
Characterization, Embedded clock
D-6408
D-4032
400/800Mbps (32/16), Single-ended, ±150ps EPA
PDAs, MPUs, chipsets, STB, DVD, “Jaguar DFT”
D-1616
MPU, DDR interface800/1600Mbps (32/16), Single-
ended, Source-sync, ± 30ps EPA
D-3208
1.6/3.2Gbps (16/8), Differential, Source-sync, ± 30ps EPA
HyperTransport, S-ATA, 3GIO, OC48, InfiniBand, SERDES
Q3 Q4
July 2003 20NPTest Confidential Information
Sapphire Digital Instrument Development Strategy
IsabelaJuana
ColumbusPEIC36
DC-DC
D-4064Dev
Cen
ter
: S
t-E
tien
ne
IsabelaJuana
DarwinR4X
PEIC36
DC-DC
D-4032
Dev Center : St-Etienne
IsabelaJuana
ColumbusF8X
PEIC5
DC-DC
D-1616
Dev Center : San-Jose
IsabelaJuana+SCID
ColumbusF8X
PEIC7
DC-DC
D-3208 Dev
Cen
ter
: S
an-J
ose
Isabela2Juana2+SCID2
ColumbusF8X
PEIC8
DC-DC
D-6408