Heat Transfer Engineering, 25(8):5–16, 2004Copyright C©© Taylor & Francis Inc.ISSN: 0145-7632 print / 1521-0537 onlineDOI: 10.1080/01457630490519772

Evaluation of Single PhaseFlow in Microchannels forHigh Heat Flux ChipCooling—ThermohydraulicPerformance Enhancementand Fabrication Technology

SATISH G. KANDLIKARDepartment of Mechanical Engineering, Rochester Institute of Technology, Rochester, New York

WILLIAM J. GRANDEDepartment of Microelectronic Engineering, Rochester Institute of Technology, Rochester, New York

The increased circuit density on today’s computer chips is reaching the heat dissipation limits forair-cooling technology. The direct liquid cooling of chips is being considered as a viable alternative.This paper reviews liquid cooling with internal flow channels in terms of technological options andchallenges. The possibilities presented herein indicate a four- to ten-fold increase in heat flux overthe air-cooled systems. The roadmap for single-phase cooling technology is presented to identifyresearch opportunities in meeting the cooling demands of future IC chips. The use ofthree-dimensional microchannels that incorporate either microstructures in the channel or groovesin the channel surfaces may lead to significant enhancements in single-phase cooling. A simplifiedand well-established fabrication process is described to fabricate both classes of three-dimensionalmicrochannels. Proof-of-concept microchannels are presented to demonstrate the efficacy of thefabrication process in fabricating complex microstructures within a microchannel.

A broad range of industries is driving the develop-ment of compact, advanced cooling technology. One ofthe most important of these applications is the removalof high heat fluxes in microelectronic circuitry. The con-

The first author acknowledges the IBM Faculty Award and the Mechan-ical Engineering Department for their valued support. The second authorgratefully acknowledges the invaluable assistance of Emil Piscani in the fab-rication of the prototype devices and the preparation of this manuscript. TheDean’s Office of the Kate Gleason College of Engineering at the RochesterInstitute of Technology is acknowledged for support of the fabrication work.The authors acknowledge support by NSF-MRI Award #ECS-0320869.

Address correspondence to Dr. Satish G. Kandlikar, Mechanical En-gineering Department, Rochester Institute of Technology, Rochester, NY14623. E-mail: sgkeme@rit.edu

tinuing push toward more densely packed microchipswill soon require greater thermal dissipation than canbe provided by simple forced air cooling. Liquid cool-ing using fluid channels integrated onto the microchipis the next most attractive alternative [1]. This approachoffers the advantages of a small footprint for packag-ing, reasonably low fluid flow rates, and potentiallylower operating temperatures. However, issues such asreliability and functionality have to be addressed be-fore microchannel cooling becomes widely adopted. Itshould also be recognized that unless a quantum leapin low-power device technology appears—analogous tothe displacement of bipolar junction transistors (BJT) by

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complementary metal-oxide-semiconductor (CMOS)transistors—the inexorable increases in device densitywill produce heat fluxes beyond what even forced liquidcooling can provide.

Since the accommodation of large heat flux dissipa-tion rates from a chip was demonstrated by Tuckermanand Pease [2] through the use of microchannel arrays,much of the research in the field has been focused onflow paths having constant cross-sections. Microchan-nel devices with simple rectangular, semi-circular, tri-angular, or trapezoidal shapes are readily fabricated andhave been extensively studied in the literature (e.g.,Nguyen and Wereley [3]). The performance improve-ment with small diameter channels was investigatedby Kandlikar and Grande [4], who showed perfor-mance improvements achievable with microchannels(defined as channels with 10 µm < Dh ≤ 200 µm).As the industry enters the era of microchannel cool-ing, it makes sense to investigate all possible perturba-tions and enhancements that will improve the perfor-mance of microchannel-based coolers and extend theirutility to the microelectronics industry for as long aspossible.

More geometrically complex microchannels may of-fer attractive performance advantages, but they have notbeen extensively investigated. In this paper, we evalu-ate the cooling limits of single-phase liquid cooling inplain channels and explore the use of three-dimensionalmicrochannel flow passages that incorporate a varietyof microstructures into the channels for heat transferenhancement. We refer to these as three-dimensionalmicrochannels because their cross-sectional geometryvaries along the flow length. Recently, a number of in-vestigators have explored the use of three-dimensionalmicrochannels. Complex serpentine flow channels forimproved passive mixing have been built using the two-sided wet chemical etching of silicon wafers (Liu et al.[5]). The geometry of the device, however, makes it in-compatible with integrated circuit cooling applications.Polymeric microchannels with corrugated walls havebeen analyzed and demonstrated for flow control andmixing by Stroock et al. [6, 7]. The materials of con-struction and the fabrication methods cannot be trans-lated into the chip cooling arena. Thus, it does not ap-pear that three-dimensional microchannels have beeninvestigated for high flux heat transfer applications, pos-sibly because of a limited understanding of their heattransfer and pressure drop characteristics and becauseof their increased fabrication complexity. In this paper,the requirements for high heat flux integrated circuitcooling are reviewed, the conventional engineering ap-proaches are examined, and several three-dimensionaldevice geometries that may offer important perfor-mance enhancements for microchannel-based high flux

cooling systems are further explored from a fabricationstandpoint.

OVERVIEW OF CURRENT CHIPCOOLING OPTIONS

Heat removal from IC chips has been a major lim-iting factor in the development of microprocessors forcomputer systems. Although aggressive cooling tech-nologies (such as compact heat exchanger passages orheat sinks with heat pipes) have been employed for spe-cific high-end computing systems, the workhorse for thevast majority of computer applications continues to beair-cooling technology.

Air cooling integrated circuit chips has been exten-sively used because of the following attractive features:good compatibility with the microelectronic circuit en-vironment, low auxiliary system support requirements,high reliability of the cooling system, low initial sys-tem cost, low operating and maintenance costs, andlong developmental history and experience. However,there are a number of shortcomings associated withair cooling systems, such as low power dissipation po-tential, fan noise, and operational difficulties in dustyenvironments.

The main concern for air-cooling systems is their lowheat removal potential. This arises from the low spe-cific heat of air, which requires larger mass flow ratesto achieve cooling. Moreover, the high specific volumeof air leads to very large volumetric flow rates and theirresulting high pumping costs and pressure drops creat-ing fans that can deliver large volumetric flow rates atrelatively large pressure heads without excessive noiselevels poses a major design challenge in the air moverdesign. A good discussion on the fluid selection for cool-ing with internal flow channels is given by [8].

The low heat transfer coefficients associated with air-cooling systems necessitate the use of heat spreaders inan effort to increase the heat transfer surface area forconvection. Figure 1 shows a schematic of an air-cooledsystem. Its equivalent thermal circuit is also shown. The

Figure 1 Schematic of an air-cooled chip with a heat spreader.

6 heat transfer engineering vol. 25 no. 8 2004

three main thermal resistances between the chip and theair are:

�Cement: thermal resistance of the cement used to bondthe chip to the heat spreader; also includes the contactresistances between the chip and the cement and thecement and the heat spreader.

�Heat Spreader: thermal resistance of the heat spreader.�Convection: thermal resistance due to convection be-

tween the fins and the air.

Significant efforts have been directed toward reduc-ing each of the three resistances. The heat spreader de-sign evolved from conduction in a copper base to athermosiphon loop transferring heat from the base tothe hollow extended surfaces. The convective resistancehas been reduced by increased air flow velocity, sur-face area, and heat transfer coefficient. The combinationof thermosiphon loops and compact air flow passages(with their higher pressure drop penalties) have madethe heat spreader and convective resistances quite low(e.g., 0.05◦C-cm2/W for a commercial finned unit).

In spite of the considerable research directed towardlowering the thermal resistance of the cement, it stillrepresents a major resistance in the thermal circuit. Theuse of specially formulated high conductivity cements,controlling their thickness to a very low value and pro-viding very smooth surfaces, has resulted in a �Cement

of as low as 0.1◦C-cm2/W. With a heat flux density of100 W/cm2, this translates into a 10◦C drop across thechip and the heat spreader. This value is quite large, con-sidering that the total temperature differential available(LMTD for single-phase flow) may be only 40–50◦C.

It becomes clear that increasing the allowable chippower dissipation rates will require considerable reduc-tions in the thermal resistance between the chip and theheat spreader. The requirements of a thick base of highthermal conductivity material for the heat spreader anda good bond between silicon and the heat spreader makeit difficult to lower �Cement any further.

Another major factor that limits further reduction inthe thickness of the thermal cement is the difference inthe thermal expansion coefficients for copper and thesilicon substrate. Reducing the cement thickness causesmuch higher thermal stresses in the silicon substrate,leading to its mechanical failure. Direct cooling of thechips completely eliminates the contact resistance andassociated thermal expansion problem. The incorpora-tion of parallel, high aspect ratio microchannels furtherincreases the convective heat transfer surface area andthe heat transfer coefficient. These and other issues as-sociated with direct liquid cooling are addressed, andthe channel geometrical design is discussed to serve asa guideline in the design of the coolant passages.

DIRECT COOLING WITH WATER—DESIGNCONSIDERATIONS

Direct circulation of a fluid in channels fabricated onthe chip eliminates altogether the thermal resistance as-sociated with the cement used in mounting heat sinks.In this regard, the superior thermal properties (highspecific heat, density, and thermal conductivity) of liq-uid water over refrigerants and air make it a desirablefluid for direct cooling. The incompatibility of waterwith electrical components can be overcome by usingthe back side of the chip for liquid flow passages. Al-though it is undesirable to subject the finished chips tomicrochannel fabrication from a manufacturing stand-point, improvements in the microchannel fabricationtechnology are expected to provide a very high yieldto keep the costs under control. Nakayama [9] clearlybrings out the superiority of direct water cooling, es-pecially in conjunction with microchannels. The use ofexternal heat sinks with liquid cooled microchannelshas also been extensively studied in the literature (e.g.,Missaggia et al. [10] and Bower et al. [11]).

Consider a chip that generates q watts and has its backsurface area Ac available for heat dissipation. A simpleanalysis neglecting the conjugate effects in the substrateis performed to show the need for microchannel flowpassages. For circulating water in a rectangular channelformed on the back surface, as shown in Figure 2, theminimum heat transfer coefficient required to meet thedesign goal is given by:

h = q

AcθLMTD= q ′′

c

θLMTD(1)

where q ′′c is the heat flux at the chip surface and θLMTD is

the log-mean temperature difference between the chip

Figure 2 Top and cross-sectional views of the flow channel forwater utilizing the back surface of the chip for cooling.

heat transfer engineering vol. 25 no. 8 2004 7

Figure 3 The variation of the heat transfer coefficient with a gapsize for laminar flow of water in a rectangular flow channel with a25 mm width.

surface temperature, also assumed to be constant in thispreliminary system level analysis, and the water inletand outlet temperatures (Tw,i and Tw,o, respectively).

Figure 3 shows the variation of the heat transfer co-efficient h needed to meet the cooling requirement asa function of heat flux for a chip surface temperatureTc = 85◦C and water inlet and outlet temperatures ofTw,i = 20◦C and Tw,o = 40◦C, respectively. For a heatflux corresponding to 20 W/cm2 (∼50 W/in2), a heattransfer coefficient of around 3,677 W/m2◦C is needed,whereas for a heat flux of 200 W/cm2(∼ 500 W/in2),h = 36,770 W/m2◦C is needed.

Now consider the simple cooling system with waterflowing over the chip surface in a rectangular channel,as shown in Figure 2. To achieve the desired heat trans-fer coefficients, it is imperative that a small hydraulicdiameter channel be used. The flow in such small chan-nels is expected to be laminar. For a nominal channelwidth of 25 mm (∼1 inch) and a channel length L of25 mm, the variation of heat transfer coefficient with thegap height g is obtained by the following equations fora constant heat flux boundary condition. The actual di-mensions are chosen for illustrative purposes only andhave no effect on the result showing the need for mi-crochannel flow passages. The hydraulic diameter ofthe rectangular channel is given by:

Dh = 4 gw

2(g + w)(2)

where g is the gap between the chip surface and the topcover and w is the width of the channel (assumed to be25 mm). The Nusselt number for the constant heat fluxboundary condition is dependent on the channel aspectratio and is given by Kakac et al. [12]:

Nu = 8.235(1 − 2.0421α + 3.0853α2 − 2.4765α3

+ 1.0578α4 − 0.1861α5) (3)

Figure 4 The variation of the heat transfer coefficient with a gapsize g for laminar flow of water in a 25 mm-wide rectangularchannel.

where α is the channel aspect ratio, α = g/w. Theresulting heat transfer coefficient, h = Nu k/Dh , isplotted as a function of the gap g in Figure 4. The wa-ter properties are calculated at a mean temperature of57.5◦C. Although the actual heat transfer coefficient ishigher due to the developing flow conditions along thelength, the results presented in Figure 4 illustrate therelative magnitude of the heat transfer rates associatedwith plain channels.

It is seen from Figure 4 that a gap size on the order of1 mm yields a heat transfer coefficient of 2370 W/m2◦C,which corresponds to a heat flux of only 22 W/cm2, asseen from Figure 3. Reducing the gap size to 100 µmyields a heat transfer coefficient of 24,600 W/m2◦C,which corresponds to a heat flux of about 175 W/cm2

in Figure 3.Although providing rectangular cooling passages of

100 µm or smaller extends the chip power to over100 W/cm2, the pressure drop for water flowing throughthe rectangular cooling channel becomes quite large.The water flow rate increases directly with the chippower for the fixed water inlet and outlet temperatures,and is given by:

m = q

cp(Tw,o − Tw,i )(4)

The frictional pressure drop of water flowing through therectangular channel is given by the following equation:

�p = 2 f LρV 2

Dh(5)

where V is the mean flow velocity, L is the flow length,ρ is the fluid density, and f is the friction factor, whichdepends on the channel aspect ratio.

For laminar flow conditions, the product f · Re isgiven by the flowing equation (Kakac et al. [12]):

f · Re = 24(1 − 1.3553α + 1.9467α2 − 1.701α3

+ 0.9564α4 − 0.2537α5) (6)

8 heat transfer engineering vol. 25 no. 8 2004

Figure 5 The variation of pressure drop with a gap height forwater flow in a 25 mm-wide rectangular channel.

Figure 5 shows the frictional pressure drop for waterflow plotted as a function of the chip power, calculatedusing Eqs. (4) and (5). It is seen from Figure 5 thatthe pressure drop increases dramatically below 0.1 to0.2 mm gap sizes. For example, for 0.1 mm gap size,the pressure drop is close to 1 bar for q ′′ = 100 W/cm2.The high pressure drop is not desirable. Besides thepumping power considerations, the silicon chip, whichis generally 525–775 µm thick, may not be able to sus-tain the mechanical stresses.

NEED FOR MICROCHANNELSAND ENHANCEMENT

The cooling requirements of 100 W/cm2 and abovecannot be easily met with either air cooling or, as dis-cussed in the above section, with the simple water-cooling system shown in Figure 2. In order to meetthis requirement, we need to increase the product of hA,where h is the heat transfer coefficient and A is the heattransfer surface area. Since h is related to the channelhydraulic diameter, increasing the surface area A is an-other viable option. The heat transfer surface area Acan be increased by incorporating microchannels on thechip surface, as shown in Figure 6.

The flow characteristics of water inside the mi-crochannels are determined by the channel hydraulic di-ameter and cross-sectional area available for flow. Froma heat transfer perspective, a smaller channel hydraulic

Figure 6 Microchannel flow passages on a silicon chip.

diameter and larger channel surface area are favored.This leads to a large number of deep narrow channels,as shown in Figure 6. However, to accommodate thenecessary mass flow rate through the microchannels, alarge flow cross-sectional area is beneficial. A detailedanalysis for such channels is investigated by a numberof researchers, such as, Upadhye and Kandlikar [13].

As an example of potential area enhancement possi-bilities, consider the incorporation of simple pin fins ina square channel 300×300 µm in cross-section. Placingpin fins of 30 µm diameter and 60 µm height at a pitchof 60 µm over the base would provide an area enhance-ment ratio of 2.57 over a flat-bottomed channel. Suchenhancement structures are difficult and expensive tofabricate in macroscopic channels using conventionalmethods but can be easily manufactured in silicon mi-crochannels by standard microfabrication techniques.

As seen from the above discussion, the heat transfersurface area and channel hydraulic diameter directly af-fect the heat transfer performance, while the hydraulicdiameter and channel cross-sectional area affect thepressure drop. The desired feature is thus to have a largechannel cross-sectional area in conjunction with a highheat transfer coefficient. These requirements can be metwith the next generation of microchannels incorporatingsomewhat larger hydraulic diameters providing a largercross-sectional area, and using heat transfer enhance-ment features.

Single-phase enhancement technology has been ex-tensively investigated in the literature and is commonlyemployed in industry. Tao et al. [14] discuss differentheat transfer mechanisms associated with different en-hancement techniques in conventional sized channels.Bergles [15], in one of his recent summary articles on en-hancement technology, proposes combinations of var-ious enhancement strategies in the next generation ofenhancement techniques. Steinke and Kandlikar [16]present a summary of conventional single-phase en-hancement strategies for microchannel applications.

Various techniques have been utilized for single-phase heat transfer coefficient enhancements in lam-inar flows. After reviewing various enhancement ap-proaches, the following techniques seem to holdpromise in microchannel application:

• Increase in surface area through pin fins of circular,rectangular, or other streamlined cross-sections;

• Increase in surface area and heat transfer coefficientthrough interrupted and staggered strip-fin design, orany other advanced design similar to the compact heatexchanger surfaces;

• Increase in local heat transfer coefficient by breakingthe boundary layer through periodic flow constric-tions;

heat transfer engineering vol. 25 no. 8 2004 9

• Incorporation of grooves and ridges, at specified an-gles to the flow direction, to achieve heat transfer en-hancement similar to microfin tubes;

• Incorporation of mixing features to improve the mix-ing between the bulk of the flow and the fluid flowingadjacent to the channel walls.

The thermohydraulic performance evaluation interms of heat transfer and pressure drop characteristicsof various enhancement techniques is essential beforeimplementing them in practical devices. Such a studycan be undertaken by conducting numerical simulationusing CFD software, as well as through experimentalevaluation. In addition, micro-PIV techniques arerecommended to validate the flow characteristics fromnumerical code. Another major issue would be manu-facturing considerations using silicon microfabricationtechnology, which is discussed further in the nextsection.

From a microfabrication standpoint, the enhance-ment strategies listed above can be grouped into twodistinct classes of three-dimensional microchannel de-vices: those that require microstructures within thechannel itself and those that require microstructures orgrooves on the surfaces of microchannel walls. In theremainder of this work, a simplified fabrication processfor building both classes of devices will be described.Proof-of-concept prototypes were constructed to con-firm the utility of the process scheme.

DEEP REACTIVE ION ETCHING TECHNOLOGY

The need for deep, narrow flow channels requireshigh aspect ratio microfabrication technology. Reac-tive ion etching (RIE) techniques have served thesemiconductor industry since the early 1970s. RIE iscarried out in a capacitatively coupled parallel plateconfiguration and is simple, robust, and easy to main-tain. Unfortunately, while RIE can be tuned to producevertical structures, etch rates tend to be low, makingthe fabrication of deep channels an excessively time-consuming and expensive process. In the 1990s, a num-ber of advances emerged in high aspect ratio etch tech-nology. Of particular interest are the deep reactive ionetch (DRIE) processes, which combine high densityplasma reactor designs with effective methods to sup-press the erosion of the sidewalls. The most commer-cially prominent DRIE technique is the so-called Boschprocess, which was invented by Larmer and Schilp [17]and is readily available from several equipment man-ufacturers. The microfabricated channels described inthis work were etched in a standard DRIE tool. Thenovel multiple mask process developed and demon-

strated here should be easily adapted to any standardtool.

MICROSTRUCTURES WITHIN CHANNELS

The fabrication of microstructures formed withinthe microchannels is discussed first. The features con-sidered here all characteristically protrude from the“floors” of the channels.

The most straightforward method of producing struc-tures in microchannels is to use the same patterned maskmaterial that defines the edges of the microchannel it-self. The microstructures that are fabricated in this man-ner will have the general appearance shown in Figure 7,where the height of the features is equal to the depth ofthe channel. The possible geometries are virtually lim-itless, constrained only by lithographic and processingconsiderations. A few representative structures such asfins, posts, and T-shaped fins are depicted in the figure.The inset shows a top view of the device, and also howthe necessary etch mask would have to be lithographi-cally patterned. In addition to modifying the heat trans-fer characteristics, the structures within the channels canserve other purposes such as filtering, flow control, andstructural rigidity.

In the simple case of Figure 7, the height of the struc-tures in the channels is the same as the depth of the mi-crochannel. The tops of the features are coincident withthe unetched substrate surface. In a more complicated,related configuration, the structures in the channel donot all have to possess the same height. An example isshown in Figure 8, where for simplicity only a set offins is depicted.

It should be recognized that the geometrical free-dom to design microstructures of the arbitrary shapedescribed in Figure 7 applies equally to this case. Ad-ditionally, it is possible to have more than two different

Figure 7 A microchannel with a variety of structures in the chan-nel. The height of the structures is equal to the depth of the channel.The inset shows a top view.

10 heat transfer engineering vol. 25 no. 8 2004

Figure 8 A microchannel with finned structures of variousheights. The inset shows a top view.

heights to the structures in the microchannel. Indeed,the technique generalizes to an arbitrary number of dis-tinct structure heights, and it is possible to assign anyheight to any structure.

Fabrication Considerations

The microstructures shown in Figure 7 do not requirea fabrication sequence any more complex than that re-quired for simple microchannels. Such structures canbe realized by appropriately patterning the etch mask toinclude spatial information about both the features andthe channel walls.

Microstructures whose heights differ from the chan-nel depth, such as the short fins in Figure 8, requirea more complex fabrication sequence. There are sev-eral possible processing approaches. The conventionalmethod would be to use two cycles of lithographic pat-terning and etching, as illustrated in Figure 9. In thisprocessing sequence, a first etch produces trenches ofan intermediate depth. A second patterning step, shownin Figure 9(c), is necessary to define the shallow mi-crostructures. This is the most problematic part of theprocess for several reasons. Since it is desirable to leavethe first masking material in place, the choice of materialfor the second masking layer is subject to severe com-patibility constraints. The deposition process and thepatterning chemistries of the second mask layer cannotdegrade the first mask. An even more daunting chal-lenge is successfully photopatterning the second masklayer in the presence of severe topology. In realistic mi-crochannel heat transfer devices, the second mask layermay need to be aligned and patterned at the bottom ofa high aspect ratio channel several hundred microns indepth. This makes the fabrication of fine shallow struc-tures extremely difficult.

A technique called one-step two-level etching(OSTLE) offers a simpler approach (see Grande et al.

Figure 9 The conventional formation of shallow and deep fea-tures: (a) pattern mask to define deep features, (b) etch to an inter-mediate depth, (c) pattern mask to define shallow features, (d) etchto final depth, and (e) no masking layers.

[18]). The use of this well-established process providesa relatively inexpensive method of producing com-plex microchannel structures. As shown in Figure 10,OSTLE requires two distinct lithography steps that arecarried out sequentially before any significant topol-ogy is built up. The key to the technique is that in anion-assisted process such as DRIE, the wafer experi-ences both a physical as well as a chemical componentof attack. The physical etch component, caused by ionbombardment, produces a steady erosion of the etchmask. When fabricating simple features, such as thosein Figure 7, the etch mask is intended to protect theunderlying region of the substrate throughout the du-ration of the etching process. The erosion rate of themasking material, then, sets a minimum thickness forthe mask to ensure that it is never completely removed.In the OSTLE technique, features with different heightscan be produced by using two distinct masking lay-ers: one that is impermeable to the etch and anotherthat is erodible. The impermeable mask is thick enoughto protect the underlying substrate for the entire etchprocess. The mask may be thinned by ion bombard-ment, but it never disappears altogether. The erodiblemask, in contrast, is designed to ablate completely awayat the point in the etch process where the etch depthequals the intended height of the shallow features. The

heat transfer engineering vol. 25 no. 8 2004 11

Figure 10 The use of the OSTLE process: (a) erodible mask todefine shallow features, (b) impermeable mask to define deep fea-tures, (c) etch to depth, and (d) removal of masking layers.

shallow features are then preserved in height as contin-ued etching removes material from the top of the featureas quickly as from the base. The depth of the shallowfeatures is determined by the thickness and etch rateof the erodible mask material. In practice, the erodiblemask layer is usually patterned first and is only on the or-der of 1 µm thick. The impermeable mask can be easilypatterned in the presence of the erodible mask becausethe topographical step heights are small.

As depicted in Figure 10, the use of a single erodiblemask leads to the formation of features with two dif-ferent depths. It should be evident that OSTLE can begeneralized to produce any number of distinct featureheights with the application of multiple erodible masks.It should also be appreciated that the designer has com-plete freedom over the placement, shape, and height ofall microstructures formed in the channel.

Experimental Verification

The fabrication of microstructures within microchan-nels was demonstrated using rapid prototyping tech-niques. Experiments were carried out on 100 mm sili-con wafers that were patterned with simple transparencyphototools and etched in an ST Systems (STS) DRIEtool.

Figure 11 The silicon-to-SiO2 etch rate ratio as a function of RIEand ICP power. Other process parameters are: 130 sccm SF6, 85sccm C4F8, 12 sec etch cycle, 7 sec passivation cycle, and a pressurecontrol valve setting of 80.

Thermally grown silicon dioxide was used as theerodible mask. The etch rate ratio of silicon to silicondioxide is a strong function of all the process param-eters. Figure 11 illustrates the general behavior of theetch rate ratio with the reactive ion etch (RIE) power,which is applied to the sample platen, and the induc-tively coupled plasma (ICP) power, which produces thechamber plasma. Other process parameters, such as gasflow rates, pressure, loading conditions, and even theexact details of feature sizes will also affect the ratio.To illustrate the range of thicknesses of thermal oxiderequired to serve as an erodible mask, consider the dataof Figure 11 at typical etch conditions of 12 watts RIEpower and 600 watts of ICP power. At these settings,the etch rate ratio of silicon to silicon dioxide is ap-proximately 350. This means that shallow features witha height of 50 µm would require an erodible mask ofabout 0.14 µm thickness. Such a thin film should presentno topographical difficulties in the patterning of the im-permeable mask.

In our experimental work, the silicon dioxide layerwas grown using a standard wet oxide recipe to a thick-ness of 0.28 µm and then patterned using contact lithog-raphy and wet etching in buffered hydrofluoric acid.The impermeable mask was patterned using Shipley812 photoresist spun to a thickness of 1.15 µm. A pairof photomasks was designed with a variety of featuresincluding posts and fins and printed as a transparencyon an imagesetter (Grande [19]). After the patterning ofthe impermeable mask, a DRIE process was carried out.The ICP power and RIE power were 600 W and 12 W,respectively. Other process conditions were 130 sccmSF6, 85sccm C4F8, a 12 second etch cycle, a 7 secondpassivation cycle, and a pressure control valve settingof 78. The measured depth of the microchannels was

12 heat transfer engineering vol. 25 no. 8 2004

Figure 12 A scanning electron micrograph of posts within a mi-crochannel. Successive rows of posts are alternately tall and shallow.Tall posts are approximately 90 µm in height, equal to the depthof the microchannel. Shallow posts are approximately 60 µm inheight.

90 µm. The shallow features had a height of 60 µm. Theobserved etch rate ratio was 214. The disparity in etchrate ratio in this work versus the data of Figure 11 canbe attributed to a smaller pressure control valve setting,loading effects, and feature size differences. This dis-crepancy demonstrates that careful process control isnecessary to accurately hold target depths. Figure 12shows one of the resultant microchannels.

The microchannel shown in Figure 12 is 500 µmwide and approximately 90 µm deep. The repeated mi-crostructure pattern within the microchannel is a row offour posts inclined at 45◦ to the direction of flow. Theposts have a diameter of about 80 µm. It can be clearlyseen that the rows alternate between tall posts with aheight equal to the depth of the channel and shallowposts having a height of about 60 µm.

It should be noted that the height of the shallow struc-tures can be controlled over a very broad range. Thethermal growth of silicon dioxide is an extremely welldeveloped technology because of the material’s use asa gate dielectric in transistors. Current manufacturingprocesses can produce uniform thicknesses of thermaloxide down to a few nanometers (Sze [20]). At the lowerrange of the silicon-to-silicon dioxide etch selectivityshown in Figure 11, it should be possible to create shal-low features with heights on the order of a micron. At theother extreme, a 1 µm thick erodible mask coupled withhigh etch selectivity processing conditions could pro-duce shallow features of 500–600 µm height. Clearly,the shallow features can be tailored to range from di-mensions comparable to the microchannels themselvesdown to dimensions that look like controlled surfaceroughness.

MICROSTRUCTURES WITHIN THEMICROCHANNEL WALLS

In this section, we examine the use of structuresformed in the sidewalls as well as the floor of the mi-crochannels. The structures form grooves in the surfacesof the channels. Figure 13 illustrates several types ofstructures, including grooves perpendicular to the di-rection of flow, grooves inclined at 45◦ to the direction

Figure 13 Microchannels with structures formed in the sidewallsand floor of the channel: (a) straight grooves, (b) angled grooves,and (c) chevron-shaped corrugations. The insets provide top views.

heat transfer engineering vol. 25 no. 8 2004 13

Figure 14 A geometrical layout of mask materials for (a) mi-crostructures within microchannels, and (b) microstructures formedwithin the sidewalls of a microchannel.

of flow, and grooves that take on a chevron shape in thefloor of the channel and then extend vertically up thesidewalls.

Microstructures in the microchannel walls can befabricated in a manner very similar to that of the mi-crostructures in the previous section. The major differ-ence with this class of devices is that the microstruc-tures or grooves are always the deep features, and themicrochannel “floor” is produced by the shallow etch.Figure 14 shows how the impermeable and erodiblemask layers are patterned to achieve microstructureswithin the microchannel versus microstructures formedin the sidewalls.

Experimental Verification

The fabrication of microstructures within microchan-nel walls was also demonstrated using rapid prototyp-ing techniques; in fact, these features were produced onthe same wafer as the devices of the previous section.As seen in Figure 14b, the “floor” of the microchan-nel is the shallow etch feature defined by the erodiblemask, while the grooves in the “floor” are deeply etchedfeatures defined by open areas with no masking mate-rial. The grooves in the sidewalls extend vertically andare produced by a scalloped pattern in the imperme-able mask that defines the walls of the microchannel.Figure 15 shows a microchannel with chevron-shapedgrooves. The microchannel is 500 µm wide and approx-imately 30 µm deep. The chevron-shaped microstruc-tures are approximately 60 µm deep, as measured fromthe microchannel floor.

Figure 15 A scanning electron micrograph of a microchannelwith chevron-shaped grooves etched into the floor of the channel.The grooves extend vertically upwards at the sidewalls. The mi-crochannels are approximately 500 µm wide and 30 µm deep. Thegrooves are etched approximately 60 µm into the “floor” of thechannel.

DISCUSSION

Given the high level of understanding of single-phase heat transfer phenomena in plain and enhancedgeometries and the current status of microfabricationtechnology, a case can be made to seriously consider im-plementing enhancement features in microchannel flowpassages for high heat flux chip cooling. However, thereare a number of issues that must be addressed beforewidespread application of these techniques becomes areality.

Pressure Drop Considerations

The improvement in the thermal performance of en-hanced 3-D structures is accompanied by an increasein pressure drop. A careful analysis needs to be per-formed to evaluate the suitability of these structures forspecific applications with regard to the maximum allow-able system pressure as well as the size and cost consid-erations for the pumping system. Although the pressuredrops per unit length are higher, it is imperative thatthe microchannel heat exchangers will employ single-pass design with shorter passage lengths. The pump-ing power needs to be evaluated under a new paradigmthat addresses the benefits of single-phase microchan-nel cooling as opposed to the more complex systemsincorporating phase change and/or spray or jet cool-ing techniques. This paradigm shift is expected to besimilar to that experienced in automotive compact heatexchanger applications, where higher pressure drops areaccepted due to associated size and weight benefits overheat exchangers employing conventional size channels.

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Further, it is expected that incorporating smaller chan-nel lengths will permit the heat exchanger design withinthe specified design envelope.

Experimental Verification of Design

The development of specific 3-D structures poses an-other major challenge. Working from a design concept,preliminary CFD analysis would provide guidance inthis area. However, experimental verification is essentialto address issues such as flow maldistribution, entranceregion effects, variability introduced in the channel sizeand shape by the manufacturing process, substrate heatconduction, localized hot spots, fin efficiency, and lo-calized variation of heat transfer coefficients. It shouldbe emphasized here that heat transfer and pressure dropexperiments pose special measurement challenges, ashighlighted by Kandlikar [21].

Fouling Considerations

Although clean fluids will be employed, fouling dueto the interaction of various piping and pump materialswith silicon microstructures has not been investigated.This research is expected to set standards for cleanlinessand the additives required for reliable long-term perfor-mance of 3-D enhanced single-phase cooling systems.

Manufacturing Technology and Costs

Although incorporating 3-D silicon enhancementstructures is not expected to add significant costs to themicrofabrication process itself, the major cost consider-ation will be overall yield. It seems preferable to buildthe microchannel cooling passages after the microelec-tronic circuitry is completed, rather than at the beginningof the process. At this stage, wafers in process repre-sent high value, and the yield through the microchannelconstruction phase becomes critical. Manufacturing re-search will be required to demonstrate that issues such aswafer handling, increased wafer fragility, and backsideprocessing do not lead to unacceptable yield losses.

Comparison with Flow Boiling Systems

The single-phase cooling option is preferable to thetwo-phase (boiling) option because of increased com-plexities associated with the boiling systems. Further,the saturation temperature becomes an issue with water,and one is forced to employ subatmospheric pressuresfor IC chip cooling. Additional issues such as dissolved

gases, condensation equipment, nucleation site deac-tivation through fouling and hysteresis, need to be ad-dressed. Although the two-phase systems are inherentlycapable of removing high heat fluxes through the latentheat transport, enhanced 3-D structures may be effec-tive alternatives for intermediate heat fluxes, tentativelyin the 100–300 W/cm2 range.

CONCLUSIONS

Microchannel heat transfer applications have becomemore demanding in terms of performance and systemintegrability since the early 1980s. In this paper, theuse of engineered structures within microchannels hasbeen explored. The thermohydraulic benefits have beenexamined and realistic methods of fabrication have beendescribed. Fabrication methodologies for two specificclasses of devices, microchannels containing structureswithin the channel and those with grooves etched intothe channel walls, have been proposed. Both types ofdevices have been successfully built and presented.

NOMENCLATURE

A surface area, m2

cp specific heat, J/Kg KD diameter, mf friction factor, dimensionlessg gap height, mh heat transfer coefficient, W/m2 Kk thermal conductivity, W/m KL length, mm mass flow rate, kg/sn number of channels, dimensionlessNu Nusselt number, dimensionlessq power generation or heat removal rate, Wq ′′ heat flux, W/m2

Q volume flow rate, m3/sRe Reynolds number, dimensionlesst thickness, mT temperature, KV mean flow velocity, m/sw channel width, m

Greek Symbols

α channel aspect ratio, g/w dimensionless� thermal resistance, K/Wθ temperature difference, Kµ dynamic viscosity, kg/m sρ density of fluid, kg/m3

�p pressure drop, Pa

heat transfer engineering vol. 25 no. 8 2004 15

Subscripts and Superscripts

c chipw,i water inletw,o water outletLMTD log mean temperature difference

REFERENCES

[1] Schmidt, R., Challenges in Electronic Cooling: Opportu-nities for Enhanced Thermal Management Techniques—Microprocessor Liquid Cooled Minichannel Heat Sink, FirstInternational Conference on Microchannels and Minichan-nels, Rochester, NY, April 24–25, pp. 951–959, 2003.

[2] Tuckerman, D. B., and Pease, R. F., High Performance HeatSinking for VLSI, IEEE Electron. Dev. Lett., EDL-2, pp. 126–129, 1981.

[3] Nguyen, N.-T., and Wereley, S. T., Fundamentals and Appli-cations of Microfluidics, Artech House, Boston, MA, 2002.

[4] Kandlikar, S. G., and Grande, W. J., Evolution of MicrochannelFlow Passages—Thermohydraulic Performance and Fabrica-tion Technology, Heat Transfer Eng., vol. 24, pp. 3–17, 2003.

[5] Liu, R. H., Stremler, M. A., Sharp, K. V., Olsen, M. G.,Santiago, J. G., Adrian, R. J., Aref, H., and Beebe, D. J.,Passive Mixing in a Three-Dimensional Serpentine Mi-crochannel, J. Microelectromech. Syst., vol. 9, pp. 190–197,2000.

[6] Stroock, A. D., Dertinger, S. K., Whitesides, G. M., and Ajdari,A., Patterning Flows Using Grooved Surfaces, Anal. Chem.,vol. 74, pp. 5306–5312, 2002.

[7] Stroock, A. D., and Whitesides, G. M., Controlling Flows inMicrochannels with Patterned Surface Charge and Topology,Acc. Chem. Res., vol. 36, pp. 597–604, 2003.

[8] Incropera, F. P., Liquid Cooling of Electronic Devices bySingle-Phase Convection, John Wiley and Sons, Inc., NewYork, 1999.

[9] Nakayama, W., Enhanced Heat Transfer in Tight Space—A Frontier for Thermal Management of MicroelectronicEquipment, Enhanced Heat Transfer, vol. 6, pp. 121–133,1999.

[10] Missaggia, L. J., Walpole, J. N., Liau, Z. L., and Phillips, R. J.,Microchannel Heat Sinks for Two-Dimensional High-PowerDensity Diode Laser Arrays, IEEE J. Quantum Elect., vol. 25,pp. 1988–1989, 1989.

[11] Bower, C., Ortega, A., Skandakumaran, P., Vaidyanathan, R.,Green, C., and Phillips, T., Heat Transfer in Water-CooledSilicon Carbide Multichannel Heat Sinks for High PowerElectronic Application, Proc. IMECE ’03, 2003 ASME Inter-national Mechanical Engineering Congress and Exposition,Washington, DC, Nov. 16–21, 2003.

[12] Kakac, S., Shah, R. K., and Aung, W., Handbook of Single-phase Convective Heat Transfer, John Wiley and Sons, NewYork, 1987.

[13] Upadhye, H. R., and Kandlikar, S. G., Optimization of Mi-crochannel Geometry for Direct Chip Cooling, Second In-ternational Conference on Microchannels and Minichannels,Rochester, NY, June 17–19, pp. 679–685, 2004.

[14] Tao, W. Q., He, Y. L., Wang, Q. W., Qu, Z. G., and Song, F. Q.,A Unified Analysis on Enhancing Single Phase ConvectiveHeat Transfer with Field Synergy Principle, Int. J. Heat MassTran., vol. 45, pp. 4871–4879, 2002.

[15] Bergles, A. E., ExHFT for Fourth Generation Heat TransferTechnology, Exp. Therm. Fluid Sci., vol. 26, pp. 335–344,2002.

[16] Steinke, M. E., and Kandlikar, S. G., Single-phase Heat Trans-fer Enhancement Techniques in Microchannel and Minichan-nel Flows, Second International Conference on Microchannelsand Minichannels, Rochester, NY, June 17–19, pp. 141–148,2004.

[17] Larmer, F., and Schilp, P., Method of Anisotropically EtchingSilicon, German Patent No. DE 4,241,045, 1994.

[18] Grande, W. J., Braddock, W. D., Shealy, J. R., and Tang, C. L.,One-step Two-level Etching Technique for Monolithic Inte-grated Optics, Appl. Phys. Lett., vol. 51, pp. 2189–2191, 1987.

[19] Grande, W. J., Fabrication Technologies for Advanced HeatTransfer Applications, First International Conference on Mi-crochannels and Minichannels, Rochester, NY, April 24–25,pp. 215–222, 2003.

[20] Sze, S. M., Semiconductor Devices, Physics and Technology,2nd ed., John Wiley and Sons, Inc., Hoboken, NJ, 2002.

[21] Kandlikar, S. G., Microchannels and Minichannels—History,Terminology, Classification, and Current Research Needs,First International Conference on Microchannels andMinichannels, Rochester, NY, April 24–25, pp. 1–6, 2003.

Satish Kandlikar has been a professor in theMechanical Engineering Department at RIT forthe last twenty-two years. He received his Ph.D.from the Indian Institute of Technology inBombay in 1975 and has been a faculty mem-ber there before coming to RIT in 1980. His re-search is mainly focused on flow boiling. Afterinvestigating the flow boiling phenomenon froman empirical standpoint, which resulted in widelyaccepted correlations for different geometries, hestarted to look at the problem from a fundamen-

tal perspective. Using high-speed photography techniques, he demonstratedthat small bubbles are released at a high frequency under flow conditions.His current work involves stabilizing flow boiling in microchannels, inter-face mechanics during rapid evaporation, and advanced chip cooling withsingle-phase liquid flow. He has published over 100 journal and conferencepapers. He is the Heat in History Editor of Heat Transfer Engineering anda fellow member of ASME, and he has been the organizer of the two in-ternational conferences on Microchannels and Minichannels sponsored byASME. Visit www.rit.edu/∼taleme for further information and publications.

William J. Grande has worked in the field ofmicrofabrication for more than two decades. Hisresearch has centered on the fabrication tools,processes, and devices used in the areas ofIII-V lasers, optoelectronics, microsystems, andMEMS. He holds undergraduate degrees in Elec-trical and Chemical Engineering and an M.S. andPh.D. in Applied and Engineering Physics. He ex-pects to complete the M.B.A. in 2004. In 1999,after ten years of industrial research experienceat the IIT Research Institute and Kodak Research

Labs, he joined the Microelectronic Engineering faculty at the RochesterInstitute of Technology, where he expanded the curriculum and research ef-forts in Microsystems fabrication, particularly in the area of direct thick filmwriting. In 2004, Dr. Grande joined Ohmcraft, Inc. in Honeoye, New York, asDirector of Research and Business Development. Dr. Grande holds sixteenpatents and has several more pending. His research interests include novelmicrofabrication technologies, microfluidics, rapid prototyping, and nan-otechnology. In 2000, Dr. Grande founded Tiger Microsystems, Inc., whichspecializes in the commercialization of microsystem-based products.

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