Scalable Readout System · • Trigger rates up O(1 MHz /channel) • timing resolution O(1ns) •...

Scalable Readout System

6/19/2018 [email protected] 1

2018 system hardware

SRS system componentsa typical small system


DetectorGEM / MicroMega /…

Mesh trigger pickup, HV APIC

Frontend Concentrator (FEC)

Frontend Adapter (ADC, DVM)

Frontend links(HDMI, CAT6 ..)

Backend linksCAT6 up 10Gb, optical up 100 Gb

Readout UnitDTCC link, CTF, SRU, network switch

DAQOnline/Offline/Controls

Frontend hybridsAPV / VMM / …

CratesMini, Euro

SRS from APV to VMM


APV VMM

• Analogue

• 128 channels with single chip

• Embargo list countries

• 1/2 W per hybrid

• Cooling negligible

• No zero supression

• Max trigger rate O(5kHz / hybrid)

• Timing resolution O(5 ns)

• No clustering logic

• fixed preamp gain 65mV/fC

• fixed peaking time 50-80 ns

• Noise ca 2000 e- @ Cdet~ 50 pF

• Max. Cdet ~ 50 pF

• fixed CSA gain -> limited dyn. Range

• non-linearity over full dyn range

• Digital

• 128 channels with 2 chips

• No embargo

• 3W for 128 channel hybrid

• Cooling important

• Zero suppression

• Trigger rates up O(1 MHz /channel)

• timing resolution O(1ns)

• clustering logic

• 8 different preamp gains 0.5-16mV/fC

• 4 different peaking times 25- 200ns

• Noise ca 1200 e- @ Cdet ~ 50pF

• Max. Cdet~ 1nF

• large dynamic range

• linear over full dyn. range

new HRS connector


Production of 24 pilot hybrids VMM3a imminent

-VMM3a available for prototypes -new PCB’s expected this week

-Component mounting scheduled

-Wire bonding following

-glob-tobbing following

Adapters for the connector transitionPanasonic (130 pin obsolete) –> HRS(140 pin new )

Panasonic

HRS

HRS

Panasonic

5 March 2018 [email protected] 5

tbd whether flex or rigid PCB

auxiliary power connector


IPL-103-01-L-RA-K

mount only for auxiliary power.

Matches with cable connector

IPD1-03-S-K (with latch)

Auxiliary VMM power

connector

P2 = 1.8V -> IC5,6,7,9 ->1.2V

2x VMM: 1.8A

GND =middle pin

P1 = 3.3V ->IC8 -> 2.5V

FPGA/Flash: 0.1A

The Power AUX connector is

required for test purposes

or when voltage dropoff over HDMI

cables is an issue.

P2

P1GND

J2

access to analogue VMM signals

[email protected]

Monitoring output

Peak detector output

Time detector output

on MO: analogue

output selected

via control bit smx = 1

Oscilloscope with 1M termination

5 March 2018 7

M0

PD0

TDO

analogue MO signal output

for different pulser amplitudes

analogue readout via I2C ADCs


The analogue channels ( PTO,PDO, MO)

of each VMM chip can be read out via

two micropower 12 bit ADCs on the VMM3a

Hybrids.

These ADC’s allow to monitor

-pulser DAC (after multiplexer)

-threshold DAC

-band-gap reference

-VMM temperature sensor

-analogue pulse signal ch. 0-63

-analogue time ramp signals ch. 0-63

Access pins

PDO, PTO, MO

PDO,PTO,MO signals also accessible via 3

testpins, one for each VMM3 chip

I2C ADC’s on VMM3a hybrid

PDO,PTO, MO testpins

VMM U2 ( ch . 0-64)

PDO,PTO, MO testpins

VMM U3 ( ch 64-127)

Test charge using integrated test pulser


-A

Cin ~A*Cf

CT

Cdet

Cc

1M

VMM 1 channel

Cf

DAC

test pulserDV amplitude

DQT = 𝐶𝑇

1+𝐶𝑇

𝐶𝑖𝑛

DV ~ CT[ 1-𝐶𝑇𝐶𝑖𝑛

] DV

Cf = (charge-gain)-1

A ~ 104 (estimated)

Cin ~O(103..104) pFDV

𝐶𝑇

𝐶𝑖𝑛<< 1

Example:

For DAC = 0x190: DV = 284 mV

CT1 =0.3pF : DQT = 85 fC

CT2 =3 pF: DQT = 850 fC

DQT ~ CT *DVDQT

shaper

MO analogue shaper

output Upeak ~ DQT

U= DQT / Cf

measured on VMM3:DV[mV] = 0.5722* DAC + 55[mV]

clustering and channel direction


Self-triggered if

channel peak is

above discriminator.

Clustering mode:

enable neighboring

channel for readout.

Works also between

adjacent VMM

hybrids connected

via the SETTA and

SETTB connectors.

The direction of

channels is shown.

Note:

The channel

counting on

VMM hybrids

is inversed

with respect

to APV

hybrids

J2

J3

Master / Slave HDMI links


J2 = double BW Slave J3 = DIRECT mode Master

OR

double bandwidth mode

master cable to J3

slave cable to J2

J2J3

Frontend links:HDMI cables A-D(micro)* VMM hybrid to DVMcard or Powerbox

Twisted pair lines:

4 x shielded, 3Gbps twisted pairs

Data-1M (1,3) uplink, Data-2 MS (4,6) uplink

Controls (7,9) downlink, CLK (10,12) downlink

1 x shielded twisted pair (14,19) (Ethernet HDMI 1.4) = power P2

1 x pair ( I2C) (15 SCL downlink -16 SDA bidir)

Single lines:

1 x M/S (13 sense bidir )

1 x power (18 = P1)

6 x GND 2,5,8,11,17,shell


*max. 5m, like CERN SCEM 07.89.00.220.2

! pin assignments different on D side !

A

D

A

DVM cardFEC V6 adapter for VMM hybrids with autoswitch for Direct or Master/Slave mode

DIRECT mode: 5 m cable to 8 VMM hybrids J3 (max 1k ch)M/S mode: requires powerbox, long cables, 16 VMM hybrids J2 and J3 (2k ch)


RJ45 for CAT6 cable

(common clock and I2C) to Powerbox

SATA power cable from ATX

(only required for Direct mode)8 x HDMI link ports

DCDC convertersLED indicator Direct / Powerbox

Pushbutton VMM Power reset

Autoswitch relays: Direct <-> M/S

From ATX

+12V – 4A

(+5V)

+3V3 – 1.5A

LED 1 on PCB = 3V3 SATA OK

LED 3 on PCB = 12 V SATA OK

DVMcard for SRS digital frontends( VMM etc )

11/9/2017 [email protected] for GDD lab CERN 14

Photo DCARD prototype 2017

2018: revised version with M/S auto-selection

coming very soon

SATA power ( 30W for 8 hybrids)

from ATX power supply

DCDC converters

8 x HDMI – ports

up to 8 x HDMI 1.4 cables A-D

max 5m

HDMI ports

FEC

Virtex6SFP+

SFP+

DDR3

1 GbEthernet

(Single FEC)

Initial small systems ( max. 2k ch with 2 FECs in a Minicrate ) DIRECT frontend links 5m to DVMcards (no powerbox)

(max. 8 VMMs per DVM @ max. 5 m )

5 March 2018 [email protected]

15

2x RG45

DTCC 800Mbps

SRU, CTF

for multiple FECs)

Trig IN

NIM

Single EFC

VMM-M

VMM-M

VMM-M

VMM-M

VMM-M

VMM-M

VMM-M

VMM-M

DCDC

30W

ATX -SATARJ45

NIM

Out

Not used

Auto-switch = “DIRECT”

M/S =1on all lines

all cables connected to J3

all hybrids in Master mode M

FEC DVM

SRS Mini-crate

2019: scaling up (>2k ch, >5m) Powerbox - Master/Slave – 8-FEC/Eurocate – SRU*


* BW upgrade of SRU needed for more than 10 GBps

Large SRS systems( rack environment with SRU)


SRU in 1 U rack mounted box

Eurocrate with FEC cards

DTCC links ( CAT6 cables)

24 ports DTCC links

- 3 ports 5Gbps, 1 port 10 GBE

FPGA

LX240 Virtex6

Scaling beyond 10 Gbit


- Replace FPGAs ( like in SRU) by SoC multi-processors ( D.Pfeiffer et al )

- easier to program in C than in Verilog

- chip-integrated with multiple10 Git link protocols

- Insert large data buffers in Readout ( DDR3 etc) ( see talk Yan Huang )

- equilibrate trigger statistics ->smooth uplink

- allow for L2 triggering to reduce uplink BW

- Commercial “SRU-like” cards in uTCA crates with high BW backplanes (tbd)

- buy hardware & put effort into software

- Mux Optical FEC links ( 5-10 GBps) to uTCA crate(s) (tbd)

- use streaming concepts like adoped by

LHC experiment for 50-100Gbit data uplinks

Points for a very high BW SRU upgrade Project

FEC V6FEC V6* ‘Working Horse” SRS frontend concentrator


* designed 2013 by J.Toledo, UPV Valencia

- Virtex 6 FPGA with network support

- 2 x SFP+ ports, 5 Gbit each, J11 defaults to 1 GBE/UDP link

- NIM I/O and 2x RJ45 for DTCC links

- User I/O plug above SRS powerbus plug

- 3 x PCIe connectors for SRS adapter cards

- plugin-DDR3 memory 2 Gbyte

- reconfigurable firmware (JTAG) via SPI Flash

Photo DDR3 memory plugin

FEC V6 bottom side

New Firmware by Yan Huang: enable DDR3 event-buffer for VMM data

New SRS crates

• Eurocrate V1: 4 FEC + 1 CTF

• Eurocrate V2: 8 FEC + 1 CTF

• Minicrates AB => Minicrates ABC

C = 3rd slot for CTF


New 160W ATX adapter for SRS-> for new Euro- and Mini-crates


ATX 20W

ballast resistor

24 pin connector for

450W ATX power supply

New low-profile connection

On-off –reset switch

8 x LED

resettable PCT fuses

DC-DC generator for -5V@15W

Faston 15A power cable connectors for 8 SRS

Voltages as required by FEC, SRU etcOn-off remote connector

1V8 - 10A (orange LED)

3V3 - 10A (orange LED)

4V2 - 10A (red LED)

+5V -10A ( red LED)

+5V standby - 0.3A (green LED)

+12V0 - 0.5A (blue LED)

-12V0 - 0.3A (blue LED)

-5V0 - 5A (yellow LED)

New

New

New

New

New

New SRS V2 Eurocrate( 8 FECs up 16 k channels )

11/9/2017 [email protected] for GDD lab CERN 22

V1 : 4 FEC + 1 CTF slot:

1 x 450 W power supply

1 x new ATX adapter

V2 : 8 FEC + 1 CTF slot:

2 x 450 W power supply

2 x new ATX adapter

V2 Eurocrate

Photo V2 Eurocrate proto 2018

for ALICE Focal

Important: you must place a ventilator unit below

New Minicrate ABC


A,B slots for 2 FECs ( max 4k channels)

C slot and power for CTF ( common clock and trigger)

Remote Power on/off (coax cable )

Power panel (banana plugs for +12V,+5V,+3V3 )

CTF cardcommon clock and trigger for up 8 FECs

( see RD51 Miniweek Dec. 2017 WG5, Givi Sekhniaize )


CTF card is required for

SRS systems with > 1 FEC

- common clock and trigger

- same cable / pinout as SRU

- Eurocrate slot 9 reserved for CTF

- New Minicrate ABC slot C reserved for CTF

- External NIM or internal auto-trigger

- External LVDS clock ( LHC) or internal 40 MHz

New CTF V6 cards successfully tested

ready for production

APICpickup amplifier-shaper-trigger “NIM-IN-a-BOX”

see Miniweek Febr. 2018 WG5 H.Muller

User manual APIC V4.1:

https://indico.cern.ch/event/702782/contributions/2900690/attachments/1602340/2582632/APIC_V4.1_Manual_HM25032018.pdf

APIC summary features• CSA preamplifier preset to: 1mV/fC ( 0.5-2mV/fC via trimmer)

• CSA output: 2 ns max risetime, 50 OHM, +/- 3pC => +/- 3V, 1us fall-time

• Pole-Zero: asymptotic return to zero ( trimmer for externally connected CSA)

• Fast shaper default: tp =30ns, 50 OHM max 1V, 1M max 2V, pos. or neg.

• Slow shaper: tp = 400 ns, 50 OHM max 1V, 1M max 2V, pos. or neg.

• Shaper gain: 0.1 – 20 relative to CSA output

• Test pulse external: NIM 50 OHM, TTL @1M , LVTTL@ 50 OHM , 1kHz- 100kHz

• Test pulse internal: 187 fC pos an neg , tf=202ps, tr =608 ps

• Baseline +/- 150mV

• Trigger TOT/TBT: on slope of CSA, pos or neg, complementary 50 OHM NIM, 50 ns

• External Trigger Input=> 3 functions: 1 direct out, 2 gated with TOT, 3 gated with TBT

• Pulse stretcher on NIM trigger out 50 OHM NIM, 50-500ns

• Trigger Buzzer: from NIM trigger out

• Battery max 31Wh storage, good for 11 -21 h autonomous operation (depending on enabled units)


https://indico.cern.ch/event/702782/contributions/2900690/attachments/1602340/2582632/APIC_V4.1_Manual_HM25032018.pdf

Summary


• VMM frontend: 2nd life for SRS applications

• Major SRS hardware upgrades & developments done:

Hybrids, Connectors, FEC- Adapters, Crates,

CTF, Powerbox, APIC (HV and Trigger)

• Pending for larger systems: upgrade of SRU backend

Need developers and users for pilot systems

• VMM frontend: A 2nd life for SRS applications

• Major SRS hardware upgrades & developments

Hybrids, Connectors, FEC- Adapters, Crates,

CTF, Powerbox, APIC (HV and Trigger)

• Manpower & resources needed for Firmware & Software

• Larger systems: upgrade of SRU backend

• High rate systems: DDR buffering

Main issue:

developers and users for pilot systems


Auxiliary slides


VMM globtop revision

VMM ASICs on SRS hybrids are wire-bonded

globtop Epoxy adhesives are used to protect

the ASIC and to provide thermal flux for cooling

globtop on our VMM protoypes ( photo)

appears to have side-effects, may even be

responsible for defecting bond connections

New globtop adhesive better adapted

for large-surface ASICs and high thermal coefficient

just arrived and will be tested on next VMM3 hybrids


APIC V4.x new plugins being worked on

• HV plugin for MicroMegas:

generate +HV and -HV relative to GND

as alternative to already existing

+HV bias ( 10-100V) for Si Diodes

• External preamplifiers (powered by APIC)

low-noise preamps for high-Cdet Diodes

fast preamplifiers for pSEC applications

• Peakfinder (powered by APIC): digitization of fast

shaper peaks voltages by slow ADCs (Arduino etc)


Date post:	10-Oct-2020
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Scalable Readout System · • Trigger rates up O(1 MHz /channel) • timing resolution O(1ns) •...

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