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SCAN Testing
Sungho Kang
Yonsei University
2Computer Systems Lab.
YONSEI UNIVERSITY
IntroductionOutline
Introduction Scan Registers Scan Cell Scan Methodology Scan Length Partial Scan Design Rules Conclusion
3Computer Systems Lab.
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IntroductionScan
Scan is a test methodology that allows one to control and observe all internal nodes in a synchronous design
Application for finite state machines Combinational and sequential elements tested separately Logic Test Two mode operation
Normal mode Test mode
4Computer Systems Lab.
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IntroductionScan Design
Combinational
Q D
C
Q D
C
Q D
C
POPI
Clk
MUX0
MUX
MUX0
0
1
1
1
N/T_
Sin
Sout
5Computer Systems Lab.
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IntroductionScan Design
Huffman Model of Sequential Circuit
CombinationalCircuit
F/F
F/F
F/F
PrimaryOutputs
Primary Inputs
Clock
6Computer Systems Lab.
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IntroductionScan Design
Normal Mode
CombinationalCircuit
F/F
F/F
F/F
PrimaryOutputs
Primary Inputs
SCAN INSCAN OUTMODE
MUX
7Computer Systems Lab.
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IntroductionScan Design
Test Mode : Flush Test (shift test of scan path)
CombinationalCircuit
F/F
F/F
F/F
PrimaryOutputs
Primary Inputs
SCAN INSCAN OUT
MODE
MUX
8Computer Systems Lab.
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IntroductionScan Design
Test Mode : Scan in of a test vector
CombinationalCircuit
F/F
F/F
F/F
PrimaryOutputs
Primary Inputs
SCAN INSCAN OUT
MODE
MUX
9Computer Systems Lab.
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IntroductionScan Design
Test Mode : Apply the test vector to Pi and observe a response at PO
CombinationalCircuit
F/F
F/F
F/F
PrimaryOutputs
Primary Inputs
SCANINSCANOUT
MODE
MUX
10Computer Systems Lab.
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IntroductionScan Design
Test Mode : Capture response by a clock tick
CombinationalCircuit
F/F
F/F
F/F
PrimaryOutputs
Primary Inputs
SCANINSCANOUT
MODE
MUX
11Computer Systems Lab.
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IntroductionScan Design
Test Mode : Scan Out of a response
CombinationalCircuit
F/F
F/F
F/F
PrimaryOutputs
Primary Inputs
SCAN INSCAN OUT
MODE
MUX
12Computer Systems Lab.
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IntroductionScan Cell
A specialized FF or latch activated only when the design is in scan mode Allows data to be scanned in for control Allows data to be scanned out for observation
13Computer Systems Lab.
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IntroductionTest for Sequential Circuits
Flush Test Used in two-clock circuits Simultaneously activates both master clock and the scan clock in
the scan mode Inputs of 0 and 1 are successively applied at the scan register inp
ut Initialize FFs to 0 and shift 1 through FFs
Shift Test Used in both two-clock and single-clock circuits This test shift pattern of 0 and 1 through the shift register in the sc
an mode 00110011... sequence is shifted through FFs
14Computer Systems Lab.
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IntroductionScan Design Flow
Complete HDL Design using scan design rules Synthesize logic using the selected ASIC library Convert regular FFs to scan FFs
Use test synthesis program Connects the scan data in a serial chain and clocks
Use test synthesis program Generate test patterns automatically
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IntroductionScan Test Operation Loop
Put the chip into scan mode Shift data into scan chain through Scan in
While scanning in the next pattern through Scan in, scanning out the results through Scan out of the previous pattern
Apply the functional clock to latch responses into scan FFs
Perform above 2 steps for each test pattern
16Computer Systems Lab.
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IntroductionScan vs Conventional Test Methods
Scan Conventional
Test Generation Automatic Manual Vector Type Structural Functional
Test Coverage Extremely High Low to Medium Vector Set Minimal Large Test Time Short Long Tester Memory Minimal Large
17Computer Systems Lab.
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IntroductionAdvantages of Scan Design
Structured design is possible Can use combinational ATPG Significant reduction of test generation time High fault coverage, typically 99.5 Ease of fault diagnosis
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IntroductionDisadvantages of Scan Design
Additional circuitry is added to FF SCAN flip-flop is more expensive Additional chip area
Additional circuit pins Performance penalty
Increased propagation time Test time increase
Due to shift in and shift out Some designs are not easily realizable as scan designs Need to store Patterns
Motivation for BIST Inability to test circuits at full speed
Motivation for Delay Fault Testing
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Scan RegistersScan Registers
Simultaneous controllability and observability
Non-simultaneous controllability and observability
20Computer Systems Lab.
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Scan RegistersScan Registers
Non-simultaneous controllability and observability Load the scan register with test data by setting T2=1 and clocking
CK2 Drive the circuit to a predefined state with T1=0 Load Q2 into latch Q1 Inject signals into the circuit by setting T1=1 Observe OPs by setting T2=0 and clock CK2 once Scan out data by setting T2=1 and clocking CK2
21Computer Systems Lab.
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Scan RegistersScan Registers
Observability only
Combining many observation points
22Computer Systems Lab.
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Scan RegistersScan Registers
Controllability only
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Scan RegistersScan Design
Adding controllability and observability to a circuit To inject 0, an AND is used and to inject 1, an OR is used To inject 0 or 1, a MUX is used
24Computer Systems Lab.
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Scan RegistersScan Design
Controllability/Observability with scan chain The normal path from A to B is broken when B1=1 The top row of MUXs is used to inject data into a circuit from scan
register The lower row of MUXs is used for monitoring data within the circ
uit
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Scan RegistersFull Serial Scan
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Scan RegistersIsolated Serial Scan
Scan register is not in the normal data path Somewhat ad hoc since CPs and OPs is left up to the desi
gner
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Scan RegistersFull Isolated Scan
High overhead Support real time testing
A single test can be applied at the operational clock rate of the system
Support on-line testing Circuit can be tested while in normal operation
28Computer Systems Lab.
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Scan CellMultiplexed Data Flip-flop
Setting TE = 1 Shifting the test patterns from SI into the flip-flops Setting TE = 0 and after a sufficient time for combinationa
l logic to settle, checking the output values Applying a clock signal CLK Setting TE = 1 and shifting out the flip-flop contents via Q
29Computer Systems Lab.
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Scan CellTwo-port Dual-clock Flip-flop
Sometimes it is useful to separate the normal clock from scan clock
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Scan CellMultiplexed Data Shift Register Latch
It is often desirable to insure race-free operation by employing a two-phase non-overlapping clock
31Computer Systems Lab.
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Scan CellTwo-port Shift Register Latch
Avoid the delay introduced by the MUX LSSD
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Scan CellRaceless Two-port D Flip-flop
CLK : Control normal operation SK : Select scan data and control scan process
33Computer Systems Lab.
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Scan CellPolarity-hold Addressable Latch
Random access scan Since no shift operation occurs, a single latch per cell is s
ufficient Latches that are not addressed produce a scan-out value
of So = 1 The So output of all latches can be wired-ANDed together
to form the scan-out signal Sout
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Scan CellFASCAN
No delay in data path Additional MUX in clock path
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Scan MethodsScan/Set
Use generic isolated scan architecture Add to the circuit a shift register whose sole purpose is th
e shifting in and out of test data FFs(test purpose); Ls(system latches converted to 2-port latches) More overhead Possible to gate the latch contents into the test shift register durin
g normal system operation Possible to scan circuit nodes other than latch outputs into the te
st shift register
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Scan MethodsRandom Access Scan
Non-serial Scan
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Scan MethodsRandom Access Scan
Treat each one of the latch elements as a bit in memory Each bit in the memory has its own unique address, and it
has a port which can load data into the latches so that the contents of the latch can be observed
There is only one scan-in and one scan-out Addressing scheme which allows each latch to be
uniquely selected, so that it can be either controlled or observed.
Normal operation Scan clock is off
Only one latch receives the scan clock and that value is loaded into the latch.
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Scan MethodsLSSD
Level Sensitive Scan Design Level sensitive
If the steady state responses to any of the allowed input changes is independent of the transistor and wire delays in the network
Polarity-hold hazard-free level-sensitive latch When a clock is enabled, the state of latch is sensitive to the level
of the corresponding data input To obtain race-free operation, clocks are non-overlapping
Rules for LSSD hazard-free D latches should be used for all system bistables A two-phase latch FSM structure should be used The L1 and L2 latches should be interconnected in a scan path str
ucture
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Scan MethodsLSSD
Latch a
L1
Latch c
L1
Latch b
L2
L1
L2
A
A
AO
A
AO
Scan In
BA
DC
I
BA
C’A’CD
AI
B’
B
D: normal data, I: scan data, C: system clock, A: scan clock, B: slave clock
40Computer Systems Lab.
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Scan MethodsLSSD Double Latch Design
Both L1 and L2 participate in system function
L1
L2
L1
L2
L1
L2
L1
L2
L1
L2
O/Ps
I/Ps
Scanout
CK 1
CK 3
CK 2
SI
Com
bina
tiona
llo
gic
Com
bina
tiona
llo
gic
41Computer Systems Lab.
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Scan MethodsLSSD Double Latch Design
Test Sequence
Scan mode: apply AB clock pairs to load SRLs
Apply Primary Input stimuli
Measure Primary Output response (clocks off)
Capture state responses into SRL (eg: pulse C)
Scan mode: pulse B clock to copy L1 to L2.
Apply AB clock pairs to unload SRLs
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Scan MethodsLSSD Double Latch Design
Static Testing
Capture
End Scan in
B
AB
X
Y
C1
YX
C1
L1 L2 L1 L2
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Scan MethodsLSSD Single Latch Design
Only L1 is used in normal operation Very Expensive Eliminate races
L1
L2
L1
L2
L1
L2
L1
L2
L1
L2
O/Ps
I/Ps
Scanout
CK 4CK 1
CK 3
CK 2
SI
Com
bina
tiona
llo
gic
Com
bina
tiona
llo
gic
44Computer Systems Lab.
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Scan MethodsSRL with L2* Latch
Additional clock and clocked data port Significant reduction on silicon cost
DCK 1
SICK 3
L 1
L 2CK 2
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Scan MethodsSRL with L2* Latch
D = D1C = CK1
Q
Sin = D2A = CK2
D1 CK1D2 CK2
Q
D1 CK1D2 CK2
Q
DC
SinA
BD*C*
L1
L2
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Scan MethodsSingle Latch Design with L2* Latch
L 1
L 2
L 1
L 2
Data inputSystem clock CK 1
Scan inputShiftclock CK 3
System/shiftclock CK 2
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Scan MethodsAdvantages of LSSD
The correct operation of the logic network is independent of AC characteristics such as clock edge rise time and fall time
Network is combinational in nature as far as test generation and testing is concerned
The elimination of all hazards and races greatly simplifies both test generation and fault simulation
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Scan LengthMultiple Test Session
Test session Configuring scan paths and other logics Testing logic using scan test methodology
Together Mode The entire circuit can be tested by 100 test patterns with length of
12 100 X 12 = 1200 clock cycles
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Scan LengthMultiple Test Session
Separate Mode While C1 is being tested, C2, R3 and R4 are ignored To test C1, 8 X 100 cycles are required To test C2, 8 X 20 cycles are required Total 960 clock cycles
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Scan LengthMultiple Test Session
Overlapping Mode Initially, C1 and C2 can be combined and tested using 20 patterns
with length 12 12 X 20 cycles C2 is completely tested and C1 can be tested with remaining 80
patterns with length 8 8 X 80 cycles Total 880 clock cycles
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Partial ScanScan Shift Reduction
Target faults for each test vector If a test vector detects only a few faults, then a few FFs will be req
uired to be controlled or observed for the test vector Arrangement of FFs in the scan chain
If FFs which are frequently required to be controlled (observed) are located close to the scan input (output) line, a few scan shift operations are required
Order of test vectors Maximize the overlap between successive scan in pattern
s
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Partial ScanPartial Scan
Full scan is not always feasible Retains many advantages of full scan and reduces the co
st Exclude certain flip-flops
Fault coverage is a function of the number of scan FFs Main researches
Flip-flop selection Test length reduction Retiming
What do we lose in partial scan? Loss of fault coverage Difficult to automate in synthesis environments
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Partial ScanPartial Scan
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Partial ScanPartial Scan
How to choose scan FFs and non-scan FFs? Testability Analysis Structural Analysis ATPG Based Analysis
Used in conjunction with other schemes
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Partial ScanATPG Based Analysis
Begin with a fully scanned circuit and perform empirical evaluation for the removal of scan from each individual FF
Select one or more FFs with lowest scan desirability and delete them from the scan point set
Repeat the previous step until the phase change conditions are met
Run the ATPG system and, if the desired fault coverage is not achieved, select and add scan FFs using the pruned fault set until the desired coverage is achieved or the upperbound on the number of scanned FFs allowed is reached
Best results is obtained only when all test patterns for each fault are available
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Partial ScanTestability Analysis
Perform testability measure Based on the results, select FFs Continue the previous steps until upperbound on the num
ber of scanned FFs is selected Simple but low coverage
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Partial ScanTestability Analysis
SCOAP
CC0(Combinational 0 Controllability)
CC1(Combinational 1 Controllability)
CO(Combinational Observability)
SC0(Sequential 0 Controllability)
SC1(Sequential 1 Controllability)
SO(Sequential Observability)
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Partial ScanTestability Analysis
SCOAP
dab D Q
DFF
e
D QDFF
gfc G
AB
C
g
Node
abcdef
2
CC0
111222
5
CC1
111335
0
CO
444220
1
SC0
000010
2
SC1
000011
0
SO
222211
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Partial ScanStructural Analysis
Circuit
Circuit Graph
Partially Scanned Circuit
1 2
3
4 5 6
61
2
3
4 5
1 2
3
4 5 6
SCANIN SCANOUT
MODE
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Partial ScanStructural Analysis
Partial Scan Using I-Paths I-mode
A module S with input port X and output port Y has an identity mode (I-mode), denoted by IM( ) if S has a mode of operation in which the data on X is transferred to Y
Latches, registers, MUXs, busses, ALUs, etc. I-path
An identity transfer path (I-path) exists from output port X of module S1 to input port Y of module S2, denoted as IP( ), if data can be transferred unaltered, but possible delayed
Consists of a chain of modules, each of which has an I-mode
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Partial ScanStructural Analysis
I-mode example MUX
IM(MUX: ) ; x = 0 ; t = 10ns IM(MUX: ) ; x = 1 ; t = 10ns
ALUIM(ALU: ) ; x1x2 = 00 ; t = 20ns IM(ALU: ) ; x1x2 = 01 ; B=0; Cin=0
RegisterIM(ALU: ) ; t = 1 clock cycle
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Partial ScanTesting Using I-Paths
Example I-path exists from the output of the block C to input ports of R1, R2
and R3 I-path exists from output ports of R1, R2, R3 and R4 to input port of
C Assume that only one register can drive the bus at any one time and
a tristate driver is disabled when its control line is high Test process of C
Time Controls Operation t1-t32 Scan into R1 t33 Contents of R1 are loaded onto the bus Data on bus are loaded into R2 t34 Test pattern is applied to C Response from C is loaded into R3 is loaded onto the bus passes from bus through MUX and is loaded into R1
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Partial ScanTesting Using I-Paths
Example
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Partial ScanPartial Scan Using I-Paths
Design Problems Identifying a subset of registers to be included in the scan path Scheduling the testing of logic blocks Determining efficient ways to activate the control lines when
testing a block of logic Determining ways of organizing the scan paths to minimize the
time required to test the logic
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Partial ScanPartial Scan Using I-Paths
I-mode Parallel-to-parallel Parallel-to-serial Serial-to-parallel Serial-to-serial
Transfer-mode (T-mode) If an onto mapping exists between input port and output port of a
module T-path consists of a chain of modules having zero or more I-modes and at least one T-mode I-paths and T-paths are used for transmitting data from a scan
register to the input port of a block of logic to be tested Example
Array of inverters that maps the input vector X into NOT(X)
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Partial ScanPartial Scan Using I-Paths
Sensitized-mode (S-mode) If a module has a mode of operation such that an error in the data
at input port produces an error in the data at output port S-path consists of a chain of modules having zero or more I-
modes and at least one S-mode I-paths and S-paths are used for transmitting response to a scan
register or primary outputs Example
SUM = A+BIf B is held at any constant value, an error in A produces an
error in SUM
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Partial ScanStructural Analysis
BALLAST
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Partial ScanBALLAST
Structured Partial Scan Design A subset of storage cells is selected and made part of the
scan path so that the resulting circuit has a special balanced property
Although the resulting circuit is sequential, only combinational ATPG is required and complete coverage if all detectable faults can be achieved
Once a test pattern is shifted into the scan path, more than one normal system clock may be achieved before the test result is loaded into the scan path and subsequently shifted out
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Partial ScanBALLAST
Circuit Model Cloud : Maximal region of connected combinational logic A group of wires forms vacuous cloud if it connects the outputs of
one register directly to the inputs of anotherit represents primary inputs feeding the inputs of a registerit represents the outputs of a register that are primary outputs
Storage cells are clustered into registers as long as all storage cells share the same clock and controlC1, C2, C3 : Nonvacuous cloudsA1, A2, A3 : Vacuous clouds
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Partial ScanBALLAST
Balanced (B-structure) For any two clouds v1 and v2, all signal paths between v1 and v2
go through the same number of registers Nonbalanced Example
Unequal paths between C1 and C3 Self loop (unequal paths between C and itself)
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Partial ScanBALLAST
Test procedure Given a B-structure SB, its combinational equivalent CB is the co
mbinational circuit formed from SB by replacing each storage cell in SB by a wire
Depth d of SB is the largest number of registers on any path between any two clouds
Let T = {t1, … tn} be a complete test set for all detectable stuck at faults in CB
Each test pattern ti = {tia, tib } consists of two parts where tia is applied to PIs and tib is applied to PPIs
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Partial ScanBALLAST
Test procedure of SB Scan in the test pattern tib Apply tia to the primary inputs to S While holding tib at the PIs and tib in the scan path, clock the regi
sters in S, d times Place the scan path in its normal mode and clock it once Observe the value on the POs Simultaneously, scan out the results in the scan paths and scan in
t(I+1)b
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Partial ScanBALLAST
To test SB A pattern is shifted into the scan path R3 and R6 and held two
clock periods while a test pattern is also applied to the primary inputs A and B
After one clock period test results are captured in R1 and R2 After the second clock period test results are captured in R4 and
R5 Finally test results are captured in the scan path R3 and R6
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Partial ScanBALLAST
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Partial ScanBALLAST
Any single stuck fault that is detectable in the combinational logic in S is detectable by a test vector
Some additional test may be required to detect shorts between the I/O of storage cells
To select a minimal number of storage cells to be made part of scan path so that the resulting circuit is a balanced, is NP complete
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Partial ScanBALLAST Example
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Partial ScanBALLAST
Nonbalanced circuits may require sequential ATPG Example
Consider the fault b s-a-1 Fault b s-a-1 is redundant in combinational equivalent of the circui
t
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Partial ScanScan Chain Correlation
Unscanned flipflops are corrupted while test vectors are scanned in and while test outputs are scanned out
CombinationalCircuit
MUX
MODE
SCAN IN
SCAN OUT
PO’sPI’s n m
pp
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Partial ScanScan Chain Correlation
Solution : Separate clock
CombinationalCircuit
MUX
MODE
SCAN IN
SCAN OUT
PO’sPI’s n m
pp
C2
C1
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Partial ScanScan Chain Correlation
Solution : Additional logic
CombinationalCircuit
MUX
MODE
SCAN IN
SCAN OUT
PO’sPI’s n m
pp
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Partial ScanCost Free Scan
Use controllability of PIs to establish scan paths through combinational logic
Analyzing the circuit to determine all the cost-free scan FFs
Selecting the best input vector to establish the maximum number of cost-free scan FFs on the scan chain
Example Free scan path is established when X1=0 and X2=1
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Design RulesGeneral Scan Design Rules
Disable asynchronous clears and presets during scan (Required)
Most scan types require all asynchronous clears and presets for scan registers to be inactive in the scan mode, so that bits in the scan chain are not cleared as the scan chain is loaded
Eliminate internal tristate contention during scan (Required)
If internal busses do exist in the design, during scan mode the circuit can be put into a random state that may cause internal bus contention
Prevent multiple drivers Disable all drivers with the scan enable signal Add decoding logic to ensure that only one tristate enable
is turned on at any time
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Design RulesGeneral Scan Design Rules
Disable write signals for RAMs during scan (Required) Important to preserve the content of the RAMs, as well as
FIFOs and register files Disable W EN to the RAM with the SCAN EN Disable bidirectional output buffer during scan (Strongly
Recommended) During the scan mode, registers along the scan chain will
be toggled frequently, thus turning on and off the bidirectional buffers, causing undesirable current spikes
Avoid cross coupled NANDs or NORs (Strongly Recommended)
Timing simulation(Strongly Recommended) The shifting of data through the scan chain should be thor
oughly simulated to verify that there are no timing violations or internal bus contentions due to the scan operation
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Design RulesGeneral Scan Design Rules
No combinational Feedback Loops (Strongly Recommended)
Use multiple scan chains (Recommended) Test time is related to the length of scan chain The scan enable pin can be shared Multiple chains of different lengths are allowed
Scan chain loading using (Recommended) When fanout problem in Q Use lock-up latches (Recommended)
Lock-up latches may be necessary between the scan out and scan in of major blocks or when scan chains switches to a separate clock driver to avoid side effects of clock skew
Make RAMs reasonably controllable (Recommended) Fully synchronous Design (Recommended) No gated or internally generated clocks
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Design RulesFull Scan Design Rules
One clock rule (Required) All flip-flops must have the same clock, or effectively the same clo
ck When some clocks are not directly controllable from the PIs, the f
ull scan circuit will have to be treated as a sequential circuit
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Design RulesPartial Scan Design Rules
Minimize destructive FFs (Strongly Recommended) Destructive : Flip-flops in scan chain can be reset or clocked durin
g scan Example
The mux-scan design uses the same clock for the scan flip-flops as well as the non-scan flip-flops
FF3 and FF4 become destructive
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Design RulesPartial Scan Design Rules
Minimize destructive FFs (Strongly Recommended) Use load signal
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Design RulesPartial Scan Design Rules
Minimize destructive FFs (Strongly Recommended) Gating clock
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Design RulesPartial Scan Design Rules
Minimize destructive FFs (Strongly Recommended) Add a scan clock
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Design RulesPartial Scan Design Rules
Partial scan can be selected by submodules or branches of a clock tree (Strongly Recommended) Put an entire branch of the clock tree in the scan chain and multipl
ex that clock with a scan clock And leave flip-flops driven by another clock tree branch non-scan A higher degree of partial scan is required to achieve desired testa
bility
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Design RulesMUX Scan Design Rules
MUX scan chain
Directly controllable clock for scan flip-flops (Required) Internal clocks are not allowed to drive a scan flip-flop
unless it is multiplexed with a test clock during scan mode
Avoid destructive flip-flops (Highly Recommended)
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Design RulesDual-Phase Scan Clock Design
Two-phased scan clock scan chain
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Design RulesDual-Phase Scan Clock Design Rule
Disable system clock for scan registers during scan mode (Required) Incorrect clock-disabling circuitry
Keep internal clocks reasonably controllable (Highly Recommended)
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Design RulesDual Port Scan Design
Dual port scan chain
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Design RulesDual Port Scan Design Rules
Disable system clock for scan registers during scan mode (Required) Illegal scan chain connection
The Q output of a scan flip-flop can trigger another scan flip-flop, destroying the scan value at that flip-flop
Make sure that the signals driving the normal clocks CK of the scan flip-flops cannot toggle during the scan mode
Keep internal clocks reasonably controllable (Highly Recommended)