1 of 141/15
Schedulability-Driven Partitioning and Mapping for
Multi-Cluster Real-Time Systems
Paul Pop, Petru Eles, Zebo Peng, Viaceslav IzosimovEmbedded Systems Lab (ESLAB)
Linköping University, Sweden
2 of 142/15
...
...
Factory Systems
Heterogeneous Networks
Distributed Heterogeneous System
...
Heterogeneous NetworksMulti-Cluster Systems
...
NoCs
Automotive Electronics
...
3 of 143/15
Distributed Safety-Critical Applications
...
...
Gateway
Applications distributed over heterogeneous networks are difficult to... Analyze (guaranteeing timing constraints) Design (partitioning, mapping,
bus access optimization)
Applications distributed over the heterogeneous networks Reduce costs:
use resources efficiently Requirements:
close to sensors/actuators
[DATE’03]
This paper!
4 of 144/15
Outline
MotivationSystem architecture and application
model Scheduling for multi-clusters [DATE’03] Design optimization problems
Partitioning Mapping Bus access optimization
Branch and bound optimization strategy Experimental results Contributions and Message
5 of 145/15
S0 S1 S2 SG S0 S1 S2 SG
TDMA RoundCycle of two rounds
Slot
Time Triggered Protocol (TTP) Bus access scheme:
time-division multiple-access (TDMA) Schedule table located in each TTP
controller: message descriptor list (MEDL)
Controller Area Network (CAN) Priority bus, collision avoidance Highest priority message
wins the contention Priorities encoded in the frame
identifier
Hardware Architecture
Gateway
...
...
Time-triggered cluster Static cyclic scheduling Time-triggered protocol
Event-triggered cluster Fixed priority preemptive
scheduling Controller area network protocol
6 of 146/15
CPUNG
Out
CAN
TTP Controller
S1SG
Round2
P4P1
CPUN1
TTP ControllerMBI
CPU
MBI
CAN Controller
CPUN2 CAN Controller
T
m1m2m1
S1SG
Out
TTP
T
P2 P3
Out
N2
m3
m3
Software Architecture...
...
Time-triggered cluster
Event-triggered cluster
Gateway
7 of 147/15
Multi-Cluster Scheduling [DATE’03]Application,
Partitioning,Mapping,
ArchitectureTT Bus
Configuration Priorities
ScheduleTables
Responsetimes
StaticSchedulin
gMulti-Cluster Scheduling
Offsets
ResponseTimes Respons
eTime
Analysis
MultiClusterScheduling algorithm Schedulability analysis: communication delays through the gateway Scheduling: cannot be addressed separately for each cluster
8 of 148/15
Problem Formulation Input
System architecture Application Partial partitioning and mapping,
based on the designer’s experience
Application: set of process graphs
...
...
Architecture: Multi-cluster
Output Design implementation
such that the application is schedulable Partitioning for each un-partitioned process Mapping for each un-mapped process Priorities for ET messages TDMA slot sequence and sizes for the TT bus Priorities for ET processes Schedule table for TT messages
Partitioning andmappingCommunicationinfrastructureSchedulinginformation
9 of 149/15
P4
P5
P3 P6
P2
P1N1
Missed
(faster) N2
(slower) N3
Met
Motivational Example #1
N2 N3
TTC ETCN1
CAN
TTP
P3
P6P5
P4
P2P1P1P2P3P4
N1 N2X XX5070
4090X
P5 X 40
N3
P6
70XXXXX 40 X
P4
P5
P3 P6
P2
P1N1
P4
Preempted
(faster) N2
(slower) N3
Met
Met
Preemptionnot allowed
P3
P4 P4
P6
P5P2
P1N1
Preempted
(faster) N2
(slower) N3
MetMet
Deadline for P6
Deadline for P5
In which cluster to place process P4?
10 of 1410/15
P1N1
P3
TTP S2
N2
S3 SG SG S3 S1 SG
P2
Missed
S2 S3 S1m1
m2
N3
CAN
NG
N4
Motivational Example #2
P1 P3P2m1
m2 P1P2P3
N1 N220 XXX
40X
N4X50X
N3XX20
N3 N4
TTC ETCN2
CAN
TTP
N1 NG
Where to map process P2?
Met
P1N1
P3
TTP S2
T
CAN
N4 P2
NG
S2 SG S2 S3 S1 SG
T
S2 S3 S1
N4
N3
m1
m1
m2
m2
N2
Deadline
11 of 1411/15
Motivational Example #3
P1N1 P4
TTP S1
T
CAN
N2 P2
NG
SG m1 SG S1
T
m2
T
P3
T
S1 SGm4 S1SG m3
Round 4Missed
m1
m3
m2
m4
What are the priorities on ETC? Which slot should come first on the TTC?
P1P2P3P4
N1 N220 XXX40
40X20
P1
P4
P2 P3
m1 m2
m3 m4
N1 N2
TTCCAN
TTP
ETC
P1N1 P4
TTP S1
T
CAN
N2 P2
NG
SG m1 SG S1
T
m2
T
P3
T
S1 SGSG
Missed
m1
m2
m3
m4
m3 m4
P1N1 P4
TTP SG
T
CAN
N2 P2
NG
S1
T T
P3
S1 SGS1SG m4 m3
Met
Round 1m
2m
1
m4
m3
m1 m2
Deadline
12 of 1412/15
Optimization Strategy Multi-Cluster Configuration
1. Branch and Bound Partitioning and Mapping Branching rule Selection rule Bounding rule: lower bound
2. Bus Access Optimization Determines the slot sequence and lengths on the TTC,
message priorities on the ETC Greedy optimization heuristic
Straightforward solution Partitioning and mapping that balances the utilization of processors
and buses Could be produced by a designer without optimzation tools
13 of 1413/15
0%10%20%30%40%50%60%70%80%90%
100%
50 100 150 200 250
Experimental ResultsPe
rcen
tage
sche
dula
ble
appl
icatio
ns [%
]
Number of processes
Can we increase the number of schedulable applications?
Straightforwardsolution
Multi-clusterConfiguration
14 of 1414/15
Experimental Results, Cont.How time-consuming is our optimization strategy?
5
10
15
20
25
30
35
40
0
45
50 100 150 200 250
Aver
age
exec
utio
n tim
e [m
inut
es]
Number of processes
Multi-Cluster Configuration
Straightforwardsolution
Case study Vehicle cruise controller Distributed over the
TT and ET clusters
15 of 1415/15
Contributions and Message Contributions
Addressed design problems characteristic to multi-clusters Partitioning Mapping Bus Access Optimization
Proposed a branch and bound approach for optimization
Analysis and optimization methods areneeded for the efficient
implementation of applications distributed over interconnected
heterogeneous networks.