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Copyright © 2014, Arasan Chip Systems, Inc.Slide 1
SD 4.1
Total IP Solution
Zachi FriedmanSenior Director of Marketing
Arasan Chip Systems, Inc.
May 2014
Copyright © 2014, Arasan Chip Systems, Inc.Slide 2
Agenda
• SD 4.x Market Adoption Update
• SD 4.1 Technical Overview
• Arasan’s Total IP Solution for SD 4.1
• Demo / Video
• Questions & Answers
Copyright © 2014, Arasan Chip Systems, Inc.Slide 3
SD 4.x Market Adoption
New Cameras:• Fujifilm X-T1
New Devices:
UHS-II Card Readers:• Sandisk Extreme Pro
Copyright © 2014, Arasan Chip Systems, Inc.Slide 4
What is SD?
• Secure Digital (SD) is a non-volatile memory card format for use in portable devices
• introduced in 1999 as an evolutionary improvement over MultiMediaCards (MMC)
• Secure Digital standard is maintained by the SD Association (SDA)
Copyright © 2014, Arasan Chip Systems, Inc.Slide 5
SD Evolution & Roadmap
SD 4.0• Increased max transfer speed from 104MB/s to 312MB/s (UHS-II in
Half-Duplex mode)
SD 4.1• Added ADMA3 support• Available Now from Arasan!
SD 5.0• Spec is being defined by SD Association• No speed increase• Fine tune and optimize for 1080p / 4K Video Recording
Copyright © 2014, Arasan Chip Systems, Inc.Slide 6
Trends in Standards & Specs
Time
# of Standards
Decreasing TimeBetween Standard Revs
Gpbs
AnalogDigital Increasing
Performance
Copyright © 2014, Arasan Chip Systems, Inc.Slide 7
Processor
Application
Device Driver
NAND flash
SD4.1 Host & Device Block Diagram
6/26/2013
Syst
em In
terf
ace
DM
A
Clock / PowerManagement
BlockBuffer
UHS-II Interface Controller
UHS-I Interface
UH
S-II
SD-T
RAN
CM-T
RAN
LIN
K
Pro
cess
or
(AR
M)
AH
Bm
em
ory
Hos
t Int
erfa
ce(M
aste
r / T
arge
t)
SD3.0/SD4.1Host Register
Hos
t DM
A(S
DM
A/AD
MA3
)
Clock / PowerManagement
BlockBuffer
UHS-II Interface Controller
SD/SDIO/eMMC Interface Control (CMD/DAT/RES)
UH
S-II
SD-T
RAN
CM-T
RAN
LIN
K
SD Bus
RCLK +/-
D0 +/-
D1 +/-
Register
SD4.1 / eMMC5.0 Host SD4.1 Device
Copyright © 2014, Arasan Chip Systems, Inc.Slide 8
SD4.1 Host Controller IP Core
• Backward Compatible to SD3
• AXI / AHB / OCP system bus (32/64 bit)
• Supports new differential serial interfaces• UHS-II FD156 – up to 1.56Gbps full duplex mode• UHS-II HD312 – up to 3.12Gbps half duplex mode
• Supports legacy SD bus interfaces• Default Speed mode: up to 25Mhz• High Speed mode: up to 50Mhz• UHS-I speed modes: SDR 12/25/50/104, DDR50
6/26/2013
Copyright © 2014, Arasan Chip Systems, Inc.Slide 9
UHS-II PHY Key Features
• Compliant to SD Part 1 Physical Layer Spec ver. 4.20
• Low Voltage Differential Transmitter & Receiver (230mVpp)
• High Data Rates: • 3.12Gbps in Half-Duplex mode• 1.56Gbps in Full-Duplex mode
• Low BER of 10-12 using 8b10b line coding
• Amplitude detectors on the receivers, Serializer and De-serializer
• Support for legacy features on RCLK pins
6/26/2013
Copyright © 2014, Arasan Chip Systems, Inc.Slide 10
UHS-II PHY Architecture (Analog)
• RCLK range: 26-52MHz• Data rates: 390 – 1,560 Mbps (Full-duplex)• Support for the optional Spread-Spectrum Clocking scheme• Lane D1 and D0 are universal (both transmit and receive)
PHY AFE
÷15 /÷30
Serializer
Tx PLL
DeserializerCDR
÷10
@rateCLK
10Recovered
Upstream Data
RefCLK
PCLK
m
10DownstreamData
PHY AFE
Serializer
Deserializer
CDR
÷10@rate CLK
Upstream Data
RCLK
10
DownstreamData
RCLK
D0
D1
10
Host UHS-II Device UHS-II
Copyright © 2014, Arasan Chip Systems, Inc.Slide 11
Arasan Provides End-End Solutions
• Analog IP – Lowest power & silicon size• GDS-II for customer specific process
technology • Full on-chip testability
• Digital IP – Easy integration to SoC• Delivered as RTL • Verification IP and synthesis scripts
• Verification IP – Enables low risk design• Verilog simulation environment with a
comprehensive test suite
• Full software stacks accelerates design• Bus interface layer, low level driver, protocol
stack and API’s
• Hardware Validation Platform • Full-speed emulation of host/device • Early software development platform
Copyright © 2014, Arasan Chip Systems, Inc.Slide 12
Mobile Storage Total IP Solution
Ara
san
SW
IP
Ara
san
Dev
ice
IP
Ara
san
Hos
t IP
OS / File System
Application SW
UFS SD/SDIO
SD/SDIO 4.1
Controller
UFS 2.0Controller
UHS II M-PHY
Software Stack
SD/SDIO 4.1
Controller
UFS 2.0 Controller
UHS IIM-PHY
ONFI 3.2controller
NV-DDR2 & Pads
eMMC 5.0Controller
eMMC
Standard Interfaces
Ara
san
Har
dwar
e V
alid
atio
n P
latfo
rm
Ara
san
Ver
ifica
tion
IP
ONFI 3.2controller
ONFI
eMMC 5.0Controller
NV-DDR2 & Pads
eMMC 5.0 Pads & DLL
eMMC 5.0 Pads & DLL
Copyright © 2014, Arasan Chip Systems, Inc.Slide 13
SD 4.1 Hardware Validation Platform
Transaction Layer
PHY
LINUX
Middleware
Protocol Stack
Low Level Device Driver
PCI-Xpress Bus Interface Layer
So
ftw
are
Sta
ck
IP H
ardw
are
Bitm
ap
API
API
Memory CPUPCIe Bus FPGA
X86 Motherboard SD 4.1 Host IP: FPGA Board
Daughter Card:SD 4.x Device
• Functions as SD 4.1 Host
• UHS-II Enabled (1.56Gbps Full-Duplex)
• Backward compatible to SD 3.0 / UHS-I
• Can be used as a “Gold Model”
Early validation
Software development
Production testing
Interoperability tests
Link Layer
Copyright © 2014, Arasan Chip Systems, Inc.Slide 14
SD 4.1 HVP – FPGA & Daughter Card
Copyright © 2014, Arasan Chip Systems, Inc.Slide 15
Availability
• Arasan has been an executive member in the SD Association since 2001
• Arasan is the leading IP provider for Mobile Storage• Storage solutions available: SD 4.1, eMMC 5.0, UFS 2.0, ONFI 3.2
• SD 4.1 Host and Device IP is shipping now
• UHS-II PHY is available now • Please contact us for more information on specific process technologies