SEMICONDUCTOR TECHNICAL DATA - pudn.comread.pudn.com/downloads150/ebook/648507/Pre-approval...

SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA

This document contains information on a product under development. Solomon Systech reserves the right to change or discontinue this product without notice. http://www.solomon-systech.com SSD2123 Rev 0.50 P 1/75 Mar 2008 Copyright 2008 Solomon Systech Limited

SSD2123

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480 x 272 RGB TFT LCD Driver Integrated Power Circuit, Gate and Source Driver

SSD2123 Rev 0.50 P 2/75 Mar 2008 Solomon Systech

CONTENTS

1 GENERAL DESCRIPTION ....................................................................................................... 6

2 FEATURES................................................................................................................................... 6

3 ORDERING INFORMATION ................................................................................................... 7

4 BLOCK DIAGRAM .................................................................................................................... 7

5 DIE PAD FLOOR PLAN ............................................................................................................ 8

6 PIN DESCRIPTION .................................................................................................................. 16

7 COMMAND TABLE ................................................................................................................. 21

8 COMMAND DESCRIPTION................................................................................................... 23

9 EXTENDED COMMAND DESCRIPTION............................................................................ 36

10 MTP PROGRAMMING/ ERASE......................................................................................... 39

11 GAMMA ADJUSTMENT FUNCTION ............................................................................... 43 11.1 STRUCTURE OF GRAYSCALE AMPLIFIER ..............................................................................................................44 11.2 GAMMA ADJUSTMENT REGISTER.........................................................................................................................46

11.2.1 Gradient adjusting register.........................................................................................................................46 11.2.2 Amplitude adjusting register.......................................................................................................................46 11.2.3 Micro adjusting register..............................................................................................................................46

11.3 LADDER RESISTOR / 8 TO 1 SELECTOR .................................................................................................................47 12 BLOCK FUNCTION DESCRIPTION................................................................................. 52

12.1 SERIAL INTERFACE ..............................................................................................................................................52 Serial Interface – 4-wires (8 bits) ...............................................................................................................................52 Serial Interface – 3-wires (9 bits) ...............................................................................................................................53 Serial Interface – 3-wires (24 bits) .............................................................................................................................54

12.2 DATA CONTROL...................................................................................................................................................55 12.3 BOOSTER AND REGULATOR CIRCUIT ...................................................................................................................55 12.4 SHIFT REGISTER...................................................................................................................................................55 12.5 DATA LATCHES ...................................................................................................................................................55 12.6 RESET CIRCUIT ....................................................................................................................................................55

13 DC CHARACTERISTICS..................................................................................................... 56

14 AC CHARACTERISTICS..................................................................................................... 57 14.1 DISPLAY SIGNAL OUTPUT TIMING ........................................................................................................................57 14.2 .................................................................................................................................................................................57 14.3 DISPLAY GENERAL INFORMATION.......................................................................................................................58 14.4 DISPLAY GENERAL INFORMATION.......................................................................................................................58 14.5 8-BIT SERIAL INTERFACE .....................................................................................................................................65 14.6 .................................................................................................................................................................................65 14.7 24-BIT RGB INTERFACE ......................................................................................................................................66

15 ITO RESISTANCE REQUIREMENT................................................................................. 67

16 SSD2123Z OUTPUT VOLTAGE RELATIONSHIP .......................................................... 68


17 INTERFACE MAPPING....................................................................................................... 69 17.1 MAPPING FOR WRITING AN INSTRUCTION ...........................................................................................................69 17.2 MAPPING FOR WRITING PIXEL DATA(S) ..............................................................................................................69

18 APPLICATION CIRCUIT .................................................................................................... 70

19 PACKAGE INFORMATION................................................................................................ 71 19.1 DIE TRAY DIMENSION .........................................................................................................................................71

20 MTP DETAIL ......................................................................................................................... 72


TABLES TABLE 3-1 : ORDERING INFORMATION ..................................................................................................................................7 TABLE 5-1: SSD2123 BUMP DIE PAD COORDINATES (BUMP CENTRE) .................................................................................9 TABLE 6-1: POWER SUPPLY PINS.........................................................................................................................................16 TABLE 6-2: INTERFACE LOGIC PINS.....................................................................................................................................18 TABLE 6-3: INTERFACE LOGIC PINS.....................................................................................................................................19 TABLE 6-4: DRIVER OUTPUT PINS .......................................................................................................................................20 TABLE 6-5: MISCELLANEOUS PINS ......................................................................................................................................20 TABLE 7-1: COMMAND TABLE AND POR (POWER ON RESET) VALUES ...............................................................................21 TABLE 7-2 – GAMMA REGISTERS POR VALUE ....................................................................................................................22 TABLE 10-1: MTP RE-WRITE CYCLE ...................................................................................................................................41


FIGURES FIGURE 4-1 : BLOCK DIAGRAM..............................................................................................................................................7 FIGURE 5-1 - DIE FLOOR PLAN (BUMP FACE UP) ...................................................................................................................8 FIGURE 8-1: LINE INVERSION AC DRIVER...........................................................................................................................25 FIGURE 10-1: MTP PROGRAMMING CIRCUITRY ...................................................................................................................39 FIGURE 10-2: MTP PROGRAMMING FLOWCHART................................................................................................................40 FIGURE 10-3: MTP ERASE CIRCUITRY.................................................................................................................................41 FIGURE 10-4: MTP ERASE FLOWCHART..............................................................................................................................42 FIGURE 14-1: GATE AND SOURCE OUTPUT TIMING (LINE INVERSION)..................................................................................57 FIGURE 14-2- EXAMPLE OF COLOR FILTER ARRANGEMENT .................................................................................................58 FIGURE 14-3- PIXEL CLOCK TIMING....................................................................................................................................58 FIGURE 14-4 COLOR MODE CONVERSION TIMING...............................................................................................................60 FIGURE 14-5 VGH OUTPUT AGAINST SHUT & RESB ........................................................................................................61 FIGURE 14-6 - POWER UP SEQUENCE ..................................................................................................................................62 FIGURE 14-7 - POWER DOWN SEQUENCE.............................................................................................................................63 FIGURE 14-8 - SPI INTERFACE TIMING DIAGRAM & TRANSACTION EXAMPLE....................................................................64 FIGURE 14-9 – 8-BIT SERIAL INTERFACE TIMING DIAGRAM & TRANSACTION EXAMPLE ....................................................65 FIGURE 14-10 – 24-BIT SERIAL INTERFACE TIMING DIAGRAM & TRANSACTION EXAMPLE ................................................66 FIGURE 16-1- LCD DRIVING VOLTAGE RELATIONSHIP .......................................................................................................68 FIGURE 18-1 - APPLICATION DIAGRAM...............................................................................................................................70


1 GENERAL DESCRIPTION

SSD2123 is an all in one driver that integrated the power circuits, gate driver and source driver into single chip. It can drive a 16.7M/262k/8 color a-TFT panel with resolution of 480 x 272 RGB.

SSD2123 embeds DC-DC Converter and Voltage generator to provide all necessary voltage required by the driver with minimum external components. A Common Voltage Generation Circuit is included to drive the TFT-display counter electrode. The driver supports three separated RGB Gamma settings. An Integrated Gamma Control Circuit is also included that can be adjusted by software commands to provide maximum flexibility and optimal display quality.

SSD2123 can be operated down to 1.6V and provide different power save modes. It is suitable for any portable battery-driven applications requiring long operation period with compact size.

2 FEATURES • 480 x 272 RGB single chip controller driver IC for 16.7M/262k/8 color amorphous TFT LCD • RGB color filter arrangement at Gate • Power Supply

- VDDIO = 1.6V – 3.6V (I/O Interface) - VCI = 2.5V – 3.6V (power supply for internal analog circuit)

• Output Voltages - Gate Driver:

VGH-GND = 6V ~ 18V VGL-GND = -6V ~ -15V VGH-VGL = 32Vp-p

- Source Driver: Source = VSS + 0.1 ~ AVDD - 0.1V Typical Source Output Voltage variation: ±30 mV

- VCOM drive: VCOMH = 2.5V ~ 6.0V VCOML = 0V ~ -3.0V VCOM amplitude = 6V (max) VCOMH in ~10mV resolution steps

• System Interface - Serial Peripheral Interface (SPI), 3 wire (9bit), 4 wire and SPID 24 bit interface

• Video interface - 24-bit RGB interface (DEN, DOTCLK, HSYNC, VSYNC, RR[7:0], BB[7:0], GG[7:0]) - 18-bit RGB interface (DEN, DOTCLK, HSYNC, VSYNC, RR[7:2], BB[7:2], GG[7:2]) - 8-bit serial RGB interface - 6-bit serial RGB interface

• Support low power consumption: - Low voltage supply - Low current sleep mode - 8-color display mode for power saving - Charge sharing function for switching circuits - Software settable for Shut and 8 color modes.

• Internal power supply circuit - Voltage generator - DC-DC converter up to +18/-12 or +15/-15 (VGH - VGL < 32V) - AVDD generator of 2x, 2.5x or 3x of VCI

• Support separate RGB gamma control • Support line / frame inversion • TFT storage capacitance: Cs on common • Support source and gate scan direction control • Built-in Non Volatile Memory (MTP) for VCOM calibration


3 ORDERING INFORMATION

Table 3-1 : Ordering Information

Ordering Part Number Package Form SSD2123Z COG

4 BLOCK DIAGRAM

Figure 4-1 : Block Diagram

Booster Circuit

CXN CXP C11N C11P C12N C12P C13N C13P C1N C1P C2N C2P C3N C3P

VCORE/VREGC/VDDIO

VGH VGL

Gate Driver

Regulator

Circuit

Source driver

Switches Network

Data Latches

Gamma / Grayscale

Voltage Generator

Data Control

VCOM

VLCD

BB

[7:0

]

GG

[7:0

]

RR

[7:0

]

DEN

DO

TCLK

HSY

NC

VS

YN

C

RL

SRG

B

BGR

RE

V

STY

PE

[1,0

]

X40

0

S0 to S479

Shift Registers

TB

Shift Registers

Serial Interface

RE

S

CS

SC

L

SD

I

SDO

G0 to G815

SHUT

VCI/VCIP

VSS/VSSRC/ AVSS/VCHS

Regulator

Circuit CM


5 DIE PAD FLOOR PLAN

Figure 5-1 - Die Floor Plan (Bump face up)

Die Information: Die Size: 23850 x 730 µm2 Die Thickness: 304 ± 25µm Bump Height: 15 µm (Typ.) Bump Co-planarity: ≤ 2 µm within die Bump Size 1: 50 x 80 µm2 (IO pad, Pad 1-333) Pad Pitch 1: 70 µm Bump Size 2: 50 x 100 µm2 (Dummy pad, Pad 334-

335, 1639-1640) Pad Pitch 2: 53 µm Bump Size 3: 17 x 100 µm2 (G/S pad, Pad 336-1638) Pad Pitch 3: 18 µm

Output Pad Pitch:

Dum

my

Dum

my

G0

G2

G4

G8

G10

25

1867 3653 19 10

0 10

0

G6

Die C

enter (0,0)x

y

* Diagram is not to scale

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :::: : :

Pin 1

Pin 334

Pin 333

Pin 1640

15

10

Center: (-11785, 25) Size: 75 x 75 µm2

25 25 25

15

10

Center: (11785, 25) Size: 75 x 75 µm2

25 25 25

50Center: (-11785, -299) Size: 50 x 50 µm2

50 Center: (11785, -299) Size: 50 x 50 µm2

50


Table 5-1: SSD2123 Bump Die Pad Coordinates (Bump Centre)

Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos1 NC -11620 -299 65 VGH -7140 -299 129 C12N -2660 -299 193 VCOMH 1820 -2992 NC -11550 -299 66 VGH -7070 -299 130 C12N -2590 -299 194 VCOMH 1890 -2993 VGH -11480 -299 67 VGH -7000 -299 131 C12N -2520 -299 195 VCOMH 1960 -2994 VGH -11410 -299 68 VGH -6930 -299 132 C12N -2450 -299 196 NC 2030 -2995 VSS -11340 -299 69 VGH -6860 -299 133 C12N -2380 -299 197 AVSS 2100 -2996 VSS -11270 -299 70 VCHS -6790 -299 134 C13P -2310 -299 198 AVSS 2170 -2997 VLCD255 -11200 -299 71 VCHS -6720 -299 135 C13P -2240 -299 199 AVSS 2240 -2998 VLCD255 -11130 -299 72 VCHS -6650 -299 136 C13P -2170 -299 200 AVSS 2310 -2999 VLCD255 -11060 -299 73 VCHS -6580 -299 137 C13P -2100 -299 201 VSS 2380 -299

10 VLCD255 -10990 -299 74 VCHS -6510 -299 138 C13N -2030 -299 202 NC 2450 -29911 VSSRC -10920 -299 75 VCHS -6440 -299 139 C13N -1960 -299 203 NC 2520 -29912 VSSRC -10850 -299 76 VCHS -6370 -299 140 C13N -1890 -299 204 NC 2590 -29913 VCIP -10780 -299 77 VCHS -6300 -299 141 C13N -1820 -299 205 NC 2660 -29914 VCIP -10710 -299 78 VCHS -6230 -299 142 CXP -1750 -299 206 NC 2730 -29915 TESTA -10640 -299 79 VCHS -6160 -299 143 CXP -1680 -299 207 NC 2800 -29916 TESTB -10570 -299 80 VCHS -6090 -299 144 CXP -1610 -299 208 VSS 2870 -29917 VSS -10500 -299 81 VCHS -6020 -299 145 CXP -1540 -299 209 NC 2940 -29918 NC -10430 -299 82 VCHS -5950 -299 146 CXN -1470 -299 210 NC 3010 -29919 NC -10360 -299 83 AVDDG -5880 -299 147 CXN -1400 -299 211 NC 3080 -29920 NC -10290 -299 84 AVDDG -5810 -299 148 CXN -1330 -299 212 NC 3150 -29921 NC -10220 -299 85 AVDDG -5740 -299 149 CXN -1260 -299 213 NC 3220 -29922 NC -10150 -299 86 AVDDG -5670 -299 150 VCIM -1190 -299 214 VSS 3290 -29923 NC -10080 -299 87 AVDDG -5600 -299 151 VCIM -1120 -299 215 CSSRC 3360 -29924 AVSS -10010 -299 88 AVDDG -5530 -299 152 VCIM -1050 -299 216 CSSRC 3430 -29925 AVSS -9940 -299 89 AVDDG -5460 -299 153 VCIM -980 -299 217 CSSRC 3500 -29926 AVSS -9870 -299 90 AVDDG -5390 -299 154 VCOM -910 -299 218 AVSS 3570 -29927 AVSS -9800 -299 91 AVDD -5320 -299 155 VCOM -840 -299 219 AVSS 3640 -29928 VGL -9730 -299 92 AVDD -5250 -299 156 VCOM -770 -299 220 VCI 3710 -29929 VGL -9660 -299 93 AVDD -5180 -299 157 VCOM -700 -299 221 VCI 3780 -29930 VGL -9590 -299 94 AVDD -5110 -299 158 VCOM -630 -299 222 VCI 3850 -29931 VGL -9520 -299 95 AVDD -5040 -299 159 VCOM -560 -299 223 VCORE 3920 -29932 VGL -9450 -299 96 AVDD -4970 -299 160 VCOM -490 -299 224 VCORE 3990 -29933 VGL -9380 -299 97 AVDD -4900 -299 161 VCOM -420 -299 225 VCORE 4060 -29934 C3P -9310 -299 98 AVDD -4830 -299 162 CSSRC -350 -299 226 VCORE 4130 -29935 C3P -9240 -299 99 AVDD -4760 -299 163 CSSRC -280 -299 227 VREGC 4200 -29936 C3P -9170 -299 100 C11P -4690 -299 164 CSSRC -210 -299 228 VREGC 4270 -29937 C3P -9100 -299 101 C11P -4620 -299 165 CSSRC -140 -299 229 VREGC 4340 -29938 C3P -9030 -299 102 C11P -4550 -299 166 CSSRC -70 -299 230 VREGC 4410 -29939 C3N -8960 -299 103 C11P -4480 -299 167 CSSRC 0 -299 231 VSS 4480 -29940 C3N -8890 -299 104 C11P -4410 -299 168 AVSS 70 -299 232 VSS 4550 -29941 C3N -8820 -299 105 C11P -4340 -299 169 AVSS 140 -299 233 VSS 4620 -29942 C3N -8750 -299 106 C11N -4270 -299 170 AVSS 210 -299 234 VDDIO 4690 -29943 C3N -8680 -299 107 C11N -4200 -299 171 AVSS 280 -299 235 VDDIO 4760 -29944 C2P -8610 -299 108 C11N -4130 -299 172 AVSS 350 -299 236 VDDIO 4830 -29945 C2P -8540 -299 109 C11N -4060 -299 173 AVSS 420 -299 237 VDDIO 4900 -29946 C2P -8470 -299 110 C11N -3990 -299 174 VCOML 490 -299 238 B7 4970 -29947 C2P -8400 -299 111 C11N -3920 -299 175 VCOML 560 -299 239 B6 5040 -29948 C2N -8330 -299 112 VCI -3850 -299 176 VCOML 630 -299 240 B5 5110 -29949 C2N -8260 -299 113 VCI -3780 -299 177 VCOML 700 -299 241 B4 5180 -29950 C2N -8190 -299 114 VCI -3710 -299 178 VCOML 770 -299 242 B3 5250 -29951 C2N -8120 -299 115 VCI -3640 -299 179 VCOML 840 -299 243 B2 5320 -29952 C1P -8050 -299 116 VCI -3570 -299 180 VCOML 910 -299 244 B1 5390 -29953 C1P -7980 -299 117 VCI -3500 -299 181 VCOML 980 -299 245 B0 5460 -29954 C1P -7910 -299 118 VCI -3430 -299 182 VCOML 1050 -299 246 VSS 5530 -29955 C1P -7840 -299 119 VCI -3360 -299 183 VCOML 1120 -299 247 G7 5600 -29956 C1N -7770 -299 120 VCI -3290 -299 184 VCOML 1190 -299 248 G6 5670 -29957 C1N -7700 -299 121 VCI -3220 -299 185 VCOMH 1260 -299 249 G5 5740 -29958 C1N -7630 -299 122 C12P -3150 -299 186 VCOMH 1330 -299 250 G4 5810 -29959 C1N -7560 -299 123 C12P -3080 -299 187 VCOMH 1400 -299 251 G3 5880 -29960 VGH -7490 -299 124 C12P -3010 -299 188 VCOMH 1470 -299 252 G2 5950 -29961 VGH -7420 -299 125 C12P -2940 -299 189 VCOMH 1540 -299 253 G1 6020 -29962 VGH -7350 -299 126 C12P -2870 -299 190 VCOMH 1610 -299 254 G0 6090 -29963 VGH -7280 -299 127 C12P -2800 -299 191 VCOMH 1680 -299 255 VSS 6160 -29964 VGH -7210 -299 128 C12N -2730 -299 192 VCOMH 1750 -299 256 R7 6230 -299


Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos257 R6 6300 -299 321 Dummy 10780 -299 385 G<99> 10836 282 449 G<227> 9684 282258 R5 6370 -299 322 Dummy 10850 -299 386 G<101> 10818 157 450 G<229> 9666 157259 R4 6440 -299 323 Dummy 10920 -299 387 G<103> 10800 282 451 G<231> 9648 282260 R3 6510 -299 324 Dummy 10990 -299 388 G<105> 10782 157 452 G<233> 9630 157261 R2 6580 -299 325 Dummy 11060 -299 389 G<107> 10764 282 453 G<235> 9612 282262 R1 6650 -299 326 Dummy 11130 -299 390 G<109> 10746 157 454 G<237> 9594 157263 R0 6720 -299 327 Dummy 11200 -299 391 G<111> 10728 282 455 G<239> 9576 282264 VSS 6790 -299 328 Dummy 11270 -299 392 G<113> 10710 157 456 G<241> 9558 157265 DOTCLK 6860 -299 329 Dummy 11340 -299 393 G<115> 10692 282 457 G<243> 9540 282266 DOTCLK 6930 -299 330 Dummy 11410 -299 394 G<117> 10674 157 458 G<245> 9522 157267 VDDIO 7000 -299 331 Dummy 11480 -299 395 G<119> 10656 282 459 G<247> 9504 282268 HSYNC 7070 -299 332 Dummy 11550 -299 396 G<121> 10638 157 460 G<249> 9486 157269 VSS 7140 -299 333 Dummy 11620 -299 397 G<123> 10620 282 461 G<251> 9468 282270 VSYNC 7210 -299 334 Dummy 11821.5 157 398 G<125> 10602 157 462 G<253> 9450 157271 VDDIO 7280 -299 335 Dummy 11768.5 282 399 G<127> 10584 282 463 G<255> 9432 282272 DEN 7350 -299 336 G<1> 11718 157 400 G<129> 10566 157 464 G<257> 9414 157273 VSS 7420 -299 337 G<3> 11700 282 401 G<131> 10548 282 465 G<259> 9396 282274 SDC 7490 -299 338 G<5> 11682 157 402 G<133> 10530 157 466 G<261> 9378 157275 SDI 7560 -299 339 G<7> 11664 282 403 G<135> 10512 282 467 G<263> 9360 282276 SCK 7630 -299 340 G<9> 11646 157 404 G<137> 10494 157 468 G<265> 9342 157277 CSB 7700 -299 341 G<11> 11628 282 405 G<139> 10476 282 469 G<267> 9324 282278 SDO 7770 -299 342 G<13> 11610 157 406 G<141> 10458 157 470 G<269> 9306 157279 VDDIO 7840 -299 343 G<15> 11592 282 407 G<143> 10440 282 471 G<271> 9288 282280 GPI3 7910 -299 344 G<17> 11574 157 408 G<145> 10422 157 472 G<273> 9270 157281 GPI2 7980 -299 345 G<19> 11556 282 409 G<147> 10404 282 473 G<275> 9252 282282 GPI1 8050 -299 346 G<21> 11538 157 410 G<149> 10386 157 474 G<277> 9234 157283 GPI0 8120 -299 347 G<23> 11520 282 411 G<151> 10368 282 475 G<279> 9216 282284 STYPE1 8190 -299 348 G<25> 11502 157 412 G<153> 10350 157 476 G<281> 9198 157285 STYPE0 8260 -299 349 G<27> 11484 282 413 G<155> 10332 282 477 G<283> 9180 282286 CM 8330 -299 350 G<29> 11466 157 414 G<157> 10314 157 478 G<285> 9162 157287 RESB 8400 -299 351 G<31> 11448 282 415 G<159> 10296 282 479 G<287> 9144 282288 SPID 8470 -299 352 G<33> 11430 157 416 G<161> 10278 157 480 G<289> 9126 157289 REV 8540 -299 353 G<35> 11412 282 417 G<163> 10260 282 481 G<291> 9108 282290 BGR 8610 -299 354 G<37> 11394 157 418 G<165> 10242 157 482 G<293> 9090 157291 TB 8680 -299 355 G<39> 11376 282 419 G<167> 10224 282 483 G<295> 9072 282292 RL 8750 -299 356 G<41> 11358 157 420 G<169> 10206 157 484 G<297> 9054 157293 SHUT 8820 -299 357 G<43> 11340 282 421 G<171> 10188 282 485 G<299> 9036 282294 GAMAS 8890 -299 358 G<45> 11322 157 422 G<173> 10170 157 486 G<301> 9018 157295 NC 8960 -299 359 G<47> 11304 282 423 G<175> 10152 282 487 G<303> 9000 282296 SRGB 9030 -299 360 G<49> 11286 157 424 G<177> 10134 157 488 G<305> 8982 157297 DENMODE 9100 -299 361 G<51> 11268 282 425 G<179> 10116 282 489 G<307> 8964 282298 X400 9170 -299 362 G<53> 11250 157 426 G<181> 10098 157 490 G<309> 8946 157299 VDDIO 9240 -299 363 G<55> 11232 282 427 G<183> 10080 282 491 G<311> 8928 282300 AVSS 9310 -299 364 G<57> 11214 157 428 G<185> 10062 157 492 G<313> 8910 157301 AVSS 9380 -299 365 G<59> 11196 282 429 G<187> 10044 282 493 G<315> 8892 282302 AVSS 9450 -299 366 G<61> 11178 157 430 G<189> 10026 157 494 G<317> 8874 157303 AVSS 9520 -299 367 G<63> 11160 282 431 G<191> 10008 282 495 G<319> 8856 282304 VCI 9590 -299 368 G<65> 11142 157 432 G<193> 9990 157 496 G<321> 8838 157305 VCI 9660 -299 369 G<67> 11124 282 433 G<195> 9972 282 497 G<323> 8820 282306 VCI 9730 -299 370 G<69> 11106 157 434 G<197> 9954 157 498 G<325> 8802 157307 VCI 9800 -299 371 G<71> 11088 282 435 G<199> 9936 282 499 G<327> 8784 282308 NC 9870 -299 372 G<73> 11070 157 436 G<201> 9918 157 500 G<329> 8766 157309 NC 9940 -299 373 G<75> 11052 282 437 G<203> 9900 282 501 G<331> 8748 282310 NC 10010 -299 374 G<77> 11034 157 438 G<205> 9882 157 502 G<333> 8730 157311 NC 10080 -299 375 G<79> 11016 282 439 G<207> 9864 282 503 G<335> 8712 282312 NC 10150 -299 376 G<81> 10998 157 440 G<209> 9846 157 504 G<337> 8694 157313 NC 10220 -299 377 G<83> 10980 282 441 G<211> 9828 282 505 G<339> 8676 282314 NC 10290 -299 378 G<85> 10962 157 442 G<213> 9810 157 506 G<341> 8658 157315 NC 10360 -299 379 G<87> 10944 282 443 G<215> 9792 282 507 G<343> 8640 282316 NC 10430 -299 380 G<89> 10926 157 444 G<217> 9774 157 508 G<345> 8622 157317 NC 10500 -299 381 G<91> 10908 282 445 G<219> 9756 282 509 G<347> 8604 282318 NC 10570 -299 382 G<93> 10890 157 446 G<221> 9738 157 510 G<349> 8586 157319 NC 10640 -299 383 G<95> 10872 282 447 G<223> 9720 282 511 G<351> 8568 282320 NC 10710 -299 384 G<97> 10854 157 448 G<225> 9702 157 512 G<353> 8550 157


Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos513 G<355> 8532 282 578 G<485> 7362 157 643 G<615> 6192 282 708 G<745> 5022 157514 G<357> 8514 157 579 G<487> 7344 282 644 G<617> 6174 157 709 G<747> 5004 282515 G<359> 8496 282 580 G<489> 7326 157 645 G<619> 6156 282 710 G<749> 4986 157516 G<361> 8478 157 581 G<491> 7308 282 646 G<621> 6138 157 711 G<751> 4968 282517 G<363> 8460 282 582 G<493> 7290 157 647 G<623> 6120 282 712 G<753> 4950 157518 G<365> 8442 157 583 G<495> 7272 282 648 G<625> 6102 157 713 G<755> 4932 282519 G<367> 8424 282 584 G<497> 7254 157 649 G<627> 6084 282 714 G<757> 4914 157520 G<369> 8406 157 585 G<499> 7236 282 650 G<629> 6066 157 715 G<759> 4896 282521 G<371> 8388 282 586 G<501> 7218 157 651 G<631> 6048 282 716 G<761> 4878 157522 G<373> 8370 157 587 G<503> 7200 282 652 G<633> 6030 157 717 G<763> 4860 282523 G<375> 8352 282 588 G<505> 7182 157 653 G<635> 6012 282 718 G<765> 4842 157524 G<377> 8334 157 589 G<507> 7164 282 654 G<637> 5994 157 719 G<767> 4824 282525 G<379> 8316 282 590 G<509> 7146 157 655 G<639> 5976 282 720 G<769> 4806 157526 G<381> 8298 157 591 G<511> 7128 282 656 G<641> 5958 157 721 G<771> 4788 282527 G<383> 8280 282 592 G<513> 7110 157 657 G<643> 5940 282 722 G<773> 4770 157528 G<385> 8262 157 593 G<515> 7092 282 658 G<645> 5922 157 723 G<775> 4752 282529 G<387> 8244 282 594 G<517> 7074 157 659 G<647> 5904 282 724 G<777> 4734 157530 G<389> 8226 157 595 G<519> 7056 282 660 G<649> 5886 157 725 G<779> 4716 282531 G<391> 8208 282 596 G<521> 7038 157 661 G<651> 5868 282 726 G<781> 4698 157532 G<393> 8190 157 597 G<523> 7020 282 662 G<653> 5850 157 727 G<783> 4680 282533 G<395> 8172 282 598 G<525> 7002 157 663 G<655> 5832 282 728 G<785> 4662 157534 G<397> 8154 157 599 G<527> 6984 282 664 G<657> 5814 157 729 G<787> 4644 282535 G<399> 8136 282 600 G<529> 6966 157 665 G<659> 5796 282 730 G<789> 4626 157536 G<401> 8118 157 601 G<531> 6948 282 666 G<661> 5778 157 731 G<791> 4608 282537 G<403> 8100 282 602 G<533> 6930 157 667 G<663> 5760 282 732 G<793> 4590 157538 G<405> 8082 157 603 G<535> 6912 282 668 G<665> 5742 157 733 G<795> 4572 282539 G<407> 8064 282 604 G<537> 6894 157 669 G<667> 5724 282 734 G<797> 4554 157540 G<409> 8046 157 605 G<539> 6876 282 670 G<669> 5706 157 735 G<799> 4536 282541 G<411> 8028 282 606 G<541> 6858 157 671 G<671> 5688 282 736 G<801> 4518 157542 G<413> 8010 157 607 G<543> 6840 282 672 G<673> 5670 157 737 G<803> 4500 282543 G<415> 7992 282 608 G<545> 6822 157 673 G<675> 5652 282 738 G<805> 4482 157544 G<417> 7974 157 609 G<547> 6804 282 674 G<677> 5634 157 739 G<807> 4464 282545 G<419> 7956 282 610 G<549> 6786 157 675 G<679> 5616 282 740 G<809> 4446 157546 G<421> 7938 157 611 G<551> 6768 282 676 G<681> 5598 157 741 G<811> 4428 282547 G<423> 7920 282 612 G<553> 6750 157 677 G<683> 5580 282 742 G<813> 4410 157548 G<425> 7902 157 613 G<555> 6732 282 678 G<685> 5562 157 743 G<815> 4392 282549 G<427> 7884 282 614 G<557> 6714 157 679 G<687> 5544 282 744 DUMMY 4374 157550 G<429> 7866 157 615 G<559> 6696 282 680 G<689> 5526 157 745 DUMMY 4356 282551 G<431> 7848 282 616 G<561> 6678 157 681 G<691> 5508 282 746 DUMMY 4338 157552 G<433> 7830 157 617 G<563> 6660 282 682 G<693> 5490 157 747 S<479> 4320 282553 G<435> 7812 282 618 G<565> 6642 157 683 G<695> 5472 282 748 S<478> 4302 157554 G<437> 7794 157 619 G<567> 6624 282 684 G<697> 5454 157 749 S<477> 4284 282555 G<439> 7776 282 620 G<569> 6606 157 685 G<699> 5436 282 750 S<476> 4266 157556 G<441> 7758 157 621 G<571> 6588 282 686 G<701> 5418 157 751 S<475> 4248 282557 G<443> 7740 282 622 G<573> 6570 157 687 G<703> 5400 282 752 S<474> 4230 157558 G<445> 7722 157 623 G<575> 6552 282 688 G<705> 5382 157 753 S<473> 4212 282559 G<447> 7704 282 624 G<577> 6534 157 689 G<707> 5364 282 754 S<472> 4194 157560 G<449> 7686 157 625 G<579> 6516 282 690 G<709> 5346 157 755 S<471> 4176 282561 G<451> 7668 282 626 G<581> 6498 157 691 G<711> 5328 282 756 S<470> 4158 157562 G<453> 7650 157 627 G<583> 6480 282 692 G<713> 5310 157 757 S<469> 4140 282563 G<455> 7632 282 628 G<585> 6462 157 693 G<715> 5292 282 758 S<468> 4122 157564 G<457> 7614 157 629 G<587> 6444 282 694 G<717> 5274 157 759 S<467> 4104 282565 G<459> 7596 282 630 G<589> 6426 157 695 G<719> 5256 282 760 S<466> 4086 157566 G<461> 7578 157 631 G<591> 6408 282 696 G<721> 5238 157 761 S<465> 4068 282567 G<463> 7560 282 632 G<593> 6390 157 697 G<723> 5220 282 762 S<464> 4050 157568 G<465> 7542 157 633 G<595> 6372 282 698 G<725> 5202 157 763 S<463> 4032 282569 G<467> 7524 282 634 G<597> 6354 157 699 G<727> 5184 282 764 S<462> 4014 157570 G<469> 7506 157 635 G<599> 6336 282 700 G<729> 5166 157 765 S<461> 3996 282571 G<471> 7488 282 636 G<601> 6318 157 701 G<731> 5148 282 766 S<460> 3978 157572 G<473> 7470 157 637 G<603> 6300 282 702 G<733> 5130 157 767 S<459> 3960 282573 G<475> 7452 282 638 G<605> 6282 157 703 G<735> 5112 282 768 S<458> 3942 157574 G<477> 7434 157 639 G<607> 6264 282 704 G<737> 5094 157 769 S<457> 3924 282575 G<479> 7416 282 640 G<609> 6246 157 705 G<739> 5076 282 770 S<456> 3906 157576 G<481> 7398 157 641 G<611> 6228 282 706 G<741> 5058 157 771 S<455> 3888 282577 G<483> 7380 282 642 G<613> 6210 157 707 G<743> 5040 282 772 S<454> 3870 157


Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos773 S<453> 3852 282 838 S<388> 2682 157 903 S<323> 1512 282 968 S<258> 342 157774 S<452> 3834 157 839 S<387> 2664 282 904 S<322> 1494 157 969 S<257> 324 282775 S<451> 3816 282 840 S<386> 2646 157 905 S<321> 1476 282 970 S<256> 306 157776 S<450> 3798 157 841 S<385> 2628 282 906 S<320> 1458 157 971 S<255> 288 282777 S<449> 3780 282 842 S<384> 2610 157 907 S<319> 1440 282 972 S<254> 270 157778 S<448> 3762 157 843 S<383> 2592 282 908 S<318> 1422 157 973 S<253> 252 282779 S<447> 3744 282 844 S<382> 2574 157 909 S<317> 1404 282 974 S<252> 234 157780 S<446> 3726 157 845 S<381> 2556 282 910 S<316> 1386 157 975 S<251> 216 282781 S<445> 3708 282 846 S<380> 2538 157 911 S<315> 1368 282 976 S<250> 198 157782 S<444> 3690 157 847 S<379> 2520 282 912 S<314> 1350 157 977 S<249> 180 282783 S<443> 3672 282 848 S<378> 2502 157 913 S<313> 1332 282 978 S<248> 162 157784 S<442> 3654 157 849 S<377> 2484 282 914 S<312> 1314 157 979 S<247> 144 282785 S<441> 3636 282 850 S<376> 2466 157 915 S<311> 1296 282 980 S<246> 126 157786 S<440> 3618 157 851 S<375> 2448 282 916 S<310> 1278 157 981 S<245> 108 282787 S<439> 3600 282 852 S<374> 2430 157 917 S<309> 1260 282 982 S<244> 90 157788 S<438> 3582 157 853 S<373> 2412 282 918 S<308> 1242 157 983 S<243> 72 282789 S<437> 3564 282 854 S<372> 2394 157 919 S<307> 1224 282 984 S<242> 54 157790 S<436> 3546 157 855 S<371> 2376 282 920 S<306> 1206 157 985 S<241> 36 282791 S<435> 3528 282 856 S<370> 2358 157 921 S<305> 1188 282 986 S<240> 18 157792 S<434> 3510 157 857 S<369> 2340 282 922 S<304> 1170 157 987 DUMMY 0 282793 S<433> 3492 282 858 S<368> 2322 157 923 S<303> 1152 282 988 S<239> -18 157794 S<432> 3474 157 859 S<367> 2304 282 924 S<302> 1134 157 989 S<238> -36 282795 S<431> 3456 282 860 S<366> 2286 157 925 S<301> 1116 282 990 S<237> -54 157796 S<430> 3438 157 861 S<365> 2268 282 926 S<300> 1098 157 991 S<236> -72 282797 S<429> 3420 282 862 S<364> 2250 157 927 S<299> 1080 282 992 S<235> -90 157798 S<428> 3402 157 863 S<363> 2232 282 928 S<298> 1062 157 993 S<234> -108 282799 S<427> 3384 282 864 S<362> 2214 157 929 S<297> 1044 282 994 S<233> -126 157800 S<426> 3366 157 865 S<361> 2196 282 930 S<296> 1026 157 995 S<232> -144 282801 S<425> 3348 282 866 S<360> 2178 157 931 S<295> 1008 282 996 S<231> -162 157802 S<424> 3330 157 867 S<359> 2160 282 932 S<294> 990 157 997 S<230> -180 282803 S<423> 3312 282 868 S<358> 2142 157 933 S<293> 972 282 998 S<229> -198 157804 S<422> 3294 157 869 S<357> 2124 282 934 S<292> 954 157 999 S<228> -216 282805 S<421> 3276 282 870 S<356> 2106 157 935 S<291> 936 282 1000 S<227> -234 157806 S<420> 3258 157 871 S<355> 2088 282 936 S<290> 918 157 1001 S<226> -252 282807 S<419> 3240 282 872 S<354> 2070 157 937 S<289> 900 282 1002 S<225> -270 157808 S<418> 3222 157 873 S<353> 2052 282 938 S<288> 882 157 1003 S<224> -288 282809 S<417> 3204 282 874 S<352> 2034 157 939 S<287> 864 282 1004 S<223> -306 157810 S<416> 3186 157 875 S<351> 2016 282 940 S<286> 846 157 1005 S<222> -324 282811 S<415> 3168 282 876 S<350> 1998 157 941 S<285> 828 282 1006 S<221> -342 157812 S<414> 3150 157 877 S<349> 1980 282 942 S<284> 810 157 1007 S<220> -360 282813 S<413> 3132 282 878 S<348> 1962 157 943 S<283> 792 282 1008 S<219> -378 157814 S<412> 3114 157 879 S<347> 1944 282 944 S<282> 774 157 1009 S<218> -396 282815 S<411> 3096 282 880 S<346> 1926 157 945 S<281> 756 282 1010 S<217> -414 157816 S<410> 3078 157 881 S<345> 1908 282 946 S<280> 738 157 1011 S<216> -432 282817 S<409> 3060 282 882 S<344> 1890 157 947 S<279> 720 282 1012 S<215> -450 157818 S<408> 3042 157 883 S<343> 1872 282 948 S<278> 702 157 1013 S<214> -468 282819 S<407> 3024 282 884 S<342> 1854 157 949 S<277> 684 282 1014 S<213> -486 157820 S<406> 3006 157 885 S<341> 1836 282 950 S<276> 666 157 1015 S<212> -504 282821 S<405> 2988 282 886 S<340> 1818 157 951 S<275> 648 282 1016 S<211> -522 157822 S<404> 2970 157 887 S<339> 1800 282 952 S<274> 630 157 1017 S<210> -540 282823 S<403> 2952 282 888 S<338> 1782 157 953 S<273> 612 282 1018 S<209> -558 157824 S<402> 2934 157 889 S<337> 1764 282 954 S<272> 594 157 1019 S<208> -576 282825 S<401> 2916 282 890 S<336> 1746 157 955 S<271> 576 282 1020 S<207> -594 157826 S<400> 2898 157 891 S<335> 1728 282 956 S<270> 558 157 1021 S<206> -612 282827 S<399> 2880 282 892 S<334> 1710 157 957 S<269> 540 282 1022 S<205> -630 157828 S<398> 2862 157 893 S<333> 1692 282 958 S<268> 522 157 1023 S<204> -648 282829 S<397> 2844 282 894 S<332> 1674 157 959 S<267> 504 282 1024 S<203> -666 157830 S<396> 2826 157 895 S<331> 1656 282 960 S<266> 486 157 1025 S<202> -684 282831 S<395> 2808 282 896 S<330> 1638 157 961 S<265> 468 282 1026 S<201> -702 157832 S<394> 2790 157 897 S<329> 1620 282 962 S<264> 450 157 1027 S<200> -720 282833 S<393> 2772 282 898 S<328> 1602 157 963 S<263> 432 282 1028 S<199> -738 157834 S<392> 2754 157 899 S<327> 1584 282 964 S<262> 414 157 1029 S<198> -756 282835 S<391> 2736 282 900 S<326> 1566 157 965 S<261> 396 282 1030 S<197> -774 157836 S<390> 2718 157 901 S<325> 1548 282 966 S<260> 378 157 1031 S<196> -792 282837 S<389> 2700 282 902 S<324> 1530 157 967 S<259> 360 282 1032 S<195> -810 157


Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos1033 S<194> -828 282 1098 S<129> -1998 157 1163 S<64> -3168 282 1228 DUMMY -4338 1571034 S<193> -846 157 1099 S<128> -2016 282 1164 S<63> -3186 157 1229 DUMMY -4356 2821035 S<192> -864 282 1100 S<127> -2034 157 1165 S<62> -3204 282 1230 DUMMY -4374 1571036 S<191> -882 157 1101 S<126> -2052 282 1166 S<61> -3222 157 1231 G<814> -4392 2821037 S<190> -900 282 1102 S<125> -2070 157 1167 S<60> -3240 282 1232 G<812> -4410 1571038 S<189> -918 157 1103 S<124> -2088 282 1168 S<59> -3258 157 1233 G<810> -4428 2821039 S<188> -936 282 1104 S<123> -2106 157 1169 S<58> -3276 282 1234 G<808> -4446 1571040 S<187> -954 157 1105 S<122> -2124 282 1170 S<57> -3294 157 1235 G<806> -4464 2821041 S<186> -972 282 1106 S<121> -2142 157 1171 S<56> -3312 282 1236 G<804> -4482 1571042 S<185> -990 157 1107 S<120> -2160 282 1172 S<55> -3330 157 1237 G<802> -4500 2821043 S<184> -1008 282 1108 S<119> -2178 157 1173 S<54> -3348 282 1238 G<800> -4518 1571044 S<183> -1026 157 1109 S<118> -2196 282 1174 S<53> -3366 157 1239 G<798> -4536 2821045 S<182> -1044 282 1110 S<117> -2214 157 1175 S<52> -3384 282 1240 G<796> -4554 1571046 S<181> -1062 157 1111 S<116> -2232 282 1176 S<51> -3402 157 1241 G<794> -4572 2821047 S<180> -1080 282 1112 S<115> -2250 157 1177 S<50> -3420 282 1242 G<792> -4590 1571048 S<179> -1098 157 1113 S<114> -2268 282 1178 S<49> -3438 157 1243 G<790> -4608 2821049 S<178> -1116 282 1114 S<113> -2286 157 1179 S<48> -3456 282 1244 G<788> -4626 1571050 S<177> -1134 157 1115 S<112> -2304 282 1180 S<47> -3474 157 1245 G<786> -4644 2821051 S<176> -1152 282 1116 S<111> -2322 157 1181 S<46> -3492 282 1246 G<784> -4662 1571052 S<175> -1170 157 1117 S<110> -2340 282 1182 S<45> -3510 157 1247 G<782> -4680 2821053 S<174> -1188 282 1118 S<109> -2358 157 1183 S<44> -3528 282 1248 G<780> -4698 1571054 S<173> -1206 157 1119 S<108> -2376 282 1184 S<43> -3546 157 1249 G<778> -4716 2821055 S<172> -1224 282 1120 S<107> -2394 157 1185 S<42> -3564 282 1250 G<776> -4734 1571056 S<171> -1242 157 1121 S<106> -2412 282 1186 S<41> -3582 157 1251 G<774> -4752 2821057 S<170> -1260 282 1122 S<105> -2430 157 1187 S<40> -3600 282 1252 G<772> -4770 1571058 S<169> -1278 157 1123 S<104> -2448 282 1188 S<39> -3618 157 1253 G<770> -4788 2821059 S<168> -1296 282 1124 S<103> -2466 157 1189 S<38> -3636 282 1254 G<768> -4806 1571060 S<167> -1314 157 1125 S<102> -2484 282 1190 S<37> -3654 157 1255 G<766> -4824 2821061 S<166> -1332 282 1126 S<101> -2502 157 1191 S<36> -3672 282 1256 G<764> -4842 1571062 S<165> -1350 157 1127 S<100> -2520 282 1192 S<35> -3690 157 1257 G<762> -4860 2821063 S<164> -1368 282 1128 S<99> -2538 157 1193 S<34> -3708 282 1258 G<760> -4878 1571064 S<163> -1386 157 1129 S<98> -2556 282 1194 S<33> -3726 157 1259 G<758> -4896 2821065 S<162> -1404 282 1130 S<97> -2574 157 1195 S<32> -3744 282 1260 G<756> -4914 1571066 S<161> -1422 157 1131 S<96> -2592 282 1196 S<31> -3762 157 1261 G<754> -4932 2821067 S<160> -1440 282 1132 S<95> -2610 157 1197 S<30> -3780 282 1262 G<752> -4950 1571068 S<159> -1458 157 1133 S<94> -2628 282 1198 S<29> -3798 157 1263 G<750> -4968 2821069 S<158> -1476 282 1134 S<93> -2646 157 1199 S<28> -3816 282 1264 G<748> -4986 1571070 S<157> -1494 157 1135 S<92> -2664 282 1200 S<27> -3834 157 1265 G<746> -5004 2821071 S<156> -1512 282 1136 S<91> -2682 157 1201 S<26> -3852 282 1266 G<744> -5022 1571072 S<155> -1530 157 1137 S<90> -2700 282 1202 S<25> -3870 157 1267 G<742> -5040 2821073 S<154> -1548 282 1138 S<89> -2718 157 1203 S<24> -3888 282 1268 G<740> -5058 1571074 S<153> -1566 157 1139 S<88> -2736 282 1204 S<23> -3906 157 1269 G<738> -5076 2821075 S<152> -1584 282 1140 S<87> -2754 157 1205 S<22> -3924 282 1270 G<736> -5094 1571076 S<151> -1602 157 1141 S<86> -2772 282 1206 S<21> -3942 157 1271 G<734> -5112 2821077 S<150> -1620 282 1142 S<85> -2790 157 1207 S<20> -3960 282 1272 G<732> -5130 1571078 S<149> -1638 157 1143 S<84> -2808 282 1208 S<19> -3978 157 1273 G<730> -5148 2821079 S<148> -1656 282 1144 S<83> -2826 157 1209 S<18> -3996 282 1274 G<728> -5166 1571080 S<147> -1674 157 1145 S<82> -2844 282 1210 S<17> -4014 157 1275 G<726> -5184 2821081 S<146> -1692 282 1146 S<81> -2862 157 1211 S<16> -4032 282 1276 G<724> -5202 1571082 S<145> -1710 157 1147 S<80> -2880 282 1212 S<15> -4050 157 1277 G<722> -5220 2821083 S<144> -1728 282 1148 S<79> -2898 157 1213 S<14> -4068 282 1278 G<720> -5238 1571084 S<143> -1746 157 1149 S<78> -2916 282 1214 S<13> -4086 157 1279 G<718> -5256 2821085 S<142> -1764 282 1150 S<77> -2934 157 1215 S<12> -4104 282 1280 G<716> -5274 1571086 S<141> -1782 157 1151 S<76> -2952 282 1216 S<11> -4122 157 1281 G<714> -5292 2821087 S<140> -1800 282 1152 S<75> -2970 157 1217 S<10> -4140 282 1282 G<712> -5310 1571088 S<139> -1818 157 1153 S<74> -2988 282 1218 S<9> -4158 157 1283 G<710> -5328 2821089 S<138> -1836 282 1154 S<73> -3006 157 1219 S<8> -4176 282 1284 G<708> -5346 1571090 S<137> -1854 157 1155 S<72> -3024 282 1220 S<7> -4194 157 1285 G<706> -5364 2821091 S<136> -1872 282 1156 S<71> -3042 157 1221 S<6> -4212 282 1286 G<704> -5382 1571092 S<135> -1890 157 1157 S<70> -3060 282 1222 S<5> -4230 157 1287 G<702> -5400 2821093 S<134> -1908 282 1158 S<69> -3078 157 1223 S<4> -4248 282 1288 G<700> -5418 1571094 S<133> -1926 157 1159 S<68> -3096 282 1224 S<3> -4266 157 1289 G<698> -5436 2821095 S<132> -1944 282 1160 S<67> -3114 157 1225 S<2> -4284 282 1290 G<696> -5454 1571096 S<131> -1962 157 1161 S<66> -3132 282 1226 S<1> -4302 157 1291 G<694> -5472 2821097 S<130> -1980 282 1162 S<65> -3150 157 1227 S<0> -4320 282 1292 G<692> -5490 157


Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos1293 G<690> -5508 282 1358 G<560> -6678 157 1423 G<430> -7848 282 1488 G<300> -9018 1571294 G<688> -5526 157 1359 G<558> -6696 282 1424 G<428> -7866 157 1489 G<298> -9036 2821295 G<686> -5544 282 1360 G<556> -6714 157 1425 G<426> -7884 282 1490 G<296> -9054 1571296 G<684> -5562 157 1361 G<554> -6732 282 1426 G<424> -7902 157 1491 G<294> -9072 2821297 G<682> -5580 282 1362 G<552> -6750 157 1427 G<422> -7920 282 1492 G<292> -9090 1571298 G<680> -5598 157 1363 G<550> -6768 282 1428 G<420> -7938 157 1493 G<290> -9108 2821299 G<678> -5616 282 1364 G<548> -6786 157 1429 G<418> -7956 282 1494 G<288> -9126 1571300 G<676> -5634 157 1365 G<546> -6804 282 1430 G<416> -7974 157 1495 G<286> -9144 2821301 G<674> -5652 282 1366 G<544> -6822 157 1431 G<414> -7992 282 1496 G<284> -9162 1571302 G<672> -5670 157 1367 G<542> -6840 282 1432 G<412> -8010 157 1497 G<282> -9180 2821303 G<670> -5688 282 1368 G<540> -6858 157 1433 G<410> -8028 282 1498 G<280> -9198 1571304 G<668> -5706 157 1369 G<538> -6876 282 1434 G<408> -8046 157 1499 G<278> -9216 2821305 G<666> -5724 282 1370 G<536> -6894 157 1435 G<406> -8064 282 1500 G<276> -9234 1571306 G<664> -5742 157 1371 G<534> -6912 282 1436 G<404> -8082 157 1501 G<274> -9252 2821307 G<662> -5760 282 1372 G<532> -6930 157 1437 G<402> -8100 282 1502 G<272> -9270 1571308 G<660> -5778 157 1373 G<530> -6948 282 1438 G<400> -8118 157 1503 G<270> -9288 2821309 G<658> -5796 282 1374 G<528> -6966 157 1439 G<398> -8136 282 1504 G<268> -9306 1571310 G<656> -5814 157 1375 G<526> -6984 282 1440 G<396> -8154 157 1505 G<266> -9324 2821311 G<654> -5832 282 1376 G<524> -7002 157 1441 G<394> -8172 282 1506 G<264> -9342 1571312 G<652> -5850 157 1377 G<522> -7020 282 1442 G<392> -8190 157 1507 G<262> -9360 2821313 G<650> -5868 282 1378 G<520> -7038 157 1443 G<390> -8208 282 1508 G<260> -9378 1571314 G<648> -5886 157 1379 G<518> -7056 282 1444 G<388> -8226 157 1509 G<258> -9396 2821315 G<646> -5904 282 1380 G<516> -7074 157 1445 G<386> -8244 282 1510 G<256> -9414 1571316 G<644> -5922 157 1381 G<514> -7092 282 1446 G<384> -8262 157 1511 G<254> -9432 2821317 G<642> -5940 282 1382 G<512> -7110 157 1447 G<382> -8280 282 1512 G<252> -9450 1571318 G<640> -5958 157 1383 G<510> -7128 282 1448 G<380> -8298 157 1513 G<250> -9468 2821319 G<638> -5976 282 1384 G<508> -7146 157 1449 G<378> -8316 282 1514 G<248> -9486 1571320 G<636> -5994 157 1385 G<506> -7164 282 1450 G<376> -8334 157 1515 G<246> -9504 2821321 G<634> -6012 282 1386 G<504> -7182 157 1451 G<374> -8352 282 1516 G<244> -9522 1571322 G<632> -6030 157 1387 G<502> -7200 282 1452 G<372> -8370 157 1517 G<242> -9540 2821323 G<630> -6048 282 1388 G<500> -7218 157 1453 G<370> -8388 282 1518 G<240> -9558 1571324 G<628> -6066 157 1389 G<498> -7236 282 1454 G<368> -8406 157 1519 G<238> -9576 2821325 G<626> -6084 282 1390 G<496> -7254 157 1455 G<366> -8424 282 1520 G<236> -9594 1571326 G<624> -6102 157 1391 G<494> -7272 282 1456 G<364> -8442 157 1521 G<234> -9612 2821327 G<622> -6120 282 1392 G<492> -7290 157 1457 G<362> -8460 282 1522 G<232> -9630 1571328 G<620> -6138 157 1393 G<490> -7308 282 1458 G<360> -8478 157 1523 G<230> -9648 2821329 G<618> -6156 282 1394 G<488> -7326 157 1459 G<358> -8496 282 1524 G<228> -9666 1571330 G<616> -6174 157 1395 G<486> -7344 282 1460 G<356> -8514 157 1525 G<226> -9684 2821331 G<614> -6192 282 1396 G<484> -7362 157 1461 G<354> -8532 282 1526 G<224> -9702 1571332 G<612> -6210 157 1397 G<482> -7380 282 1462 G<352> -8550 157 1527 G<222> -9720 2821333 G<610> -6228 282 1398 G<480> -7398 157 1463 G<350> -8568 282 1528 G<220> -9738 1571334 G<608> -6246 157 1399 G<478> -7416 282 1464 G<348> -8586 157 1529 G<218> -9756 2821335 G<606> -6264 282 1400 G<476> -7434 157 1465 G<346> -8604 282 1530 G<216> -9774 1571336 G<604> -6282 157 1401 G<474> -7452 282 1466 G<344> -8622 157 1531 G<214> -9792 2821337 G<602> -6300 282 1402 G<472> -7470 157 1467 G<342> -8640 282 1532 G<212> -9810 1571338 G<600> -6318 157 1403 G<470> -7488 282 1468 G<340> -8658 157 1533 G<210> -9828 2821339 G<598> -6336 282 1404 G<468> -7506 157 1469 G<338> -8676 282 1534 G<208> -9846 1571340 G<596> -6354 157 1405 G<466> -7524 282 1470 G<336> -8694 157 1535 G<206> -9864 2821341 G<594> -6372 282 1406 G<464> -7542 157 1471 G<334> -8712 282 1536 G<204> -9882 1571342 G<592> -6390 157 1407 G<462> -7560 282 1472 G<332> -8730 157 1537 G<202> -9900 2821343 G<590> -6408 282 1408 G<460> -7578 157 1473 G<330> -8748 282 1538 G<200> -9918 1571344 G<588> -6426 157 1409 G<458> -7596 282 1474 G<328> -8766 157 1539 G<198> -9936 2821345 G<586> -6444 282 1410 G<456> -7614 157 1475 G<326> -8784 282 1540 G<196> -9954 1571346 G<584> -6462 157 1411 G<454> -7632 282 1476 G<324> -8802 157 1541 G<194> -9972 2821347 G<582> -6480 282 1412 G<452> -7650 157 1477 G<322> -8820 282 1542 G<192> -9990 1571348 G<580> -6498 157 1413 G<450> -7668 282 1478 G<320> -8838 157 1543 G<190> -10008 2821349 G<578> -6516 282 1414 G<448> -7686 157 1479 G<318> -8856 282 1544 G<188> -10026 1571350 G<576> -6534 157 1415 G<446> -7704 282 1480 G<316> -8874 157 1545 G<186> -10044 2821351 G<574> -6552 282 1416 G<444> -7722 157 1481 G<314> -8892 282 1546 G<184> -10062 1571352 G<572> -6570 157 1417 G<442> -7740 282 1482 G<312> -8910 157 1547 G<182> -10080 2821353 G<570> -6588 282 1418 G<440> -7758 157 1483 G<310> -8928 282 1548 G<180> -10098 1571354 G<568> -6606 157 1419 G<438> -7776 282 1484 G<308> -8946 157 1549 G<178> -10116 2821355 G<566> -6624 282 1420 G<436> -7794 157 1485 G<306> -8964 282 1550 G<176> -10134 1571356 G<564> -6642 157 1421 G<434> -7812 282 1486 G<304> -8982 157 1551 G<174> -10152 2821357 G<562> -6660 282 1422 G<432> -7830 157 1487 G<302> -9000 282 1552 G<172> -10170 157


Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos Pad # Signal X-pos Y-pos1553 G<170> -10188 282 1618 G<40> -11358 157 1554 G<168> -10206 157 1619 G<38> -11376 282 1555 G<166> -10224 282 1620 G<36> -11394 157 1556 G<164> -10242 157 1621 G<34> -11412 282 1557 G<162> -10260 282 1622 G<32> -11430 157 1558 G<160> -10278 157 1623 G<30> -11448 282 1559 G<158> -10296 282 1624 G<28> -11466 157 1560 G<156> -10314 157 1625 G<26> -11484 282 1561 G<154> -10332 282 1626 G<24> -11502 157 1562 G<152> -10350 157 1627 G<22> -11520 282 1563 G<150> -10368 282 1628 G<20> -11538 157 1564 G<148> -10386 157 1629 G<18> -11556 282 1565 G<146> -10404 282 1630 G<16> -11574 157 1566 G<144> -10422 157 1631 G<14> -11592 282 1567 G<142> -10440 282 1632 G<12> -11610 157 1568 G<140> -10458 157 1633 G<10> -11628 282 1569 G<138> -10476 282 1634 G<8> -11646 157 1570 G<136> -10494 157 1635 G<6> -11664 282 1571 G<134> -10512 282 1636 G<4> -11682 157 1572 G<132> -10530 157 1637 G<2> -11700 282 1573 G<130> -10548 282 1638 G<0> -11718 157 1574 G<128> -10566 157 1639 Dummy -11768.5 282 1575 G<126> -10584 282 1640 Dummy -11821.5 157 1576 G<124> -10602 157 1577 G<122> -10620 282 1578 G<120> -10638 157 1579 G<118> -10656 282 1580 G<116> -10674 157 1581 G<114> -10692 282 1582 G<112> -10710 157 1583 G<110> -10728 282 1584 G<108> -10746 157 1585 G<106> -10764 282 1586 G<104> -10782 157 1587 G<102> -10800 282 1588 G<100> -10818 157 1589 G<98> -10836 282 1590 G<96> -10854 157 1591 G<94> -10872 282 1592 G<92> -10890 157 1593 G<90> -10908 282 1594 G<88> -10926 157 1595 G<86> -10944 282 1596 G<84> -10962 157 1597 G<82> -10980 282 1598 G<80> -10998 157 1599 G<78> -11016 282 1600 G<76> -11034 157 1601 G<74> -11052 282 1602 G<72> -11070 157 1603 G<70> -11088 282 1604 G<68> -11106 157 1605 G<66> -11124 282 1606 G<64> -11142 157 1607 G<62> -11160 282 1608 G<60> -11178 157 1609 G<58> -11196 282 1610 G<56> -11214 157 1611 G<54> -11232 282 1612 G<52> -11250 157 1613 G<50> -11268 282 1614 G<48> -11286 157 1615 G<46> -11304 282 1616 G<44> -11322 157 1617 G<42> -11340 282

Note: IC material Temperature expansion factor should take into account during panel design.


6 Pin Description

SSD2123 Pin Function Description

Key: I = Input O =Output I/O = Bi-directional (input/output) P = Power pin GND = System VSS

Table 6-1: Power Supply Pins

Name Type Connect to Function Description When not

in use VSS GND System ground pin of the IC. - AVSS GND Grounding for analog circuit. -

VSSRC GND Grounding for analog circuit. This pin requires a noise free path for providing accurate LCD driving voltages.

-

VCHS

P

GND

Ground of Power Supply

Grounding for booster circuit. -

VCORE VREGC Power for Core Logic

VDD for core use - Connect a capacitor for stabilization -

VDDEXT System VDD

Power for Internal VCORE Regulator

Voltage input pin for internal logic. Connect to System VDD (refer to power connection Figure 14-1)

-

VDDIO

P

System VDD

Power for Interface Logic Pins

Voltage input pin for logic I/O. -

VCI Power supply

Booster input voltage pin. - Connect to voltage source between 2.5V to 3.6V -

VCIP P

VCI

Power for Analog Circuits

Voltage supply pin for analog circuit. This pin requires a noise free path for providing accurate LCD driving voltages.

-

VCIM O Stabilizing capacitor

Booster Output Negative voltage of VCI -

AVDD Stabilizing capacitor

Booster Voltages

Booster voltage and regulated between 5.1V to 6.1V. Controlled by command Power control 2 (R0Ch) -

AVDDG O

AVDD on FPC

Voltage for analog

power supply used by on chip analog blocks and VGH/VGL dcdc. Must connect AVDD together -

VCOMH Stabilizing capacitor

This pin indicates a HIGH level of VCOM generated in driving the VCOM alternation. -

VCOML O Stabilizing

capacitor

Voltages for VCOM Signal This pin indicates a LOW level of VCOM generated in

driving the VCOM alternation. -

VLCD255 Stabilizing capacitor This pin is the maximum source driver voltage. -

VGH Stabilizing capacitor A positive power output pin for gate driver. -

VGL

O

Stabilizing capacitor

LCD Driving Voltages

A negative power output pin for gate driver. -

VCOMR I

External voltage source or Open

External Reference

This pin provides voltage reference for internal voltage regulator when register VDV[4:0] of Power Control 4 is set to “01111”.

Open

VREGC P Stabilizing capacitor

Regulator output for Regulator output for VCORE use -


logic circuits

CXP - Connect a capacitor to CXN - CXN

Booster capacitor - Connect a capacitor to CXP -

C11P - Connect a capacitor to C11N - C11N

Booster capacitor - Connect a capacitor to C11P -

C12P - Connect a capacitor to C12N C12N

Booster capacitor - Connect a capacitor to C12P

C13P - Connect a capacitor to C13N C13N

Booster capacitor - Connect a capacitor to C13P







CSSRC

P

Charge Sharing

Booster and Stabilization Capacitors

- Connect a capacitor to VSS Open


Table 6-2: Interface Logic Pins

Name Type Connect to Function Description When not in

use

SPID VDDIO or VSS

ID selection pin for the SPI serial interface. When sending serial data, the “ID” bit must match with the logic stage of this pin. (Refer to Serial Interface block description on Page XX for details)

-

CSB MPU Chip select pin of serial interface. Open or VDDIO

SDI MPU Data input pin in serial mode. Open or VDDIO

SDC MPU Data/Command pin of serial interface. Open or VDDIO

SCK

I

MPU

Serial Interface

Clock input pin in serial mode. Open or VDDIO

SDO O MPU Serial Interface Data output pin in serial mode. Open

SHUT I VDDIO or VSS

Logic Control

Display shut down pin to put the driver into sleep mode. A sharp falling edge must be provided to such pin when IC power on. - Connect to VDDIO for sleep mode - Connect to VSS for normal operating mode Note: Software can override the setting

VDDIO or VSS

VSYNC

I MPU Frame synchronization signal. Fixed to VDDIO or VSS if not used. -

HSYNC I MPU

RGB Interface Line synchronization signal. Fixed to VDDIO or VSS if not

used -

DOTCLK

I MPU Display Timing Signals

Dot-clock signal and oscillator source. External clock must be provided to that pin even at front or back porch non-display period.

-

DEN

I MPU Display enable pin from controller. VDDIO

RR[7:0]

GG[7:0]

BB[7:0]

I MPU Graphic Display Data

- RR[7:0] : Red Data – 24bit parallel/8bit serial - RR[7:2] : Red Data –18bit parallel/6bit serial - GG[7:0] : Green Data –24bit parallel - GG[7:2] : Green Data –18bit parallel - BB[7:0] : Blue Data –24bit parallel - BB[7:2] : Blue Data –18bit parallel

VDDIO or VSS

RESB I MPU System reset

System reset pin. Initialization occurs once this pin is pulled Low, the minimum pulse length is 1ms. A low pulse must be applied after power-on. Connect this pin to VDDIO when not used.

VDDIO

SRGB I VDDIO or VSS

RGB interface selection

Determine data input for SSD2123. - Connect to VSS for the operation of parallel RGB mode 18/24 bits. - Connect to VDDIO for the operation of serial RGB mode 6/8 bits. Note: Software can override the setting

-

X400 I VDDIO or VSS


Determine data input for SSD2123. - Connect to VSS for the operation of using full 480 sources - Connect to VDDIO for the operation of using 400 sources at center. First data will appear at S40. Note: Software can override the setting

-


DENMODE I VDDIO or VSS


Determine data input for SSD2123. - Connect to VSS for the operation of SYNC mode - Connect to VDDIO for the operation of DEN mode Note: Software can override the setting

-

GPI[3:0] I User define General propose pins defined by user Open (GPIP=VSS)

GAMAS I VDDIO or VSS

Logic Control GAMAS controls the default register values VDDIO or VSS

Table 6-3: Interface Logic Pins

Name Type Connect to Function Description When not in use

STYPE0 I VDDIO or VSS

-

STYPE1 I VDDIO or VSS

Serial Interface Selection

STYPE[1:0] = 0x ; SPID type 3 wires SPI 24 bits STYPE[1:0] = 10 ; standard 3 wires SPI 9 bits STYPE[1:0] = 11 ; standard 4 wires SPI 8 bits -

BGR I VDDIO or VSS

Color mapping selection pin. Refer to G0-G815 pin description. Note: Software can override the setting

VDDIO or VSS

REV

I VDDIO or VSS

Input pin to select the display reversion. - Connect to VDDIO mapping data “0” to maximum pixel voltage for normal white panel - Connect to VSS mapping data “0” to minimum pixel voltage for normal black panel Note: Software can override the setting

VDDIO or VSS

RL

I VDDIO or VSS

Select the Source driver data shift direction. - Connect to VDDIO for display first pixel data at S0 - Connect to VSS for display first pixel data at S479 Note: Software can override the setting

VDDIO or VSS

TB

I VDDIO or VSS

Select the Gate driver scan direction. Note: Software can override the setting

VDDIO or VSS

CM

I VDDIO or VSS

Panel Mapping controls

Input pin to select 16.7M-color or 8-color display mode. After entered 8-color display mode, the driver will switch to Frame-Inversion-Mode, and only MSB of the data Red, Green and Blue will be considered. - Connect to VDDIO for 8-color display mode - Connect to VSS for 16.7M-color display mode Note: Software can override the setting

VDDIO or VSS

wu

Line


Table 6-4: Driver Output Pins


VCOM LCD A power supply for the TFT-display common electrode. Open

G0-G815 LCD

Gate driver output pins. These pins output VGH or VGL level. Color filter arrangement depends on BGR pin. G(3n): Display Red if BGR = Low, Blue if BGR = High. G(3n+1): Display Green. G(3n+2): Display Blue if BGR = Low, Red if BGR = High.

Open

S0-S479

O

LCD

LCD Driving Signals

Source driver output pins. Open

Table 6-5: Miscellaneous Pins


NC - - - These pins must be left open and cannot be connected together Open

DUMMY - - - Floating pins and no connection inside the IC. These pins can be shorted together or connect to any signal. Open

TESTA/B/C I/O FPC IC Testing Signal

Test pin of the internal circuit. - Leave this pin open and optional to insert test point in FPC for evaluation.

Open


7 COMMAND TABLE

Table 7-1: Command Table and POR (Power On Reset) values

Reg# Register R/W D/C IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0R Index 0 0 * * * * * * * ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

Driver output control 0 1 X400 RL REV CAD BGR SM 1 1 0 0 0 0 1 1 1 1

R01h ([XXXX][X011]0Fh )

X X X X X 0 1 1 0 0 0 0 1 1 1 1

LCD-Driving-Waveform Control

0 1 0 0 0 0 B/C EOR NW9 NW8 NW7 NW6 NW5 NW4 NW3 NW2 NW1 NW0 R02h

(0C02h) 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0

Power control (1) 0 1 DCT3 DCT2 DCT1 DCT0 BT3 BT2 BT1 BT0 DC3 DC2 DC1 DC0 AP2 AP1 AP0 1 R03h

(0407h) 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1

Separate Gamma(1) 0 1 0 0 0 0 0 OLO 0 0 0 0 0 0 0 0 0 0 R04h

(0400h) 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

Frame cycle control 0 1 NO1 NO0 SDT1 SDT0 EQ1 EQ0 0 0 EQ2 0 0 0 BTP1 BTP0 0 0 R0Bh

(D800h) 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0

Power control (2) 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 VRC2 VRC1 VRC0 R0Ch

(0005h) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Power control (3) 0 1 0 0 0 0 0 0 0 0 0 0 0 0 VRH3 VRH2 VRH1 VRH0 R0Dh

(000Fh) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

Power control (4) 0 1 0 0 VCOMG VDV4 VDV3 VDV2 VDV1 VDV0 0 0 0 0 0 0 0 VCOMASR0Eh

(2C00h) 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0

Gate scan starting Position 0 1 0 0 0 0 0 0 0 SCN8 SCN7 SCN6 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0R0Fh (0000h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Software 8 color mode

0 1 0 0 0 0 0 0 1 0 1 1 0 0 1 1 cm_en cm_softR10h

(02CCh) 0 0 0 0 0 0 1 0 1 1 0 1 1 1 0 0

Double source amp 0 1 0 0 0 0 0 0 0 0 1 SAmp 0 1 0 0 0 0 R15h

(0090h) 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0

Pixel per line 0 1 XL8 XL7 XL6 XL5 XL4 XL3 XL2 XL1 XL0 HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0

(EF8Eh) x400=0 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 0 R16h (C786h) x400=1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 1 0

Vertical Porch 0 1 0 0 0 0 0 0 0 0 VBP7 VBP6 VBP5 VBP4 VBP3 VBP2 VBP1 VBP0 R17h

(0003h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Power control (5) 0 1 0 0 0 0 0 0 nMTP 0 VCM7 VCM6 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0R1Eh

(0034h) 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0

Power control (5) 0 1 0 0 0 1 1 0 0 0 VCMR7 VCMR6 VCMR5 VCMR4 VCMR3 VCMR2 VCMR1 VCMR0R1Fh

(1834h) GAMAS=1 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 0

Gamma Buffer biasing current

0 1 0 0 1 0 1 IT2 IT1 IT0 0 0 0 0 0 0 0 0 R26h (2800h) 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0

VCOM EQ 0 1 0 0 0 0 0 0 0 1 1 1 0 1 0 VCOMEQ2

VCOMEQ1

VCOMEQ0R2Ah

(01D2h) 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 0

2nd booster freq 0 1 ENSDO 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 R2Bh

(0520h) 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0

2nd booster freq 0 1 0 0 1 1 DCYT3 DCYT2 DCYT1 DCYT0 DCY3 DCY2 DCY1 DCY0 1 1 0 1 R2Ch

(3DDDh) 0 0 1 1 1 1 0 1 1 1 0 1 1 1 0 1

Software Shut (5) 0 1 0 0 1 1 1 1 1 1 0 1 0 UNREG 0 SS1 SS0 0 R2Dh

(3F40h) 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0

Read SDO (5) 0 1 1 0 1 1 0 1 0 1 0 1 RSDO 0 0 1 0 0 R2Eh

(B544h) 1 0 1 1 0 1 0 1 0 1 0 0 0 0 0 0

γ control (1) 0 1 0 0 0 0 0 PKP 12

PKP 11

PKP 10 0 0 0 0 0 PKP

02 PKP 01

PKP 00 R30h

(0000h) GAMAS=1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

γ control (1) 0 1 0 0 0 0 0 PKP 32

PKP 31

PKP 30 0 0 0 0 0 PKP

22 PKP 21

PKP 20 R31h

(0305h) GAMAS=1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1

γ control (1) 0 1 0 0 0 0 0 PKP 52

PKP 51

PKP 50 0 0 0 0 0 PKP

42 PKP 41

PKP 40 R32h

(0000h) GAMAS=1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

wu

Line


γ control (1) 0 1 0 0 0 0 0 PRP 12

PRP 11

PRP 10 0 0 0 0 0 PRP

02 PRP 01

PRP 00 R33h

(0201h) GAMAS=1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1

γ control (1) 0 1 0 0 0 0 0 PKN 12

PKN 11

PKN 10 0 0 0 0 0 PKN

02 PKN 01

PKN 00 R34h

(0607h) GAMAS=1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1

γ control (1) 0 1 0 0 0 0 0 PKN 32

PKN 31

PKN 30 0 0 0 0 0 PKN

22 PKN 21

PKN 20 R35h

(0204h) GAMAS=1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0

γ control (1) 0 1 0 0 0 0 0 PKN 52

PKN 51

PKN 50 0 0 0 0 0 PKN

42 PKN 41

PKN 40 R36h

(0707h) GAMAS=1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1

γ control (1) 0 1 0 0 0 0 0 PRN 12

PRN 11

PRN 10 0 0 0 0 0 PRN

02 PRN 01

PRN 00 R37h

(0203h) GAMAS=1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1

γ control (2) 0 1 0 0 0 VRP 14

VRP 13

VRP 12

VRP 11

VRP 10 0 0 0 0 VRP

03 VRP 02

VRP 01

VRP 00 R3Ah

(0F0Fh) GAMAS=1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

γ control (2) 0 1 0 0 0 VRN 14

VRN 13

VRN 12

VRN 11

VRN 10 0 0 0 0 VRN

03 VRN

02 VRN

01 VRN

00 R3Bh (0F02h) GAMAS=1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0

Note: X means hardware defining default setting

Table 7-2 – Gamma Registers POR value

Register GAMAS=0 GAMAS=1PKP0 000 000 PKP1 000 000 PKP2 111 101 PKP3 111 011 PKP4 011 000 PKP5 000 000 PRP0 001 001 PRP1 100 010 VRP0 1011 1111 VRP1 01101 01111 PKN0 111 111 PKN1 011 110 PKN2 000 100 PKN3 000 010 PKN4 111 111 PKN5 111 111 PRN0 100 011 PRN1 010 010 VRN0 1011 0010 VRN1 01101 01111

BT[3:0] TBD 0100 BTP[1:0] TBD 00 VRC[2:0] TBD 101 VRH[3:0] TBD 1111 VDV[4:0] TBD 01100 VCM[7:0] TBD 00110100HBP[6:0] TBD 0000110


8 COMMAND DESCRIPTION Index (IR) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0W 0 ∗∗∗∗ ∗∗∗∗ ∗∗∗∗ ∗∗∗∗ ∗∗∗∗ ∗∗∗∗ ∗∗∗∗ ∗∗∗∗ ∗∗∗∗ ID6 ID5 ID4 ID3 ID2 ID1 ID0

The index instruction specifies the RAM control indexes (R00h to R7Fh). It sets the register number in the range of 0000000 to 1111111 in binary form. But do not access to Index register and instruction bits which do not have it’s own index register. Driver Output Control (R01h) (POR = [XXXX][X011]0Fh) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0W 1 X400 RL REV 0 BGR 0 1 MUX8 MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0

POR X X X 0 X 0 1 1 0 0 0 0 1 1 1 1 X400: When X400=”0”, full 480 sources are in operation When X400=”1”, only 400 sources at the center are in operation. First data will appear at S40.

X400 = 0 X400 = 1

RL: Selects the output shift direction of the source driver. When RL = “1”, S0 shifts to S479 and 1st pixel color is assigned from S0. When RL = “0”, S479 shifts to S0 and 1st pixel color is assigned from S479. Set RL bit and BGR bit when changing the dot order of R, G and B. REV: Displays all character and graphics display sections with reversal when REV = “1”. Since the grayscale level can be reversed, display of the same data is enabled on normally white and normally black panels. Source output level is indicated below.

Source Output level REV RGB data VCOM = ”H” VCOM = ”L”

1 000000B

: 111111B

V63 :

V0

V0 :

V63

0 000000B

: 111111B

V0 :

V63

V63 :

V0 BGR: Selects the <R><G><B> arrangement. When BGR = “0” <R><G><B> color is assigned from G0. When BGR = “1” <B><G><R> color is assigned from G0. Note: The default setting of register bits X400, RL, REV, BGR and TB are defined by the logic stage of corresponding hardware pins.

These bits will override the hardware setting once software command was sent to set the bits.

G812 G814

G0 G2 G4

G1 G3 G5

G813 G815

S0 S479

G0 G2 G4

G716 G718

G1G3G5

G717G719

S40 S439


TB = 0 TB = 1

RL = 0

RL = 1

G0 G2 G4

G812 G814

G1G3G5

G813G815

S0 S479

G0 G2 G4

G812 G814

G1 G3 G5

G813 G815

S0 S479

G0 G2 G4

G812 G814

G1G3G5

G813G815

S0 S479

G0 G2 G4

G812 G814

G1 G3 G5

G813 G815

S0 S479


LCD-Driving-Waveform Control (R02h) (POR = 0C02h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0W 1 0 0 0 0 B/C EOR NW9 NW8 NW7 NW6 NW5 NW4 NW3 NW2 NW1 NW0

POR 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 B/C: Select the liquid crystal drive waveform VCOM.

When B/C = 0, frame inversion of the LCD driving signal is enabled. When B/C = 1, a N-line inversion waveform is generated and alternates in a N-line equals to NW[9:0]+1.

EOR: When B/C = 1 and EOR = 1, the odd/even frame-select signals and the N-line inversion signals are EORed for alternating drive. EOR is used when the LCD is not alternated by combining the set values of the lines of the LCD driven and the N-lines. NW9-0: Specify the number of lines that will alternate at the N-line inversion setting (B/C = 1). NW9-0 alternate for every set value + 1 lines.

Figure 8-1: Line Inversion AC Driver

N Frame N+1 Frame

Frame Inversion 816 line drive

Line Inversion 816 line drive

Back porch Front porch Back porch Front porch

2 3 4 820 823 824 1 2 31 822 821 5 4 5 820 823 822 821 824

N Frame N+1 Frame

Back porch Front porch Back porch Front porch

2 3 4 820 823 824 1 2 31 822 821 5 4 5 820 823 822 821


Power control 1 (R03h) (POR = 0407h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0

W 1 DCT3 DCT2 DCT1 DCT0 BT3 BT2 BT1 BT0 DC3 DC2 DC1 DC0 AP2 AP1 AP0 1 POR 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1

DCT3-0: Set the step-up cycle of the step-up circuit for 8-color mode (CM = VDDIO). When the cycle is accelerated, the driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into account the display quality and power consumption.

DCT3 DCT2 DCT1 DCT0 No. of dotclk 0 0 0 0 52 (POR) 0 0 0 1 64 0 0 1 0 70 0 0 1 1 86 0 1 0 0 84 0 1 0 1 104 0 1 1 0 104 0 1 1 1 128 1 0 0 0 208 1 0 0 1 256 1 0 1 1 416 1 0 1 1 512

Note: For 416 dotclk per line, Horizontal line frequency (fH Typ. 14.8kHz, when dotclk=6.14MHz ) For 512 dotclk per line, Horizontal line frequency (fH Typ. 16.7kHz, when dotclk=8.54MHz )

For other number of dotclk per line, the Step up frequency will be automatically divided wthin each Fline.

DCT3 DCT2 DCT1 DCT0 Step-up cycle

1 1 0 0 Fline × 1 (max dotclk = 512)

1 1 0 1 Fline × 2 1 1 1 0 Fline × 4 1 1 1 1 Fline × 8

BT3-0: Control the step-up factor of the step-up circuit. Adjust the step-up factor according to the power-supply voltage to be used.

BT3 BT2 BT1 BT0 VGH output VGL output VGH booster ratio VGL booster ratio 0 0 0 0 AVDD x 3 -(VGH - VCI) +6 -5 0 0 0 1 AVDD x 3 -(VGH - AVDD) +6 -4 0 0 1 0 AVDD x 3 -(AVDD x 3) +6 -6 0 0 1 1 AVDD x 2 + VCI -(VGH) +5 -5 0 1 0 0 AVDD x 2 + VCI -(VGH - VCI) +5 -4 0 1 0 1 AVDD x 2 + VCI -(VGH - AVDD x 2) +5 -3 0 1 1 0 AVDD x 2 -(VGH) +4 -4 0 1 1 1 AVDD x 2 -(VGH - VCI) +4 -3 1 0 0 0 Reserved Reserved 1 0 0 1 Reserved Reserved 1 0 1 0 AVDD x 3 -(AVDD) +6 -2 1 0 1 1 Reserved Reserved 1 1 0 0 Reserved Reserved 1 1 0 1 Reserved Reserved 1 1 1 0 Reserved Reserved 1 1 1 1 Reserved Reserved


DC3-0: Set the step-up cycle of the step-up circuit for 16.7M-color mode (CM = VSS). When the cycle is accelerated, the driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into account the display quality and power consumption.

DC3 DC2 DC1 DC0 No. of dotclk 0 0 0 0 52 (POR) 0 0 0 1 64 0 0 1 0 70 0 0 1 1 86 0 1 0 0 84 0 1 0 1 104 0 1 1 0 104 0 1 1 1 128 1 0 0 0 208 1 0 0 1 256 1 0 1 1 416 1 0 1 1 512



DC3 DC2 DC1 DC0 Step-up cycle

1 1 0 0 Fline × 1 (max dotclk = 512)


AP2-0: Adjust the amount of current from the stable-current source in the internal operational amplifier circuit. When the amount of current becomes large, the driving ability of the operational-amplifier circuits increase. Adjust the current taking into account the power consumption. While there is no display, such as the system is in a sleep mode, AP2-0 can be set to (0,0,0) and shutting down the operational amplifier can reduce the power consumption.

AP2 AP1 AP0 Op-amp power 0 0 0 Least 0 0 1 Small 0 1 0 Small to medium 0 1 1 Medium 1 0 0 Medium to large 1 0 1 Large 1 1 0 Large to Maximum1 1 1 Maximum


Seperate Gamma (R04h) (POR = 0400h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0

W 1 0 0 0 0 0 OLO 0 0 0 0 0 0 0 0 0 0 POR 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

OLO: When OLO = “1”, all R,G and B gamma registers are set by one set of gamma control, R30h to R3Bh. When OLO = “0”, R, G and B gamma registers are set separately by registers R30h to R3Bh, R40h to R4Bh and

R50h to R5Bh. Frame Cycle Control (R0Bh) (POR = D800h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0

W 1 NO1 NO0 SDT1 SDT0 EQ1 EQ0 0 0 EQ2 0 0 0 BTP1 BTP0 0 0 POR 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0

NO1-0: Sets amount of non-overlap of the gate output.

NO1 NO0 Amount of non-overlap 0 0 HSYNC_falling + 100 DOTCLK 0 1 HSYNC _falling + 60 DOTCLK 1 0 HSYNC _falling + 30 DOTCLK 1 1 6 DOTCLK after Source On

SDT1-0: Set delay amount from the gate output signal falling edge of the source outputs.

SDT1 SDT0 Delay amount of the source output 0 0 HSYNC_falling – 3 DOTCLK 0 1 HSYNC_falling – 7 DOTCLK 1 0 HSYNC_falling – 11 DOTCLK 1 1 HSYNC_falling – 15 DOTCLK

EQ2-0: Sets the equalizing period on source

EQ2 EQ1 EQ0 EQ period 0 0 0 No EQ 0 0 1 16 clock cycle 0 1 0 32 clock cycle 0 1 1 Reserved 1 0 0 48 clock cycle 1 0 1 64 clock cycle 1 1 0 80 clock cycle 1 1 1 96 clock cycle

1 Line period 1 Line period

Gn

Gn+1 Non-overlap period

1 Line period 1 Line period

Gn

Sn

EQ

Delay amount of the source output Equalizing

period


BTP1-0: Set the Primary booster ratio.

BTP1 BTP0 Primary booster ratio 0 0 2X 0 1 2.5X 1 0 3X 1 1 2X

Power Control 2 (R0Ch) (POR = 0005h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0

W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 VRC2 VRC1 VRC0POR 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

VRC[2:0]: Adjust AVDD output voltage. The adjusted level is indicated in the chart below VRC2-0 setting.

VRC2 VRC1 VRC0 AVDD voltage 0 0 0 5.1V 0 0 1 5.3V 0 1 0 5.5V 0 1 1 5.7V 1 0 0 5.9V 1 0 1 6.1V 1 1 0 Reserved 1 1 1 Reserved

Note: VCI=3.3V and without panel loading

Figures on the above table are target AVDD output, actual AVDD voltage depends on VCI, booster efficiency and panel loading Power Control 3 (R0Dh) (POR = 000Fh) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0W 1 0 0 0 0 0 0 0 0 0 0 0 0 VRH3 VRH2 VRH1 VRH0

POR 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 VRH3-0: Set amplitude magnification of VLCD255. These bits amplify the VLCD255 voltage 1.78 to 3.00 times the Vref voltage set by VRH3-0.

VRH3 VRH2 VRH1 VRH0 VLCD255 Voltage 0 0 0 0 Vref x 2.815 0 0 0 1 Vref x 2.905 0 0 1 0 Vref x 3.000 0 0 1 1 Vref x 1.780 0 1 0 0 Vref x 1.850 0 1 0 1 Vref x 1.930 0 1 1 0 Vref x 2.020 0 1 1 1 Vref x 2.090 1 0 0 0 Vref x 2.165 1 0 0 1 Vref x 2.245 1 0 1 0 Vref x 2.335 1 0 1 1 Vref x 2.400 1 1 0 0 Vref x 2.500 1 1 0 1 Vref x 2.570 1 1 1 0 Vref x 2.645 1 1 1 1 Vref x 2.725

Note: Vref is the internal reference voltage equals to 2.0V.


Power Control 4 (R0Eh) (POR = 2C00h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0

W 1 0 0 VCOMG VDV4 VDV3 VDV2 VDV1 VDV0 0 0 0 0 0 0 0 VCOMASPOR 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0

VCOMG: When VCOMG = “1”, it is possible to set output voltage of VCOML to any level, and the instruction (VDV4-0) becomes available. When VCOMG = “0”, VCOML output is fixed to Hi-z level, VCI2 output for VCOML power supply stops, and the instruction (VDV4-0) becomes unavailable. Set VCOMG according to the sequence of power supply setting flow as it relates with power supply operating sequence. VDV4-0: Set the alternating amplitudes of VCOM at the VCOM alternating drive. These bits amplify VCOM amplitude 0.6 to 1.23 times the VLCD255 voltage. When VCOMG = “0”, the settings become invalid.

VDV4 VDV3 VDV2 VDV1 VDV0 VCOMA 0 0 0 0 0 VLCD255 x 0.60 0 0 0 0 1 VLCD255 x 0.63 0 0 0 1 0 VLCD255 x 0.66

: : :

: Step = 0.03

: 0 1 1 0 1 VLCD255 x 0.99 0 1 1 1 0 VLCD255 x 1.02

0 1 1 1 1 External Voltage Reference

1 0 0 0 0 VLCD255 x 1.05 1 0 0 0 1 VLCD255x 1.08

: : :

: Step = 0.03

: 1 0 1 0 1 VLCD255 x 1.20 1 0 1 1 0 VLCD255 x 1.23 1 0 1 1 1 Reserved 1 1 ∗ ∗ ∗ Reserved

Note1: VCOMA < 6.0V Note2: VCOMH – VCOML < 6.0V Note3: |VCOML| < VCI VCOMAS: Set the equation of VCOML.

VCOML = α x VCOMH - VCOMA

VCOMAS α 0 0.9475 1 0.667

Software 8 colour mode (R10h) (POR = 02CCh) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0

W 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 CM1 CM0POR 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0

CM1-0: Software command enter 8 colour mode

CM1 CM0 Status 0 0 Follow the CM pin setting 0 1 Follow the CM pin setting 1 0 Enter full colour mode 1 1 Enter 8 colour mode


Double source amplifier (R15h) (POR = 0090h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0

W 1 0 0 0 0 0 0 0 0 1 Sourceamp 0 1 0 0 0 0 POR 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0

Sourceamp: Control the source amplifier biasing current

Sourceamp Status 0 Double source amplifier biasing current1 Normal source amplifer biasing current


Pixel per line (R16h) (POR = EF8Eh when x400=0, POR = C786h when x400=1 R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0W 1 XL8 XL7 XL6 XL5 XL4 XL3 XL2 XL1 XL0 HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0

POR(x400=0) 1 1 1 0 1 1 1 1 1 0 0 0 1 1 1 0 POR(x400=1) 1 1 0 0 0 1 1 1 1 0 0 0 1 1 1 0 Note: Number of dotclk for hsync active low period must be smaller than that of HBP

Only for 24-bit, 18-bit parallel and 8-bit, 6-bit serial interface. XL8-0: Set the number of valid pixel per line.

XL8 XL7 XL6 XL5 XL4 XL3 XL2 XL1 XL0 No. of pixel per line 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 0 1 0 3

: : :

: Step = 1

: 1 1 0 0 0 1 1 1 0 399 1 1 0 0 0 1 1 1 1 400 (por if x400=1)

: : :

: Step = 1

: 1 1 1 0 1 1 1 1 0 479 1 1 1 0 1 1 1 1 1 480 (por if x400=0) 1 1 1 1 ∗ ∗ ∗ ∗ ∗ Reserved

HBP6-0: Set the delay period from falling edge of HSYNC signal to first valid data.

No. of clock cycle of DOTCLK HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0

24-bit RGB 8-bit RGB (without dummy)

0 0 0 0 0 0 0 2 6 0 0 0 0 0 0 1 3 9 0 0 0 0 0 1 0 4 12 0 0 0 0 0 1 1 5 15 0 0 0 0 1 0 0 6 18 0 0 0 0 1 0 1 7 21 0 0 0 0 1 1 0 8 (por if x400=1) 24 0 0 0 0 1 1 1 9 27 0 0 0 1 0 0 0 10 30 0 0 0 1 0 0 1 11 33 0 0 0 1 0 1 0 12 36 0 0 0 1 0 1 1 13 39 0 0 0 1 1 0 0 14 42 0 0 0 1 1 0 1 15 45 0 0 0 1 1 1 0 16 (por if x400=0) 48

: : :

: Step = 1

: :Step = 3

1 1 1 1 1 0 128 384 1 1 1 1 1 1 1 129 387


Example for 24-bit RGB interface: Example for 8-bit RGB interface (without dummy):

HYSNC Pixel Data DOTCLK

D479D478D477D0 D1 D2 Dummy Dummy

Set by HBP6-0 Set by XL8-0

Cycle time of HYSYNC

Default 480 pixels per line

8 clock cycles of DOTCLK HBP6-0 = 000110

HFP

HYSNC Pixel Data DOTCLK

D479 D0 Dummy Dummy

Set by HBP5-0 Set by XL8-0

Cycle time of HYSYNC

Default 480 pixels per line

24 clock cycles of DOTCLK HBP5-0 = 000110

HFP


Vertical Porch (R17h) (POR = 0003h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0W 1 0 0 0 0 0 0 0 0 VBP7 VBP6 VBP5 VBP4 VBP3 VBP2 VBP1 VBP0

POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VBP7-0: Set the delay period from falling edge of VSYNC to first valid line. The line data within this delay period will be treated as dummy line.

VBP7 VBP6 VBP5 VBP4 VBP3 VBP2 VBP1 VBP0 No. of clock cycle of HSYNC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 1 1 3 0 0 0 0 0 1 0 0 4

: : :

: Step = 1

: 1 1 1 0 0 0 0 0 224 1 1 1 0 0 0 0 1 225 1 1 1 1 * * * * Reserved

Example for 24-bit RGB interface:

VSYNC HSYNC

Set by VBP7-0 Cycle time of VSYNC

272Lines

1st Line Last Line Dummy Lines VFP


Power Control 5 (R1Eh) (POR = 0034h) GAMAS=1 R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0W 1 0 0 0 0 0 0 nMTP 0 VCM7 VCM6 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0

POR 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 nMTP: nMTP equals to “0” after power on reset and VCOMH voltage equals to programmed MTP value. When nMTP set to “1”, setting of VCM7-0 becomes valid and voltage of VCOMH can be adjusted. VCM7-0: Set the VCOMH voltage if nMTP = “1”. These bits amplify the VCOMH voltage 0.500 to 0.998 times the VLCD255 voltage.

VCM7 VCM6 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 VCOMH 0 0 0 0 0 0 0 0 VLCD255 x 0.500 0 0 0 0 0 0 0 1 VLCD255 x 0.503

: : :

: Step = 1/512

: 1 1 1 1 1 1 1 0 VLCD255 x 0.996 1 1 1 1 1 1 1 1 VLCD255 x 0.998

Note: VCI < VCOMH < AVDD Power Control 6 (R1Fh) (POR = 1834h) GAMAS=1 R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0

W 1 0 0 0 1 1 0 0 0 VCMR7 VCRM6 VCMR5 VCMR4 VCMR3 VCMR2 VCMR1 VCMR0

POR 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 0 Note: R1F command register will only be valid when nMTP = 0. VCMR[7:0]: To set the VCM[7:0] when nMTP = “0” which is equal to programmed MTP register(MTPR) value XOR with VCMR. These bits amplify the VCOMH voltage 0.500 to 0.998 times the VLCD255 voltage.

VCM[7:0] = VCMR[7:0] xor MTPR[7:0]

VCMR7 xor

MTPR7

VCMR6 xor

MTPR6

VCMR5 xor

MTPR5

VCMR4xor

MTPR4

VCMR3xor

MTPR3

VCMR2xor

MTPR2

VCMR1xor

MTPR1

VCMR0xor

MTPR0VCOMH

0 0 0 0 0 0 0 0 VLCD255 x 0.500 0 0 0 0 0 0 0 1 VLCD255 x 0.502

: :

Step = 1/512 :

1 1 1 1 1 1 1 0 VLCD255 x 0.996 1 1 1 1 1 1 1 1 VLCD255 x 0.998


9 EXTENDED COMMAND DESCRIPTION Reminder – In order to activate extended command, user is required to send R28h-0006 prioir to the extended command in application. See below for further description on the R28h register. Gamma Buffer Biasing Current (R26h) (POR = 2800h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0W 1 0 0 1 0 1 IT2 IT1 IT0 0 0 0 0 0 0 0 0

POR 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 IT2-0: Command Control Bit, the master control of the internal command decoder. This register provides function of software reset and MTP programming.

IT2 IT1 IT0 Op-amp power 0 0 0 Least 0 0 1 Small 0 1 0 Small to medium 0 1 1 Medium 1 0 0 Medium to large 1 0 1 Large 1 1 0 Large to Maximum 1 1 1 Maximum

VCOM MTP (R28h) (POR = 0000h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0W 1 0 0 0 0 0 0 0 0 0 0 0 0 CCB3 CCB2 CCB1 CCB0

POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCB3-0: Command Control Bit, the master control of the internal command decoder. This register provides function of software reset and MTP programming.

CCB3 CCB2 CCB1 CCB0 Usage 0 0 0 0 Release Reset or no action 0 1 0 1 Driver initialization

0 1 1 0 Enable extended test command/ Enable for MTP Programming

1 0 1 0 Fire MTP 1 1 1 0 Reset all command bits to default

All other setting Reserved

VCOM Equalizing Period (R2Ah) (POR = 01D2h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0

W 1 0 0 0 0 0 0 0 1 1 1 0 1 0 VCOMEQ2 VCOMEQ1 VCOMEQ0POR 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 0

VCOMEQ2-0: Sets the equalizing period on VCOM

VCOMEQ2 VCOMEQ1 VCOMEQ0 EQ period 0 0 0 No EQ 0 0 1 40 clock cycle 0 1 0 80 clock cycle 0 1 1 160 clock cycle 1 0 0 Xmod3 / 16 1 0 1 Xmod3 / 8 1 1 0 Xmod3 / 4 1 1 1 Xmod3 / 2 Note: Xmod3 is the number of dotclk of each subcolor.


Enable SDO (R2Bh) (POR = 0520h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0W 1 ENSDO 0 0 0 0 1 0 1 0 0 1 0 FM1 FM0 0 0

POR 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 ENSDO: When ENSDO = “0”, disable the SDO pin. When ENSDO = “1”, enable the SDO pin, can read MTP or GPIO from SDO. FM1-0: Freeze VCOM

SS1 SS0 Usage 0 X VCOM switching (por) 1 0 VCOM=VCOML 1 1 VCOM=VCOMH

Secondary Booster Frequency (R2Ch) (POR = 3DDDh) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0W 1 0 0 1 1 DCYT3 DCYT2 DCYT1 DCYT0 DCY3 DCY2 DCY1 DCY0 1 1 0 1

POR 0 0 1 1 1 1 0 1 1 1 0 1 1 1 0 1 DCYT3-0: Set the step-up cycle of the step-up circuit for 8-color mode (CM = VDDIO). When the cycle is accelerated, the driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into account the display quality and power consumption.

DCYT3 DCYT2 DCYT1 DCYT0 No. of dotclk 0 0 0 0 52 (POR) 0 0 0 1 64 0 0 1 0 70 0 0 1 1 86 0 1 0 0 84 0 1 0 1 104 0 1 1 0 104 0 1 1 1 128 1 0 0 0 208 1 0 0 1 256 1 0 1 1 416 1 0 1 1 512



DCYT3 DCYT2 DCYT1 DCYT0 Step-up cycle

1 1 0 0 Fline × 1 (max dotclk = 512)


DCY3-0: Set the step-up cycle of the step-up circuit for 16.7M-color mode (CM = Vss). When the cycle is accelerated, the driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into account the display quality and power consumption.

DCY3 DCY2 DCY1 DCY0 No. of dotclk 0 0 0 0 52 (POR) 0 0 0 1 64 0 0 1 0 70 0 0 1 1 86 0 1 0 0 84 0 1 0 1 104 0 1 1 0 104 0 1 1 1 128 1 0 0 0 208 1 0 0 1 256 1 0 1 1 416


1 0 1 1 512 Note: For 416 dotclk per line, Horizontal line frequency (fH Typ. 14.8kHz, when dotclk=6.14MHz )

For 512 dotclk per line, Horizontal line frequency (fH Typ. 16.7kHz, when dotclk=8.54MHz ) For other number of dotclk per line, the Step up frequency will be automatically divided wthin each Fline.

DCY3 DCY2 DCY1 DCY0 Step-up cycle

1 1 0 0 Fline × 1 (max dotclk = 512)


Software Shut (R2Dh) (POR = 3F40h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0W 1 0 0 1 1 1 1 1 1 0 1 0 UNREG 0 SS1 SS0 0

POR 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 UNREG: When UNREG = “1”, VCIX2 primary booster is unregulated. When UNREG = “0”, VCIX2 primary booster is regulated by VRC[2:0] register. SS1-0: Entering the shut mode by software command control

SS1 SS0 Usage 0 X Follow SHUT pin status 1 0 S/W SHUT = 0, leave shut 1 1 S/W SHUT = 1, enter shut

Read SDO (R2Eh) (POR = B544h) R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0W 1 1 0 1 1 0 1 0 1 0 ENMUX RSDO 0 0 1 0 0

POR 1 0 1 1 0 1 0 1 0 1 0 0 0 1 0 0 RSDO: When RSDO = “0”, Read MTP from SDO pin. When RSDO = “1”, Read GPIO from SDO pin. ENMUX: When ENMUX = “0”, All gate tie to VGH for 4 lines period and then tie to VGL after shut mode.

When ENMUX = “1”, All gate tie to VGH after enter shut mode


10 MTP PROGRAMMING/ ERASE MTP Programming sequence Remark: * The application setup should be synchronized. Note1: nMTP must set to “0” to activate the MTP effect. Note2: VCI is suggested to be larger than 3.3V during fire MTP. Precaution:

1. All capacitors on MTP machine should be discharged completely before placing the LCD module. 2. The MTP programming voltage should not be applied when placing and removing the LCD module. 3. The MTP programming voltage should not be applied before VDDIO/VDDEXT/VCI. 4. After MTP is finished, the capacitors at VGH and VCIX2 must be discharged completely before removing the LCD module.

Figure 10-1: MTP programming circuitry

+ -

SSD2123

VGH

14.5V ±0.1V

Note: C = 1uF (built-in on the module)

C

Apply voltage at Step (4)

GND


Figure 10-2: MTP Programming Flowchart

MTP Sequence

Power up the module as application [e.g. VCI = 3.3V, VDDIO = 3.3V]* Turn on the display as normal mode to 16.7M color with a testing pattern if any

Set nMTP = “1” in R1Eh

Adjust VCOMH by VCM[7:0] in R1Eh

Toggle reset pin – Reset SSD2123

Connect a power supply to the module [VCI = VDDEXT = VDDIO = 3.3V]*

Write commands for MTP initialization:

Register Value R28h 0006h R29h 80C0h R2Dh 3F50h

Wait 200ms for activation

Connect VGH with 14.5V power supply (Figure 10-3)

Optimized VCOMH value

Not optimum value

Write the optimum value to VCM [7:0] in R1Eh and set nMTP = “1”.

Write command for firing MTP: Register Value R28h 000Ah

Wait 500ms for the process

Power down the module and remove 14.5V power supply

MTP completed


MTP Erase sequence

Remark: * The application setup should be synchronized. Precaution:

1. All capacitors on MTP machine should be discharged completely before placing the LCD module.

2. The MTP erase voltage should not be applied when placing and removing the LCD module. 3. The MTP erase voltage should not be applied before VDDIO/VDDEXT/VCI. 4. After Erasing MTP is finished, the capacitors at VGH and VCIX2 must be discharged

completely before removing the LCD module.

Figure 10-3: MTP Erase circuitry

MTP Re-Write cycle Table 10-1: MTP Re-write cycle

Characteristics Symbol Min Typ Max Units

Re-write Cycle N - - 5 Cycle Power Supply voltage for programming VGH 14 14.5 15 V Power Supply voltage for erase VGH 9 - 12 V Program time Tprog - 0.5 - s Erase time Terase - 1 - s

Note: The suggested value is based on IC evaluation result which does not include ITO resistance.

SSD2123

VGH

9V + - Note: C = 1uF

(built-in on the module) GND

GND


Figure 10-4: MTP Erase Flowchart

MTP Erase Sequence

Turn off and Power down the module

Connect a power supply to the module [e.g. VCI = 3.3V, VDDEXT = VDDIO = 3.3V, REGVDD =High]*

Write commands for erase MTP initialization: Register Value R28h 0006h R29h 80C0h R2Dh 3F50h R0Fh 013Fh

Wait 200ms for activation

Connect VGH with 9V power supply (Figure 10-3)

Wait 1s for the process

Power down the module and remove 9V power supply

MTP Erase completed

Write command for erasing MTP: Register Value R28h 0008h

Toggle reset pin to reset the module

Write command for disable erasing MTP: Register Value R28h 0000h


11 Gamma Adjustment Function The SSD2123 incorporates gamma adjustment function for the 16M-color display. Gamma adjustment is implemented by deciding the 8-grayscale levels with angle adjustment and micro adjustment register. Also, angle adjustment and micro adjustment is fixed for each of the internal positive and negative polarity. Set up by the liquid crystal panel’s specification.

RGB Interface

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0Display Data

PKP02 PKP01 PKP00

PKP12 PKP11 PKP10

PKP22 PKP21 PKP20

PKP32 PKP31 PKP30

PKP42 PKP41 PKP40

PKP52 PKP51 PKP50

PRP02 PRP01 PRP00

PRP12 PRP11 PRP10

VRP03 VRP02 VRP01 VRP00

VRP14 VRP13 VRP12 VRP11 VRP10

Positive polarity register

PKN02 PKN01 PKN00

PKN12 PKN11 PKN10

PKN22 PKN21 PKN20

PKN32 PKN31 PKN30

PKN42 PKN41 PKN40

PKN52 PKN51 PKN50

PRN02 PRN01 PRN00

PRN12 PRN11 PRN10

VRN03 VRN02 VRN01 VRN00

VRN14 VRN13 VRN12 VRN11 VRN10

Negative polarity register R G B

LCD

LCD Driver LCD Driver LCD Driver

256 grayscale Control <R>

256 grayscale Control <G>

256 grayscale Control <B>

8-bits 8-bits 8-bits

Grayscale amplifier

8-levels 64 levels

V0

V255

G7 G6 G5 G4 G3 G2G5 G4 G3 G2 G1 G0G7 G6 G5 G4 G3 G2R7 R6 R5 R4 R3 R2


11.1 Structure of Grayscale Amplifier Below figure indicates the structure of the grayscale amplifier. It determines 8 levels (VIN0-VIN7) by the gradient adjuster and the micro adjustment register. Also, dividing these levels with ladder resistors generates V0 to V255.

8 to 1

selector

8 to 1

selector

8 to 1

selector

8 to 1

selector

8 to 1

selector

8 to 1

selector

Micro adjustment registerAmplitude

adjustment register Gradient

adjustment register

VINP0

VINP1

VINP2

VINP3

VINP4

VINP5

VINP6

VINP7

PKP0 PKP1 PKP2 PKP3 PKP4 PKP5 VRP0 VRP1 PRP0 PRP1 VLCD255

GND

Ladd

er re

sist

or

V0

V4

:V18

V252

V255

3 3 3 3 3 3 3 3 4 5

Gra

ysca

le A

mpl

ifier

V32

: V56

V80

: V118

V156

: V190

V224

: V238

* Individual ladder resistors are used for positive and negative polarity.

V253


8 to 1 selector

PKP0[2:0]

VINP1

KVP1 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8

RP1 RP2 RP3 RP4 RP5 RP6 RP7

4R

8 to 1 selector

PKP1[2:0]

VINP2



1R

8 to 1 selector

PKP2[2:0]

VINP3



1R

8 to 1 selector

PKP3[2:0]

VINP4



1R

8 to 1 selector

PKP4[2:0]

VINP5



1R


8 to 1 selector

PKP5[2:0]

VINP6


4R

5R

8R 0 to 31R

5R

0 to 30R

5R

16R

5R

0 to 28R

0 to 28R

VINP7VRP1[4:0]

VINP0VRP0[3:0]

KVP0RP0

RP15

PRP0[2:0]

PRP1[2:0]

RP23

RP31

RP46

RP47

8 to 1 selector

PKN0[2:0]

VINN1

KVN1KVN2KVN3KVN4KVN5KVN6KVN7KVN8

RN1 RN2 RN3 RN4 RN5 RN6 RN7

4R

8 to 1 selector

PKN1[2:0]

VINN2


RN8 RN9 RN10RN11RN12RN13RN14

1R

8 to 1 selector

PKN2[2:0]

VINN3


RN16RN17RN18RN19RN20RN21RN22

1R

8 to 1 selector

PKN3[2:0]

VINN4



1R

8 to 1 selector

PKN4[2:0]

VINN5

KVN33 KVN34 KVN35 KVN36 KVN37 KVN38 KVN39 KVN40


1R

KVN41 KVN42 KVN43 KVN44 KVN45 KVN46 KVN47 KVN48

8 to 1 selector

PKN5[2:0]

VINN6


4R

5R

8R0 to 31R

5R

5R

16R

5R

0 to 28R

0 to 28R

VINN7 VRN1[4:0]

VINN0VRN0[3:0]

KVN0RN0

RN15

PRN0[2:0]

PRN1[2:0]

RN23

RN31

RN46

RN47

GND

VLCD255

VRP0 VRN0

VRHP VRHN

VRLNVRLP

VRN1VRP1

Ladder resistor for positive polarity Ladder resistor for negative polarity


11.2 Gamma Adjustment Register This block is the register to set up the grayscale voltage adjusting to the gamma specification of the LCD panel. This register can independent set up to positive/negative polarities and there are three types of register groups to adjust gradient, amplitude, and micro-adjustment on number of the grayscale, characteristics of the grayscale voltage. (Using the same setting for Reference-value and R.G.B.) Following graphics indicates the operation of each adjusting register.

11.2.1 Gradient adjusting register The gradient-adjusting resistor is to adjust around middle gradient, specification of the grayscale number and the grayscale voltage without changing the dynamic range. To accomplish the adjustment, it controls the variable resistors in the middle of the ladder resistor by registers (PRP(N)0 / PRP(N)1) for the grayscale voltage generator. Also, there is an independent resistor on the positive/negative polarities in order for corresponding to asymmetry drive.

11.2.2 Amplitude adjusting register The amplitude-adjusting resistor is to adjust amplitude of the grayscale voltage. To accomplish the adjustment, it controls the variable resistors in the boundary of the ladder resistor by registers (VRP(N)0 / VRP(N)1) for the grayscale voltage generator. Also, there is an independent resistor on the positive/negative polarities as well as the gradient-adjusting resistor.

11.2.3 Micro adjusting register The micro-adjusting register is to make subtle adjustment of the grayscale voltage level. To accomplish the adjustment, it controls each reference voltage level by the 8 to 1 selector towards the 8-level reference voltage generated from the ladder resistor. Also, there is an independent resistor on the positive/negative polarities as well as other adjusting resistors.

Grayscale Number

Gra

ysca

leV

olta

ge

Gradient adjustment

Grayscale Number

Gra

ysca

leV

olta

ge

Amplitude adjustment

Grayscale Number

Gra

ysca

leV

olta

ge

Micro adjustment


11.3 Ladder Resistor / 8 to 1 selector This block outputs the reference voltage of the grayscale voltage. There are two ladder resistors including the variable resistor and the 8 to 1 selector selecting voltage generated by the ladder resistor. The gamma registers control the variable resistors and 8 to 1 selector resistors. Variable Resistor There are 3 types of the variable resistors that are for the gradient and amplitude adjustment. The resistance is set by the resistor (PRP(N)0 / PRP(N)1) and (VRP(N)0 / VRP(N)1) as below.

PRP(N)[0:1] Resistance VRP(N)0 Resistance VRP(N)1 Resistance 000 0R 0000 0R 00000 0R 001 4R 0001 2R 00001 1R 010 8R 0010 4R 00010 2R 011 12R 100 16R 101 20R

: Step = 2R

:

: Step = 1R

: 110 24R 1110 28R 11110 30R 111 28R

1111 30R

11111 31R 8 to 1 selecter In the 8 to 1 selector, a reference voltage VIN can be selected from the levels which are generated by the ladder resistors. There are six types of reference voltage (VIN1 to VIN6) and totally 48 divided voltages can be selected in one ladder resistor. Following figure explains the relationship between the micro-adjusting register and the selecting voltage.

Postive polarity Negative polarity Selected voltage Selected voltage Registor

PKP[2:0] VINP1 VINP2 VINP3 VINP4 VINP5 VINP6Registor PKN[2:0] VINN1 VINN2 VINN3 VINN4 VINN5 VINN6

000 KVP1 KVP9 KVP17 KVP25 KVP33 KVP41 000 KVN1 KVN9 KVN17 KVN25 KVN33 KVN41001 KVP2 KVP10 KVP18 KVP26 KVP34 KVP42 001 KVN2 KVN10 KVN18 KVN26 KVN34 KVN42010 KVP3 KVP11 KVP19 KVP27 KVP35 KVP43 010 KVN3 KVN11 KVN19 KVN27 KVN35 KVN43011 KVP4 KVP12 KVP20 KVP28 KVP36 KVP44 011 KVN4 KVN12 KVN20 KVN28 KVN36 KVN44100 KVP5 KVP13 KVP21 KVP29 KVP37 KVP45 100 KVN5 KVN13 KVN21 KVN29 KVN37 KVN45101 KVP6 KVP14 KVP22 KVP30 KVP38 KVP46 101 KVN6 KVN14 KVN22 KVN30 KVN38 KVN46110 KVP7 KVP15 KVP23 KVP31 KVP39 KVP47 110 KVN7 KVN15 KVN23 KVN31 KVN39 KVN47111 KVP8 KVP16 KVP24 KVP32 KVP40 KVP48 111 KVN8 KVN16 KVN24 KVN32 KVN40 KVN48


Grayscale

voltage Formula Grayscale voltage Formula Grayscale

voltage Formula

V0 VINP(N)0 V43 (V32-V80)*(37/48)+V80 V86 (V80-V176)*(90/96)+V176V1 (V0-V4)*(30/40)+V4 V44 (V32-V80)*(36/48)+V80 V87 (V80-V176)*(89/96)+V176V2 (V0-V4)*(20/40)+V4 V45 (V32-V80)*(35/48)+V80 V88 (V80-V176)*(88/96)+V176V3 (V0-V4)*(10/40)+V4 V46 (V32-V80)*(34/48)+V80 V89 (V80-V176)*(87/96)+V176V4 VINP(N)1 V47 (V32-V80)*(33/48)+V80 V90 (V80-V176)*(86/96)+V176V5 (V4-V32)*(174/192)+V32 V48 (V32-V80)*(32/48)+V80 V91 (V80-V176)*(85/96)+V176V6 (V4-V32)*(156/192)+V32 V49 (V32-V80)*(31/48)+V80 V92 (V80-V176)*(84/96)+V176V7 (V4-V32)*(138/192)+V32 V50 (V32-V80)*(30/48)+V80 V93 (V80-V176)*(83/96)+V176V8 (V4-V32)*(120/192)+V32 V51 (V32-V80)*(29/48)+V80 V94 (V80-V176)*(82/96)+V176V9 (V4-V32)*(113/192)+V32 V52 (V32-V80)*(28/48)+V80 V95 (V80-V176)*(81/96)+V176V10 (V4-V32)*(106/192)+V32 V53 (V32-V80)*(27/48)+V80 V96 (V80-V176)*(80/96)+V176V11 (V4-V32)*(99/192)+V32 V54 (V32-V80)*(26/48)+V80 V97 (V80-V176)*(79/96)+V176V12 (V4-V32)*(92/192)+V32 V55 (V32-V80)*(25/48)+V80 V98 (V80-V176)*(78/96)+V176V13 (V4-V32)*(85/192)+V32 V56 (V32-V80)*(24/48)+V80 V99 (V80-V176)*(77/96)+V176V14 (V4-V32)*(78/192)+V32 V57 (V32-V80)*(23/48)+V80 V100 (V80-V176)*(76/96)+V176V15 (V4-V32)*(71/192)+V32 V58 (V32-V80)*(22/48)+V80 V101 (V80-V176)*(75/96)+V176V16 (V4-V32)*(64/192)+V32 V59 (V32-V80)*(21/48)+V80 V102 (V80-V176)*(74/96)+V176V17 (V4-V32)*(60/192)+V32 V60 (V32-V80)*(20/48)+V80 V103 (V80-V176)*(73/96)+V176V18 (V4-V32)*(56/192)+V32 V61 (V32-V80)*(19/48)+V80 V104 (V80-V176)*(72/96)+V176V19 (V4-V32)*(52/192)+V32 V62 (V32-V80)*(18/48)+V80 V105 (V80-V176)*(71/96)+V176V20 (V4-V32)*(48/192)+V32 V63 (V32-V80)*(17/48)+V80 V106 (V80-V176)*(70/96)+V176V21 (V4-V32)*(44/192)+V32 V64 (V32-V80)*(16/48)+V80 V107 (V80-V176)*(69/96)+V176V22 (V4-V32)*(40/192)+V32 V65 (V32-V80)*(15/48)+V80 V108 (V80-V176)*(68/96)+V176V23 (V4-V32)*(36/192)+V32 V66 (V32-V80)*(14/48)+V80 V109 (V80-V176)*(67/96)+V176V24 (V4-V32)*(32/192)+V32 V67 (V32-V80)*(13/48)+V80 V110 (V80-V176)*(66/96)+V176V25 (V4-V32)*(28/192)+V32 V68 (V32-V80)*(12/48)+V80 V111 (V80-V176)*(65/96)+V176V26 (V4-V32)*(24/192)+V32 V69 (V32-V80)*(11/48)+V80 V112 (V80-V176)*(64/96)+V176V27 (V4-V32)*(20/192)+V32 V70 (V32-V80)*(10/48)+V80 V113 (V80-V176)*(63/96)+V176V28 (V4-V32)*(16/192)+V32 V71 (V32-V80)*(9/48)+V80 V114 (V80-V176)*(62/96)+V176V29 (V4-V32)*(12/192)+V32 V72 (V32-V80)*(8/48)+V80 V115 (V80-V176)*(61/96)+V176V30 (V4-V32)*(8/192)+V32 V73 (V32-V80)*(7/48)+V80 V116 (V80-V176)*(60/96)+V176V31 (V4-V32)*(4/192)+V32 V74 (V32-V80)*(6/48)+V80 V117 (V80-V176)*(59/96)+V176V32 VINP(N)2 V75 (V32-V80)*(5/48)+V80 V118 (V80-V176)*(58/96)+V176V33 (V32-V80)*(47/48)+V80 V76 (V32-V80)*(4/48)+V80 V119 (V80-V176)*(57/96)+V176V34 (V32-V80)*(46/48)+V80 V77 (V32-V80)*(3/48)+V80 V120 (V80-V176)*(56/96)+V176V35 (V32-V80)*(45/48)+V80 V78 (V32-V80)*(2/48)+V80 V121 (V80-V176)*(55/96)+V176V36 (V32-V80)*(44/48)+V80 V79 (V32-V80)*(1/48)+V80 V122 (V80-V176)*(54/96)+V176V37 (V32-V80)*(43/48)+V80 V80 VINP(N)3 V123 (V80-V176)*(53/96)+V176V38 (V32-V80)*(42/48)+V80 V81 (V80-V176)*(95/96)+V176 V124 (V80-V176)*(52/96)+V176V39 (V32-V80)*(41/48)+V80 V82 (V80-V176)*(94/96)+V176 V125 (V80-V176)*(51/96)+V176V40 (V32-V80)*(40/48)+V80 V83 (V80-V176)*(93/96)+V176 V126 (V80-V176)*(50/96)+V176V41 (V32-V80)*(39/48)+V80 V84 (V80-V176)*(92/96)+V176 V127 (V80-V176)*(49/96)+V176V42 (V32-V80)*(38/48)+V80 V85 (V80-V176)*(91/96)+V176 V128 (V80-V176)*(48/96)+V176


Grayscale

voltage Formula Grayscale voltage Formula Grayscale

voltage Formula

V129 (V80-V176)*(47/96)+V176 V172 (V80-V176)*(4/96)+V176 V215 (V176-V224)*(9/48)+V224 V130 (V80-V176)*(46/96)+V176 V173 (V80-V176)*(3/96)+V176 V216 (V176-V224)*(8/48)+V224 V131 (V80-V176)*(45/96)+V176 V174 (V80-V176)*(2/96)+V176 V217 (V176-V224)*(7/48)+V224 V132 (V80-V176)*(44/96)+V176 V175 (V80-V176)*(1/96)+V176 V218 (V176-V224)*(6/48)+V224 V133 (V80-V176)*(43/96)+V176 V176 VINP(N)4 V219 (V176-V224)*(5/48)+V224 V134 (V80-V176)*(42/96)+V176 V177 (V176-V224)*(47/48)+V224 V220 (V176-V224)*(4/48)+V224 V135 (V80-V176)*(41/96)+V176 V178 (V176-V224)*(46/48)+V224 V221 (V176-V224)*(3/48)+V224 V136 (V80-V176)*(40/96)+V176 V179 (V176-V224)*(45/48)+V224 V222 (V176-V224)*(2/48)+V224 V137 (V80-V176)*(39/96)+V176 V180 (V176-V224)*(44/48)+V224 V223 (V176-V224)*(1/48)+V224 V138 (V80-V176)*(38/96)+V176 V181 (V176-V224)*(43/48)+V224 V224 VINP(N)5 V139 (V80-V176)*(37/96)+V176 V182 (V176-V224)*(42/48)+V224 V225 (V224-V252)*(188/192)+V252V140 (V80-V176)*(36/96)+V176 V183 (V176-V224)*(41/48)+V224 V226 (V224-V252)*(184/192)+V252V141 (V80-V176)*(35/96)+V176 V184 (V176-V224)*(40/48)+V224 V227 (V224-V252)*(180/192)+V252V142 (V80-V176)*(34/96)+V176 V185 (V176-V224)*(39/48)+V224 V228 (V224-V252)*(176/192)+V252V143 (V80-V176)*(33/96)+V176 V186 (V176-V224)*(38/48)+V224 V229 (V224-V252)*(172/192)+V252V144 (V80-V176)*(32/96)+V176 V187 (V176-V224)*(37/48)+V224 V230 (V224-V252)*(168/192)+V252V145 (V80-V176)*(31/96)+V176 V188 (V176-V224)*(36/48)+V224 V231 (V224-V252)*(164/192)+V252V146 (V80-V176)*(30/96)+V176 V189 (V176-V224)*(35/48)+V224 V232 (V224-V252)*(160/192)+V252V147 (V80-V176)*(29/96)+V176 V190 (V176-V224)*(34/48)+V224 V233 (V224-V252)*(156/192)+V252V148 (V80-V176)*(28/96)+V176 V191 (V176-V224)*(33/48)+V224 V234 (V224-V252)*(152/192)+V252V149 (V80-V176)*(27/96)+V176 V192 (V176-V224)*(32/48)+V224 V235 (V224-V252)*(148/192)+V252V150 (V80-V176)*(26/96)+V176 V193 (V176-V224)*(31/48)+V224 V236 (V224-V252)*(144/192)+V252V151 (V80-V176)*(25/96)+V176 V194 (V176-V224)*(30/48)+V224 V237 (V224-V252)*(140/192)+V252V152 (V80-V176)*(24/96)+V176 V195 (V176-V224)*(29/48)+V224 V238 (V224-V252)*(136/192)+V252V153 (V80-V176)*(23/96)+V176 V196 (V176-V224)*(28/48)+V224 V239 (V224-V252)*(132/192)+V252V154 (V80-V176)*(22/96)+V176 V197 (V176-V224)*(27/48)+V224 V240 (V224-V252)*(128/192)+V252V155 (V80-V176)*(21/96)+V176 V198 (V176-V224)*(26/48)+V224 V241 (V224-V252)*(121/192)+V252V156 (V80-V176)*(20/96)+V176 V199 (V176-V224)*(25/48)+V224 V242 (V224-V252)*(114/192)+V252V157 (V80-V176)*(19/96)+V176 V200 (V176-V224)*(24/48)+V224 V243 (V224-V252)*(107/192)+V252V158 (V80-V176)*(18/96)+V176 V201 (V176-V224)*(23/48)+V224 V244 (V224-V252)*(100/192)+V252V159 (V80-V176)*(17/96)+V176 V202 (V176-V224)*(22/48)+V224 V245 (V224-V252)*(93/192)+V252V160 (V80-V176)*(16/96)+V176 V203 (V176-V224)*(21/48)+V224 V246 (V224-V252)*(86/192)+V252V161 (V80-V176)*(15/96)+V176 V204 (V176-V224)*(20/48)+V224 V247 (V224-V252)*(79/192)+V252V162 (V80-V176)*(14/96)+V176 V205 (V176-V224)*(19/48)+V224 V248 (V224-V252)*(72/192)+V252V163 (V80-V176)*(13/96)+V176 V206 (V176-V224)*(18/48)+V224 V249 (V224-V252)*(54/192)+V252V164 (V80-V176)*(12/96)+V176 V207 (V176-V224)*(17/48)+V224 V250 (V224-V252)*(36/192)+V252V165 (V80-V176)*(11/96)+V176 V208 (V176-V224)*(16/48)+V224 V251 (V224-V252)*(18/192)+V252V166 (V80-V176)*(10/96)+V176 V209 (V176-V224)*(15/48)+V224 V252 VINP(N)6 V167 (V80-V176)*(9/96)+V176 V210 (V176-V224)*(14/48)+V224 V253 (V252-V255)*(20/30)+V255V168 (V80-V176)*(8/96)+V176 V211 (V176-V224)*(13/48)+V224 V254 (V252-V255)*(10/30)+V255V169 (V80-V176)*(7/96)+V176 V212 (V176-V224)*(12/48)+V224 V255 VINP(N)7 V170 (V80-V176)*(6/96)+V176 V213 (V176-V224)*(11/48)+V224 V171 (V80-V176)*(5/96)+V176 V214 (V176-V224)*(10/48)+V224


Reference voltage of positive polarity:

Reference Formula Micr0-adjusting rgister Reference voltage

KVP0 VLCD255 - ∆V x VRP0 / SUMRP -- VINP0 KVP1 VLCD255 - ∆V x (VRP0 + 5R) / SUMRP PKP0[2:0] = “000” KVP2 VLCD255 - ∆V x (VRP0 + 9R) / SUMRP PKP0[2:0] = “001” KVP3 VLCD255 - ∆V x (VRP0 + 13R) / SUMRP PKP0[2:0] = “010” KVP4 VLCD255 - ∆V x (VRP0 + 17R) / SUMRP PKP0[2:0] = “011” KVP5 VLCD255 - ∆V x (VRP0 + 21R) / SUMRP PKP0[2:0] = “100” KVP6 VLCD255 - ∆V x (VRP0 + 25R) / SUMRP PKP0[2:0] = “101” KVP7 VLCD255 - ∆V x (VRP0 + 29R) / SUMRP PKP0[2:0] = “110” KVP8 VLCD255 - ∆V x (VRP0 + 33R) / SUMRP PKP0[2:0] = “111”

VINP1

KVP9 VLCD255 - ∆V x (VRP0 + 33R + VRHP) / SUMRP PKP1[2:0] = “000” KVP10 VLCD255 - ∆V x (VRP0 + 34R + VRHP) / SUMRP PKP1[2:0] = “001” KVP11 VLCD255 - ∆V x (VRP0 + 35R + VRHP) / SUMRP PKP1[2:0] = “010” KVP12 VLCD255 - ∆V x (VRP0 + 36R + VRHP) / SUMRP PKP1[2:0] = “011” KVP13 VLCD255 - ∆V x (VRP0 + 37R + VRHP) / SUMRP PKP1[2:0] = “100” KVP14 VLCD255 - ∆V x (VRP0 + 38R + VRHP) / SUMRP PKP1[2:0] = “101” KVP15 VLCD255 - ∆V x (VRP0 + 39R + VRHP) / SUMRP PKP1[2:0] = “110” KVP16 VLCD255 - ∆V x (VRP0 + 40R + VRHP) / SUMRP PKP1[2:0] = “111”

VINP2


VINP3


VINP4


VINP5

KVP41 VLCD255 - ∆V x (VRP0 + 87R + VRHP + VRLP) / SUMRP PKP5[2:0] = “000” KVP42 VLCD255 - ∆V x (VRP0 + 91R + VRHP + VRLP) / SUMRP PKP5[2:0] = “001” KVP43 VLCD255 - ∆V x (VRP0 + 91R + VRHP + VRLP) / SUMRP PKP5[2:0] = “010” KVP44 VLCD255 - ∆V x (VRP0 + 99R + VRHP + VRLP) / SUMRP PKP5[2:0] = “011” KVP45 VLCD255 - ∆V x (VRP0 + 103R + VRHP + VRLP) / SUMRP PKP5[2:0] = “100” KVP46 VLCD255 - ∆V x (VRP0 + 107R + VRHP + VRLP) / SUMRP PKP5[2:0] = “101” KVP47 VLCD255 - ∆V x (VRP0 + 111R + VRHP + VRLP) / SUMRP PKP5[2:0] = “110” KVP48 VLCD255 - ∆V x (VRP0 + 115R + VRHP + VRLP) / SUMRP PKP5[2:0] = “111”

VINP6

KVP49 VLCD255 - ∆V x (VRP0 + 120R + VRHP + VRLP) / SUMRP -- VINP7 SUMRP: Total of the positive polarity ladder resistance = 128R + VRHP + VRLP + VRP0 + VRP1 ∆V: Voltage difference between VLCD255 and of GND.


Reference voltage of negative polarity: Reference Formula Micr0-adjusting rgister Reference voltage

KVN0 VLCD255 - ∆V x VRN0 / SUMRN -- VINN0 KVN1 VLCD255 - ∆V x (VRN0 + 5R) / SUMRN PKN0[2:0] = “000” KVN2 VLCD255 - ∆V x (VRN0 + 9R) / SUMRN PKN0[2:0] = “001” KVN3 VLCD255 - ∆V x (VRN0 + 13R) / SUMRN PKN0[2:0] = “010” KVN4 VLCD255 - ∆V x (VRN0 + 17R) / SUMRN PKN0[2:0] = “011” KVN5 VLCD255 - ∆V x (VRN0 + 21R) / SUMRN PKN0[2:0] = “100” KVN6 VLCD255 - ∆V x (VRN0 + 25R) / SUMRN PKN0[2:0] = “101” KVN7 VLCD255 - ∆V x (VRN0 + 29R) / SUMRN PKN0[2:0] = “110” KVN8 VLCD255 - ∆V x (VRN0 + 33R) / SUMRN PKN0[2:0] = “111”

VINN1

KVN9 VLCD255 - ∆V x (VRN0 + 33R + VRHN) / SUMRN PKN1[2:0] = “000” KVN10 VLCD255 - ∆V x (VRN0 + 34R + VRHN) / SUMRN PKN1[2:0] = “001” KVN11 VLCD255 - ∆V x (VRN0 + 35R + VRHN) / SUMRN PKN1[2:0] = “010” KVN12 VLCD255 - ∆V x (VRN0 + 36R + VRHN) / SUMRN PKN1[2:0] = “011” KVN13 VLCD255 - ∆V x (VRN0 + 37R + VRHN) / SUMRN PKN1[2:0] = “100” KVN14 VLCD255 - ∆V x (VRN0 + 38R + VRHN) / SUMRN PKN1[2:0] = “101” KVN15 VLCD255 - ∆V x (VRN0 + 39R + VRHN) / SUMRN PKN1[2:0] = “110” KVN16 VLCD255 - ∆V x (VRN0 + 40R + VRHN) / SUMRN PKN1[2:0] = “111”

VINN2


VINN3


VINN4


VINN5

KVN41 VLCD255 - ∆V x (VRN0 + 87R + VRHN + VRLN) / SUMRN PKN5[2:0] = “000” KVN42 VLCD255 - ∆V x (VRN0 + 91R + VRHN + VRLN) / SUMRN PKN5[2:0] = “001” KVN43 VLCD255 - ∆V x (VRN0 + 95R + VRHN + VRLN) / SUMRN PKN5[2:0] = “010” KVN44 VLCD255 - ∆V x (VRN0 + 99R + VRHN + VRLN) / SUMRN PKN5[2:0] = “011” KVN45 VLCD255 - ∆V x (VRN0 + 103R + VRHN + VRLN) / SUMRN PKN5[2:0] = “100” KVN46 VLCD255 - ∆V x (VRN0 + 107R + VRHN + VRLN) / SUMRN PKN5[2:0] = “101” KVN47 VLCD255-∆V x (VRN0 + 111R + VRHN + VRLN) / SUMRN PKN5[2:0] = “110” KVN48 VLCD255 - ∆V x (VRN0 + 115R + VRHN + VRLN) / SUMRN PKN5[2:0] = “111”

VINN6

KVN49 VLCD255 - ∆V x (VRN0 + 120R + VRHN + VRLN) / SUMRN -- VINN7

SUMRN: Total of the negative polarity ladder resistance = 128R + VRHN + VRLN + VRN0 + VRN1 ∆V: Voltage difference between VLCD255 and of GND.


12 Block Function Description

12.1 Serial Interface

Serial Interface – 4-wires (8 bits) The clock synchronized serial peripheral interface (SPI) using the chip select line (CSB), serial transfer clock line (SCK), serial input data (SDI). The serial data transfer starts at the falling edge of CSB input and ends at the rising edge of CSB.SDC determinate the data of SDI which is register or data.

Example of 4-wires (8 bits)

CSB SDC SCK SDI

Transfer ends

DB13

DB12

DB15

DB14

DB9

DB 8

DB11

DB10

DB 5 DB

4 DB 7 DB

6 DB1

DB 0 DB

3 DB 2

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

MSB LSB

Register

Transfer starts Transfer ends Transfer startsTransfer ends

Data

MSB LSBDB 5 DB

4 DB 7

DB 6 DB

1 DB0

DB 3 DB

2

1 2 3 4 5 6 7 8

Transfer starts

Data

MSB LSB

Frame 1 (Command 10h)

CSB SDC SCK SDI

1 2 3 4 5 6 7 8

Transfer starts Transfer ends

Frame 2 (Data 5Ah)

CSB SDC SCK SDI

1 2 3 4 5 6 7 8


Frame 3 (Data 78h)

CSB SDC SCK SDI

1 2 3 4 5 6 7 8



Serial Interface – 3-wires (9 bits) The clock synchronized serial peripheral interface (SPI) using the chip select line (CSB), serial transfer clock line (SCK), serial input data (SDI). The serial data transfer starts at the falling edge of CSB input and ends at the rising edge of CSB. DC bit determinate the data of SDI which is register or data.

Example of 3-wires (9 bits)

CSB SCK SDI

DB13

DB12

DB15

DB14

DB9

DB 8

DB11

DB10

DB 5 DB

4 DB 7 DB

6 DB 1 DB

0 DB 3 DB

2

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

MSB LSB

Register

Transfer starts Transfer ends Transfer startsTransfer ends

Data

MSB LSBDB 5 DB

4 DB 7 DB

6 DB1

DB0

DB3

DB2

2 3 4 5 6 7 8 9

Transfer ends Transfer starts

Data

LSB

9

C

9

D D

1

MSB

Frame 1 (Command 10h)

CSB SCK SDI


Frame 2 (Data 5Ah)

CSB SCK SDI


Frame 3 (Data 78h)

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9


1 2 3 4 5 6 7 8 9

CSB SCK SDI


Serial Interface – 3-wires (24 bits) The clock synchronized serial peripheral interface (SPI) using the chip select line (CSB), serial transfer clock line (SCK), serial input data (SDI), and serial output data (SDO). The serial data transfer starts at the falling edge of CSB input and ends at the rising edge of CSB. DC bit determinate the data of SDI which is register or data. RW bit determinate the read / write operation. Write Read

Command Code: 1. R28hx0006h – enable R2x command 2. R2Bhx8540h – enable SDO read 3. R2EhxB544h – enable MTP read status (RSDO=0) or R2EhxB564h – enable GPI read status (RSDO=1)

32Bits SPI interface for read cycle

MTP[6:0]

CSB SCK SDI SDO RSDO=1 SDO RSDO=0

Transfer ends

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Transfer starts

MSB LSB

Start byte

x xx x x xx xx xx x x xx x“0” “0” “1” “1” “1” Device ID DC RW

code

ID D R

MSB LSB

GPI3

GPI 2x x x xGPI

1GPI 0x xx x x xx x

GPI[3:0]

25 26 27 28 29 30 31 32

MSB LSB

x xx x x xx xMTP5 MTP

4x MTP6 MTP

1MTP

0MTP

3MTP

2MTP

5 MTP 4 MTP

7 MTP 6 MTP

1MTP

0MTP

3 MTP 2

x x x x x x xx

MTP[7:0]

x x x x x xx x

Transfer endsCSB SCK SDI

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Transfer starts

MSB LSB

Start byte Index register setting / Instruction,

DB5

DB4

DB7

DB6

DB 1

DB 0

DB 3

DB 2

DB13

DB2

DB 15

DB14

DB9

DB8

DB11

DB10RW DC “0” “0”“1” “1” “1”

Device ID DC RW code

ID ID


12.2 Data Control The display data and frame position information from the controller is synchronized with the Gate Drive circuit and shift registered for the Source Driver circuit.

12.3 Booster and Regulator Circuit These two functional blocks generate the voltage of VGH, VGL, VCOM and VLCD255 which are necessary for operating a TFT LCD.

12.4 Shift Register The shift registers control the direction of line scanning of source and gate.

12.5 Data Latches This block is a series of latches carrying the display signal information. These latches hold the data, which will be fed to the Source Driver to output the required voltage level.

12.6 Reset Circuit This block is integrated into the Interface Logic which includes Power On Reset circuitry and the hardware reset pin, RES . Both of these having the same reset function. Once the RES pin receives a negative reset pulse, all internal circuitry will start to initialize. The minimum pulse width for completing the reset sequence is 10us. The status of the chip after reset is given in Command Table:


13 DC CHARACTERISTICS DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, TA = -40 to 85oC)

Symbol Parameter Test Condition Min Typ Max Unit

VDDIO Power supply pin of IO pins Recommend Operating Voltage Possible Operating Voltage 1.6 - 3.6 V

VCI Booster Reference Supply Voltage Range (3)

Recommend Operating Voltage Possible Operating Voltage 2.5 or VDDIO - 3.6 V

Isleep1 Sleep mode current (VCI pin) - 40 100 uAIsleep2 Sleep mode current (VDDIO) VDDEXT=VDDIO=3.3V, VCI=3.3V - 45 100 uA

Idp Operating mode current 100pF loading at Source output VDDEXT=VDDIO=3.3V, VCI=3.3V - 10 20 mA

VCIM Negative VCI Output Voltage No panel loading -VCI - - V 91 - % AVDD AVDD x 2 primary booster efficiency1 No panel loading, ITO for CYP, CYN, AVDD,

VCI and VCHS = 10 Ohm - - 6.1 V No panel loading; 4x booster; ITO for CYP, CYN, AVDD, VCI and VCHS = 10 Ohm TBA 89.5 - %

No panel loading; 5x booster; ITO for CYP, CYN, AVDD, VCI and VCHS = 10 Ohm TBA 88.5 - % VGH Gate driver High Output Voltage

Booster efficiency2 No panel loading; 6x booster; ITO for CYP, CYN, AVDD, VCI and VCHS = 10 Ohm

TBA 80 - %

VGL Gate driver Low Output Voltage - 15.0 - - 6.0 V VCOMH VCOM High Output Voltage - - 6.0 V VCOML VCOM Low Output Voltage VCIM+0.5 - - V VCOMA VCOMA - - 6.0 V VCOMH - VCOML - - 6.0 V VLCD255 VLCD255 Output Voltage3 - - 6.0 V ∆VLCD255 Max. Source Voltage Variation -2 - 2 % VOH1 Logic High Output Voltage Iout=-100 A 0.9 * VDDIO - VDDIO V VOL1 Logic Low Output Voltage Iout=100 A 0 - 0.1 * VDDIO V VIH1 Logic High Input voltage 0.8 * VDDIO - VDDIO V VIL1 Logic Low Input voltage 0 - 0.2 * VDDIO V IOH Logic High Output Current Source Vout = VDDIO-0.4V 50 - - µAIOL Logic Low Output Current Drain Vout = 0.4V - - -50 µA

IOZ Logic Output Tri-state Current Drain Source -1 - 1 µA

IIL/IIH Logic Input Current -1 - 1 µACIN Logic Pins Input Capacitance - 5 7.5 pF RSON Source drivers output resistance - 1 - kΩRGON Gate drivers output resistance - 500 - Ω RCON VCOM output resistance - 200 - Ω TC Temperature Coefficient - -0.01 - % Note1: AVDDX2 efficiency = AVDD /(2 x VCI) x 100% Note2: VGH efficiency = VGH/(VCI x n) x 100% (where n = booster factor) Note3: AVDD – VLCD255 ≥ 0.1V


14 AC CHARACTERISTICS

14.1 Display signal output timing

Figure 14-1: Gate and source output timing (Line inversion)

Symbol Parameter Min Typ Max UnittVSYNC 1 / Frame Frequency - 16.7 - ms tHSYNC 1 / Line Frequency - 61.3 - us tSm 1 / Source Frequency - 20.4 - us tvbp Time for Vertical back porch in each frame - 4 - Hsynctvfp Time for Vertical front porch in each frame - 2 - Hsync

14.2

1 Frame

Row 0

Polarity

GR0

GG0

GB0

GR1

GG1

GB1

GRn

GGn

GBn Sm (All black pattern)

tvfp

tHSYN

tVSYNC

Row 1 Row 271 Row 0 Row 1

.

.

.

+ + +

tSm

tvbp

VSYNC

HSYNC

- - - + + +- - -


Figure 14-2- Example of color filter arrangement

14.3 Display General Information

AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDDIO = 3.3V, TA = -40 to 85oC)

14.4 Display General Information

Figure 14-3- Pixel Clock Timing

Characteristics Symbol Target Min

Target Typ

Target Max Units

24 bits parallel - - 8.69 DOTCLK Frequency 8 bits serial

fDOTCLK - - - MHz

24 bits parallel 115 - - DOTCLK Period 8 bits serial tDOTCLK - - - nSec

GR0 GG0 GB0 GR2 GG2 GB2

GR268 GG268 GB268 GR270 GG270 GB270

S0

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

S12

S467

S468

S469

S470

S471

S472

S473

S474

S475

S476

S477

S478

S479

GR1 GG1 GB1 GR3 GG3 GB3

GR269 GG269 GB269 GR271 GG271 GB271

VSYNC HSYNC DOTCLK Pixel Data tr / tf

tds tdh tCKL tCKH

tDOTCLK thv

thsys thsyh

tvsys tvsyh

tr

DATA

0.1VDDIO 0.1VDDIO

0.1VDDIO

0.1VDDIO

0.9VDDIO 0.9VDDIO

0.1VDDIO 0.1VDDIO

0.9VDDIO 0.9VDDIO

DATA0.1VDDIO

0.9VDDIO

0.1VDDIO

0.9VDDIO

0.1VDDIO DATA


24 bits parallel - 1 - Pixel Clock Period 8 bits serial tPIXCLK - 3 - tDOTCLK

24 bits parallel Pixel Clock Freq. 8 bits serial fPIXCLK - - 8.69 MHz

Vertical Sync Setup Time tvsys 5 - - nSec Vertical Sync Hold Time tvsyh 5 - - nSec Horizontal Sync Setup Time thsys 5 - - nSec Horizontal Sync Hold Time thsyh 5 - - nSec Phase difference of Sync Signal Falling Edge thv 0 - 480 tDOTCLK DOTCLK Low Period tCKL 18 - - nSec DOTCLK High Period tCKH 18 - - nSec Data Setup Time tds 10 - - nSec Data hold Time tdh 15 - - nSec Reset pulse width tRES 10 - - uSec Rise / Fall time tr / tf 5 - 25 nSec

Note: External clock source must be provided to DOTCLK pin of SSD2123Z. The driver will not operate if absent of the clocking signal.


Figure 14-4 Color Mode Conversion Timing

Note: The color mode conversion starts at the first falling edge of VSYNC after stage change of CM.

CM HSYNC VSYNC Color Mode

16.7M color mode 8 color mode 16.7M color mode


Figure 14-5 VGH Output against SHUT & RESB

Note1: The minimum cycle time of SHUT is 10 + 2 frames. Note2: DOTCLK must be provided for boosting of VGH. The above timing diagram assumed voltages and DOTCLK are continuous

supplied after power on. Note3: VGH will be forced to VCI at the low stage of RES . Note4: The minimum pulse width of RESET is 10us.

VDDIO VDDEXT VCI RES SHUT DOTCLK VGH Output

>1us 10 us

< 10 frames VGH

~Vci

>1 CLK

< 10 frames < 10 frames

>1ns


Figure 14-6 - Power Up Sequence

Characteristics Symbol TargetMin

TargetTyp

Target Max Units

VDDEXT / VDDIO on to falling edge of SHUT tp-shut 1 - - µsec Start of DOTCLK to SHUT low tclk-shut 1 - - DOTCLK Falling edge of SHUT to LCD power on tshut-lcd - - 167 msec

- - 10 frame Falling edge of SHUT to display start -- 1 line: 512 clk -- 1 frame: 278 line -- PIXCLK = 8.5MHz

tshut-on - 167 - msec

Note1: It is necessary to input DOTCLK before the falling edge of SHUT. Note2: Display starts at 10th falling edge of VSTNC after the falling edge of SHUT.

VCI VDDIO VDDEXT RESB SHUT DOTCLK HSYNC VSYNC Display High Voltage Display

ON

tp-shut

tclk-

tshut-

1st 10th

tshut-on

≥0ms

>1ns


Figure 14-7 - Power Down Sequence


TargetTyp

Target Max Units

2 - - frame Rising edge of SHUT to display off -- 1 line: 512 clk -- 1 frame: 278 line -- PIXCLK = 8.5 MHz

tshut-off 33.4 - - msec

Input-signal-off to VDDEXT / VDDIO off toff-vdd 1 - - µsec Note1: DOTCLK must be maintained at lease 2 frames after the rising edge of SHUT. Note2: Display become off at the 2nd falling edge of VSTNC after the falling edge of SHUT. Note3: If RESET signal is necessary for power down, provide it after the 2-frames-cycle of the SHUT period.

VDD VDDIO VCI RES SHUT DOTCLK HSYNC VSYNC Display High Voltage Display ON OFF

toff-

tshut-offt

1st 2nd

≥0ms

>1ns


Figure 14-8 - SPI Interface Timing Diagram & Transaction Example


TargetTyp

Target Max Units

Serial Clock Frequency fclk - - 20 MHz Serial Clock Cycle Time tclk 50 - - nsec Clock Low Width tsl 25 - - nsec Clock High Width tsh 25 - - nsec Chip Select Setup Time tcss 5 - - nsec Chip Select Hold Time tcsh 10 - - nsec Chip Select High Delay Time tcsd 20 - - nsec Data Setup Time tds 5 - - nsec Data Hold Time tdh 15 - - nsec

Note1: SPID pin connected to VSS.

CS SCL SDI

“1” “0”“0” “0” “0” “0” “1” “0” “0” “0”“0” “0” “0” “0”“0” “0”RW ID DC “0” “0”“1” “1” “1”

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

First Transmission (Register)

CS SCL SDI

RW ID DC “0” “0”“1” “1” “1”

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Second Transmission (Data)

“1” “0”“0” “1” “0” “0” “0” “1” “0” “1”“0” “0” “1” “0”“0” “0”

24

tdstdh

tcss

tcsd

tcsh

tsl tsh


14.5 8-bit Serial Interface

Figure 14-9 – 8-bit Serial Interface Timing Diagram & Transaction Example

Characteristics Symbol HV SYNC Mode

Without Dummy Units

Serial Clock Frequency 1/tDOTCLK 25.62 MHz One Line Period tH 1536 tDOTCLK

Active Data Period tdata 1440 tDOTCLK Horizontal Back Porch tHBP 48 tDOTCLK Horizontal

Horizontal Front Porch tHFP 48 tDOTCLK One Field Period tV 278 tH

Active Line period tAL 272 tH Vertical Back Porch tVBP 4 tH Vertical

Vertical Front Porch tVFP 2 tH

14.6

RR[7:0]

DEN

DOTCLK

RR[7:0]

DEN

HSYNC

YSYNC

HSYNC

Line1

Line 2

B0 R1 R0 G0 R2 G1 B1

Line3

Line 4

Line5

Line 6

Line7

Line 8

Line9

Line 10

Line11

Line 12

Line13

Line 14

Line15

Line 16

Line n

R3 G3 G2 B2 B3 R4 R5 G5 G4 B4 G6 B5 R6 B6 R7 Invalid Data

HV SYNC Mode

DEN Mode

HV SYNC Mode

DEN Mode

Without Dummy

tV

tHBP

tDEN


14.7 24-bit RGB Interface

Figure 14-10 – 24-bit Serial Interface Timing Diagram & Transaction Example

Characteristics Symbol HV SYNC Mode Units

Serial Clock Frequency 1/tDOTCLK 8.54 MHz One Line Period tH 512 tDOTCLK

Active Data Period tdata 480 tDOTCLK Horizontal Back Porch tHBP 16 tDOTCLK Horizontal

Horizontal Front Porch tHFP 16 tDOTCLK One Field Period tV 278 tH

Active Line period tAL 272 tH Vertical Back Porch tVBP 4 tH Vertical

Vertical Front Porch tVFP 2 tH

RR[7:0]

DEN

DOTCLK

RR[7:0]

DEN

HSYNC

YSYNC

HSYNC

Line1

Line 2

R3 R4 R1 R2 R7 R5 R6

Line3

Line 4

Line5

Line 6

Line7

Line 8

Line9

Line 10

Line11

Line 12

Line13

Line 14

Line15

Line 16

Line n

R10 R11R8 R9 R12 R13 R16 R17 R14 R15 R20R18 R19 R21 R22Invalid Data

HV SYNC Mode

DEN Mode

HV SYNC Mode

DEN Mode

tV

tHBP

GG[7:0] G3 G4 G1 G2 G7 G5 G6 G10 G11G8 G9 G12 G13 G16 G17 G14 G15 G20G18 G21 G22Invalid Data

BB[7:0] B3 B4 B1 B2 B7 B5 B6 B10 B11B8 B9 B12 B13 B16 B17 B14 B15 B20B18 B19 B21 B22Invalid Data

GG[7:0] Line1

Line 2

Line3

Line 4

Line5

Line 6

Line7

Line 8

Line9

Line 10

Line11

Line 12

Line13

Line 14

Line15

Line 16

Line n

BB[7:0] Line1

Line 2

Line3

Line 4

Line5

Line 6

Line7

Line 8

Line9

Line 10

Line11

Line 12

Line13

Line 14

Line15

Line n

tD550


15 ITO RESISTANCE REQUIREMENT

Pin Suggested maximum resistanceVCOM, VCHS, AVDD, AVDDG, VCI, VCIM 10 ohm VSS, AVSS, VSSRC, CSSRC 10 ohm VCORE, VREGC , VDDIO, VCIP 20 ohm C11P, C11N, C12P, C12N, C13P, C13N, C1N, C1P, C2N, C2P, C3P, C3N, CXP, CXN, VGH, VGL, VLCD255, VCOMH, VCOML, VCOM 10 ohm

TESTA, TESTB 100 ohm DOTCLK, RR[7:0], BB[7:0], GG[7:0], VSYNC, HSYNC 50 ohm X400, DENMODE, SRGB, GAMAS, SHUT, RL, TB, BGR, REV, SPID, RESB, CM, STYPE1, STYPE0, GPI0, GPI1, GPI2, GPI3, SDO, CSB, SCK, SCI, SDC, DEN

100 ohm

Note: ITO resistance and capacitance of DOTCLK, RR[7:0], BB[7:0], GG[7:0], VSYNC, HSYNC is suggested to be the same to prevent mismatch


16 SSD2123Z OUTPUT VOLTAGE RELATIONSHIP

Figure 16-1- LCD Driving Voltage Relationship

Note: The above voltages level assumed 100% efficiency of the internal booster. There has no voltage drop due to resistance

from ITO trace of the panel.

VGL

VGH

VCI

VSS

VLCD (AVDD – 0.1V max)

AVDD

VCIM

X3

VCOMH

VCOML

VCOM Amplitude


17 INTERFACE MAPPING

17.1 Mapping for Writing an Instruction

Interface Cycle BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0 GG7 GG6 GG5 GG4 GG3 GG2 GG1 GG0 RR7 RR6 RR5 RR4 RR3 RR2 RR1 RR024 bits IB23 IB22 IB21 IB20 IB19 IB18 IB17 IB16 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0

1st IB23 IB22 IB21 IB20 IB19 IB18 IB17 IB162nd IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB83rd IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0

Remark : Not connected pins

8 bits

Hardw are pins

17.2 Mapping for Writing Pixel Data(s)

Interface Color mode Cycle BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0 GG7 GG6 GG5 GG4 GG3 GG2 GG1 GG0 RR7 RR6 RR5 RR4 RR3 RR2 RR1 RR0

16.7M B7 B6 B5 B4 B3 B2 B1 B0 G7 G6 G5 G4 G3 G2 G1 G0 R7 R6 R5 R4 R3 R2 R1 R0

8 color B7 x x x x x x x G7 x x x x x x x R7 x x x x x x x

1st R7 R6 R5 R4 R3 R2 R1 R0

2nd G7 G6 G5 G4 G3 G2 G1 G0

3rd B7 B6 B5 B4 B3 B2 B1 B0

1st R7 x x x x x x x

2nd G7 x x x x x x x

3rd B7 x x x x x x x

Remark: Not connected pinsx Don't care

Hardware pins

Parallel

Serial

16.7M

8 color


18 APPLICATION CIRCUIT

Figure 18-1 - Application Diagram


19 PACKAGE INFORMATION

19.1 Die Tray Dimension


20 MTP DETAIL Fresh die

1) Example 1 - VCMR[7:0] is as default A fresh SSD2123 will have the MTP register default value of MTPR[7:0]=0x00 and R1F default value of VCMR[7:0]=0x34, which corresponds to base values [00110100] from the 8 least significant bits.

VCMR[7:0] 0 0 1 1 0 1 0 0 MTPR[7:0] 0 0 0 0 0 0 0 0

VCOMH = VCMR XOR MTPR 0 0 1 1 0 1 0 0 2) Example 2 - VCMR[7:0] is adjusted

VCMR[7:0] will exclusive or (XOR) with the MTPR default value (0x00) to form a new VCOMH default value, and it is recommended to set this command right after the power control commands when applicable.

For example, when VCMR[7:0]=0x0030 which corresponding to [110000], the resultant VCOMH will be as below.

VCMR[7:0] 0 0 1 1 0 0 0 0MTPR[7:0] 0 0 0 0 0 0 0 0

VCOMH = VCMR xor MTPR 0 0 1 1 0 0 0 0

The new VCOMH default value will become, 0x30 (Please be noted that preceding 10’b is added to the result so as to have uniformity as R1E command is sent.)

3) Example 3 - VCM[7:0] is adjusted and nMTP=1

nMTP=1 will override the default VCOMH value and is used together with VCM[7:0] to find out the optimal value against flickering. Purpose VCMR[7:0] and MTPR[7:0] is the same as example 2.

For example, when nMTP=1 and VCM[7:0]=0xA2 which corresponding to [10100010], the resultant VCOMH will equal VCM regardless the value of VCMR XOR MTPR.

VCM[7:0] 1 0 1 0 0 0 1 0

VCOMH = VCM 1 0 1 0 0 0 1 0

The new VCOMH value will become, 0xA2


Program MTP When nMTP=1, R1E command is mainly used to find out the optimal value against flickering. The MTPR will be programmed as below. (The equivalent VCOMH value is simply VCM[7:0] if nMTP is 1)

1) Example 1 - VCMR[7:0] is as default, target VCOMH value is equivalent to

VCM[7:0] = 0xB0. When R1E-0x02B0 is sent, VCM[7:0] will be [11010000]. The MTPR will be the XOR result of VCM[7:0] and VCMR[7:0]. In this case, VCMR[7:0] is the default = 0x36.

VCM[7:0] 1 0 1 1 0 0 0 0

VCMR[7:0] 0 0 1 1 0 1 0 0 MTPR[7:0] 1 0 0 0 0 1 0 0

The result in MTPR means bit 7 and bit 2 in MTPR[7:0] are programmed.

2) Example 2 – VCMR[7:0]=0xB0 is adjusted, target VCOMH value is equivalent to VCM[7:0] = 0xB0. For optimum performance against flickering with different panel characteristic, VCMR[7:0] can be adjusted to reduce the frequency on MTP execution. For VCMR[7:0]=0xB0 is adjusted, and VCOMH target is same as VCM[7:0]=0xB0, the below result shows that MTP is not required if VCMR[7:0] is adjusted.

VCM[7:0] 1 0 1 1 0 0 0 0

VCMR[7:0] 1 0 1 1 0 0 0 0 Result

MTPR[7:0] 0 0 0 0 0 0 0 0

However, SSD2123 requires VCMR[7:0]=0xB0 to be updated when power up every time in order to produce the target VCOMH value of VCM[7:0]=0xB0

VCMR[7:0] 1 0 1 1 0 0 0 0

MTPR 0 0 0 0 0 0 0 0 VCOMH = VCMR xor

MTPR

1 0 1 1 0 0 0 0

Please be reminded that MTP registers can be programmed once and have to be erased before reprogrammed.


3) Example 3 – VCMR[7:0]=0xB0 is adjusted, target VCOMH value is equivalent to VCM[7:0] = 0xB1. Upon process variation, there may be a variation in the panel characteristic, MTP may be used to adapt this. VCMR[7:0] is adjusted to 0xB0 as example 2 to reduce the frequency on MTP execution. For VCM[7:0]=0xB1 is adjusted to adapt the process variation, and VCOMH target is same as VCM[7:0]=0xB1, the below result shows that only bit 0 of MTPR is required for programming if VCMR[7:0] is adjusted.

VCM [7:0] 1 0 1 1 0 0 0 1 VCMR[7:0] 1 0 1 1 0 0 0 0

Result MTPR

0 0 0 0 0 0 0 1

However, SSD2123 requires VCMR[7:0]=0xB0 to be updated when power up every time in order to produce the target VCOMH value of VCM[7:0]=0xB1

VCMR[7:0] 1 0 1 1 0 0 0 0

MTPR 0 0 0 0 0 0 0 1 VCOMH =

VCMR XOR MTPR

1 0 1 1 0 0 0 1


Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any, and all, liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typical” must be validated for each customer application by the customer’s technical experts. Solomon Systech does not con-vey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part.

All Solomon Systech Products complied with six (6) hazardous substances limitation requirement per European Union (EU) “Restriction of

Hazardous Substance (RoHS) Directive (2002/95/EC)” and China standard “电子信息产品污染控制标识要求 (SJ/T11364-2006)” with

control Marking Symbol . Hazardous Substances test report is available upon requested.

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