SEPIC derived three-phase switching mode rectifier with sinusoidal input current

J.-J.Shieh

Abstract: A SEPlC derivcd three-phase rectifb is proposed to achieve clean sinusoidal input current, unity power factor, step up/down DC voltage and to be insensitive to input voltage distortion. Depending upon how many boost modes are choscn and which class of generalised zero voltage space vector is selccted to obtain thc equivalent DC duty cycle, different control strategies can be obtained. It is seen that through introduction of an equivalent duty cycle the DCiDC SEPlC converter function can be maintained without affccting the desired rectifier characteristic. The input to output voltage gain for two control strategies is also derived. Finally, a hardware implementation example and somc cxperiniental results are given to demonstrate the validity of the proposed rectifier.

1 Introduction

In reccnt years, with advances in power semiconductor devices, the pulse width modulation (PWM) techniquc has been uscd more frequently to improve the quality of input current waveform and power factor [I-31. In addition, from thc energy saving point of view and also to satisfy har- monic standards such as IEC 1000-3-2 and EN 60555-2 [2, 31, the reduction in input current harmonics and improved power factor of a switching power supply is very important.

In rcsponse to the abovc requirements, a significant number of boost-type PWM rectifier systems havc been proposed [47] which have the advantage of sinusoidal mains current and controllability of output voltage. How- ever, due to the boost-type converter characteristic, the out- put voltage must be larger than thc peak value of the mains line-to-line voltage. Hence, a stcp down DCiDC converter is commonly added for low voltage applications. Although this scheme offers many possibilities, one concern is that the powcr delivered to the load is processed twice with a resulting penalty in the overall efficiency. Many single-stage single-phasc ACiDC converters have been proposed [S, 91. However, very few papers conccrning single-stage three- phase step-up/down ACiDC converters are available in existing literature. Although some Ihrcc-phase ACiDC con- verters have been proposed offering a step-upidown capa- bility [ 1&13], thc disadvantages of pulsating input currents remain to be overcomc. Recently, Kolar et al. proposed a threc-phase SEPIC-type AC/DC converter to improve the input current and power factor [14]. However, it requires 18 extra diodes that incur significantly greater conduction losses.

In this paper, a SEPlC derived three-phase rectifier is proposed such that control of the AC and DC parts of the

0 IEE, 2000 IEE Proceedings online no. 2oooO508 DOL 10.1049/ipepa:20000508 Paper first received 19111 October I999 and in revised Ionii 15th March 2000 The author is with the Department of Electrical Engineering, Ta I-iwa Institutc of Technoloby, Chiunglin, Hsinchii Hsien, 30740, Taiwan

convcrter circuit can be integratcd to achieve the ideal char- acteristic of a single-stage three-phase SEPTC AC/DC con- vertcr. In other words, the input current can be made pure sinusoidal with unity power factor and the output voltage can be stepped up/down to give pure DC. This is achieved by applying generaliscd zero voltage space vectors as in [15, 161 such that an equivalent duty cycle for the DC part of the converter can be obtained without affecting the recti- fier circuit operation.

2 generalised zero voltage space vector concepts

Circuit configuration and a brief review of

Thc basic circuit topology of the proposed single-stage PWM three-phase SEPIC converter is shown in Fig. 1. As can be observed from the full bridge of Fig. 1, theoretically thcre are 64 combinations for the six-switch status. How- cvcr, there are 37 combinations resulting in open circuit of the line current. Hence, only 27 combinations can be used for practical converter control. To be more precise, the v/, voltage of the converter in Fig. 1 can be expressed mathe- matically as follows:

vk = FZ(S~L,S~~'L,S?~~,S~~,~,S?~,:,,S~IIR,~'~/~?LS) k = 1 , 2 , 3 ( I )

where V, is expressed as a runclion of the switch status and thc DC bus voltage, and SI,., is defined as follows:

1 0

when S, (or D a ) is turned ON whcii S, (or I l l ) is turned OFF

i = 1 , 2 , . . . , 6 ( 2 ) i 'SZ"i

Next, definc the corresponding voltage space vector for each switch status as follows:

2 3

V m , E - (VI + via, + E v, + ,il'Q

m , = 0 , 1 , 2 , . . . , 7 n = 0 , 1 , 2 , . . . ,7 a = ej120" -

( 3 )

[Vi 1 4 & ] = R e { [ 1 a2 a ] V n I n } (4)

and the inverse formula is given as:

I E E Piv~<~.-Eli~c/?. POIW? Appl. , Vi)/. 147, N o 4, Jirly 2000 2x6

0

N Fig. 1

By substituting eqns. 1 and 2 into eqn. 3, one can obtain the following useful space vectors.

Proposed tlwl~-pluw SEPIC coltv(wr

Table 1: Generalised voltage space vectors

Switch state v,,,, vn + .iVQ Class

= { (;;Ws gm 3 / : = 7 ~ ~ = 7 1 , = 1 , 2 ) . . . , G sWl sW2 sW3 sW4 sM svla vinn vD vQ

(5) 1 1 0 0 0 1 VI, vbL,d3 d3 vb~,.@

0 1 0 1 0 1 v,, -vb& d3 vbud3 vi, # n, The above 27 voltage space vectors are listcd in Table 1 . 0 1 1 1 0 0 v33 - 2 v b ~ d 3 0

0 0 1 1 1 0 v44 -vbus/3 4 3 Vbus/3

V22, ..., Vfifi) and the two conventional zero voltage spacc 1 0 1 0 1 0 v55 v/bus/3 4 3 Vbus/3

From Table I one can see that class A and B space vectors corresponds to the six nonzero voltagc space vectors (VI I ,

A

vectors ( V70, Vo7), respectively. Howevcr, there arc I9 more 1 0 0 0 1 1 v6(3 2VbLiJ3 0

zero voltage space vectors, namely class C, D and E which represent the cases of short circuit of one, two or three

zero voltage space vectors are also called geiieraliscd zero

0 0 0 1 1 1 V o 7 0 0

arms of V,l,,,y of the converter, respectively. The above 21 1 1 1 0 0 0 V 7 0 0 0

voltage space vectors [15, 161. As will be seen in later 1 1 0 1 0 1 v650 0 Sections, by applying the gcneralised zero voltage spacc 1 0 1 1 1 0 v560 0 vectors onc can easily extend a DCiDC SEPIC converter to 1 1 0 0 1 1 v 6 3 0 0 a single-stage three-phasc ACiDC SEPlC converter. 0 1 1 1 1 0 v360 0

3 Operating principle of the proposed rectifier 1 0 1 0 1 1 v530 0

3. 'I One boost-mode control strategy C For simplc illustration of the operating principle, first, con- 0 0 1 1 1 1 v1,o 0 sider ideal thrcc-phase input line current commalids as 0 1 0 1 1 1 V , , O 0

largest absolute valuc with two othcr currents having 1 1 1 1 0 0 v 7 , 0 0

smaller magnitude and oppositc sign. Take interval 2 as an 1 1 1 0 1 0 v , , o 0 example, one can see that phase-1 current coniinand has 1 1 1 0 0 1 v 7 , 0 0

S4 of Fig. I . 0 1 1 1 1 1 v 3 7 0 0

I I I I I I . * I I 1 0 1 1 1 1 v 5 , 0 0

; ' 1 ; 12 ; I 13 ; 1 1 0 1 1 1 v 6 7 0 0

0 1 1 1 0 1 v 3 , 0 0

shown in Fig. 2. Obviously, in each lime intci-val none of thc input line currents change sign and one current has the 1 0 0 1 1 1 v 4 , 0 0

the largest magnitude and can be conducted through D , or

I * I I . * I A

I I I I I I D 1 1 1 1 1 0 v 7 6 0 0

1 1 1 1 0 1 v,50 0

1 1 1 0 1 1 v 7 , 0 0

E 1 1 1 1 1 1 V 7 7 0 0

0 Now, define thc following noimalised three-phase cur- rent errors:

(6) ik - i ;

Vt,., e k = ~ k = 1 , 2 , 3

where Vtri is the peak valuc of the triangular wavc S(t) and zk is the lcth phasc current command. Thus, by comparing qi with a triangular wave S(t), one has the following five

.I

I I I I I I ! I ! I I ! modes corresponding to cight states of p,{t) (E S(t) - e;), i = Fig. 2 k/c.trl iliree-pliusc. in/,ut current wvcfi i r i i i I , 2, 3.

I E E Proc..-Elect,.. P O l l ~ O ~ A / i / I / , , vo/, 147, N o . 4, JLC/I> 2000 281

Mode 1: pl > 0, hi2 < 0, p3 < 0 This means both currents i2 and i3 should be increased and il should be decreased. In this situation, the voltage vector V,, should be selected. The corresponding equivalent circuit is shown in Fig. 3 where the inductor currents il and i,, flow through the diode D. From Fig. 3 it can be seen that C, is charged through diodes D,, D,, D, and D using energy from both the input and the three input inductors L,s. At the same time, energy stored in LI feeds the output. Therefore, iLI is also decreased. Mode 2: pI > 0, ,u2 < 0, ,u3 > 0 This means that currents i l and i3 should be decreased and i2 should be increased. In this situation, the voltage vector VS? should be selected. The corresponding equiv d 1 ent cir- cult is shown Fig. 4 where the inductor currents (i, + i3) and iL1 flow through the diode D. From Fig. 4 it can be seen that CI is charged through diodes DI, D5, S3 and D using energy from both the input and the three input inductors L,,. In addition, energy stored in Ll feeds the out- put. Therefore, iLI is also decreased. Mode 3: ,U, > 0, p2 > 0. ,u3 < 0 This means currents il and i2 should be decreased and i3 should be increased. Hence, the voltage vector V I l is cho- sen. Fig. 5 shows the resulting circuit for this mode where the inductor currents (il + i2) and i,, flow through the diode D. From Fig. 5 one can see that CI is charged through diodes DI, D,, S2 and D using energy from both the input and the three input inductors L,s. At the same

time, energy stored in L , feeds the output. Therefore, i,,l is also decreased.

Mode 4: ,uI > 0, p2 > 0, p3 > O(pI < 0, p2 < 0, p3 < 0) This means currents i l , i2 and i3 should be decreased (increased). Theoretically, this mode cannot happen. How- ever, due to transient disturbance or unexpected noise, it may happen. Hence, the voltage V,, (Vu,) is chosen to reduce current errors without changing the operating prin- ciple of the subcircuit corresponding to a traditional DC to DC SEPIC converter. The corresponding equivalent circuit for the case p1 > 0, p2 > 0, p3 > 0 is shown in Fig. 6. Then, in the next switching period, if operation is changed to the other mode, current errors can be reduced continuously.

Mode 5: pl < 0, p2 > 0, ,u3 > 0 (or p3 < 0), or ,ul < 0, ,u2 <

I n this mode, to maintain the normal operating principle of the traditional SEPIC DC/DC converter for the DC part of the proposed converter any generalised zero voltage space vectors of class B, C, D or E can be applied. For example, from the viewpoint of reducing conduction losses, the gen- eralised zero voltage space vector of class E, namely V77 is preferred. vCI and vo reverse biases the diode D and induc- tor currents il,. and iLI flow through the switches as shown in Fig. 7. C, discharges through the six switches, transfer- ring energy to the inductor L,. Therefore, iLl increases. At the same time, the input feeds energy to the three input inductors.

03 p3 > 0

0

Fig.4

288

N Equivulent circuit during tivie inteiwl2 of'bii. 2; ~ n o h 2

No. 4, July 2000

0

L I

0

Similarly, the selected voltage space vectors for other intervals in Fig. 2 can be obtained easily. From the above, one can sec that the iLI current is boosted only during mode 5 by vcI. Also, practically, due lo thc finite turn on/off time of semiconductor devices, it is possible to havc a very short time period short circuit of the bridge arms during mode transitions. This effect is similar to that of mode 5 corrcsponding to the different generalised zcro volt- age space vector applied and is allowed for in thc proposcd converter.

N

R

3.2 Two boost-modes control strategy From thc prcvious Section, one can see that in mode 4 a traditional zcro voltage vector V,,, is applied. Although the AC current errors can be reduced, however, there is no energy transfer in C', capacitor. I n fact, one can apply any other generalised zero voltage space vector a s well. Simi- larly, to reduce conduction losses, V,, is preferred. and the rcsulling equivalent circuit for mode 4 is the same as Fig. 7. Thc abovc procedure can be repeated for the other inter- vals of Fig. 2 to select thc voltage space vectors. Hence, in

this new control strategy, the inductor current iLI is boostcd for two modes. As can bc observed from the later results of voltage gain, this control strategy can achieve higher V,, than the one boost-mode control strategy.

t t

t t

t t

0 t

sw4

0 t

sw2

sw5

0 t

0 t

t t , , . , I , . , , . . , . . ,

SW6" ; f j , . . j f j . j . : I

From thc above results, one can also see that the switch- ing sequences can be systematically arranged according to Table 1 for the given example and the traditional lock-out circuit can be eliminated. In addition, it is now obvious that the DC output voltage can be adjusted by the equiva- lent duty ratio of the generalised zero voltage space vector (as will be discussed latcr) through output voltage feed- back. For referencc, Fig. 8 depicts how to use a typical sinusoidal PWM control schemc to generate the desired gating signal pattern for a two boost-inodes control strat- egy. From Fig. 8 one can see that vY/< (k = 1, 2, 3) is the primitive gate control signal of switch S , obtained for the conventional SPWM scheme, i.c.

Next, from the previous two boost-mode control strategy, for to < t < t , and t6 < t < t7, V,, is added for mode 5 to obtain the desired switch states of S,,, Se and S , , in Fig. 8. Similiarly, for t3 < t < t4, V77 is applied to obtained

290

the desired switch states of SH,4, S , and Sw6 in Fig. 8. The grey areas marked with A or B in Fig. 8 show the differ- ence betwccn the traditional sinusoidal PWM gating signal and the proposed gating signal patten.

With the desired goal of a clean sinusoidal current wave- form one has

where 0 and A4 are the modulation phasc displacement a i d modulation index respectively [ 171. To avoid explicit calcu- lation of H and A4 and to achieve adjustablc output DC voltage, a closcd loop output voltage control is adopted in later hardware implementations.

4 Derivation of the input to output voltage gain

To further explore thc operating range of thc proposed converter, consider the resulting equivalent circuits of Figs. 3- 7 during time interval 2 of Fig. 2 for one switching cycle from to to t7 as sliown in Fig. 8. Similarly, the corre- sponding state equations for the remaining time intervals can also be obtained.

Assume that the input voltages and input currents are given as follows:

k = 1 , 2 , 3

(9)

2T(k ~ 1)

27r(k - I) 3

where V,,, is the maximum input phase voltage and I,,, is thc maximum input line current, and a phase shift @ is included to adjust power factor.

Considering eclns. 9 and 10 and using the state-space averaging technique [18, 191, one can obtain thc state-aver- aged equation of the proposed converter as follows:

where R,,, L,, are the equivalent series resistancc and induct- ance of the three-phase inductor respectively, C, and CO are the capacitances, and dz represents the equivalent aver- aged duty cycle of the generalised zero voltage vector,

for interval ( I ) , ( 3 ) and (5) of Fig. 2

& = { l-max{d,,} + k,dz7 for interval (a), (4) and (6) of Fig. 2

min{d,} + k,dz:o

1 171, - + -

2 2

0 1

- - _

(12)

(13)

for one boost-mode control schemc for t,wo boost-modes control schemc k , = {

dz0 and dz7 denote the equivalent averaged duty cycle of Vq7 and V70, respectively. In addition, from Figs. 2 and 8, it is straightforward to obtain the following cxpression:

dzo = X (1 + [min{ek} - max{ek}])

k E {1,2,3} (14)

dz7 = (1 - A) (1 + [miii{ek} - max{ek}])

k: E {1,2,3} (15)

dzo - 1 - min{ek} A = -

ClzO + dZ7 2 + max{ek} - iniri{e~} k E {1,2,3} (16)

Using the space vector definition of eqn. 3 for v,~,, i/<, and d/<, substituting eqns. 9 and 10 into eqn. I 1 in the synchro- nous reference frame and assume dz0 = dz7 (i.e. A = 0.5) [ I 51, one can express eqn. 11 in the following matrix form

From eqn. 25 it is interesting to see that Dz can be repre- sented approximately as an equivalent duty cycle similar to that of a conventional DC/DC converter.

Assume that the parasitic losses are neglected and consid- ering the operating condition of unity power factor (@ = 0) under steady state, one can obtain the input lo output volt- age transfer ratio:

To give some insight to cqn. 26, Fig. 9 shows plots of the transfer ratio G in terms of modulation index M and phase displacement 19 for thc two control strategies. From the above results one can see that the proposed converter indeed not only has both step-up and step-down capabili- ties with clean sinusoidal input currents and unity power factor, but also eliminates the disadvanvage of a pulsating input current.

.. ..,

0

modulation phase displacement, degrees

a

modulation phase - 3 0 7 .o modulation index(M) displacement, degrees

b Fig .9

ror ( ( I ) onc boost-iiiode control stratcgy and (/I) two boost-modes control strategy

Inj)iit-to-outl,ut wltcige trcitisfi!i. r d o idwn tlir tonvm'fei' is ojiowtcd cit liIlifJ1 poll~erfilctur

5 Hardware implementation and experimental results

As an illustration of implementation, a block diagrdni is shown in Fig. 10 whcrc an EPROM (2732A) is applied to sclcct the appropriatc vollage space vectors as shown in

29 I

Table 1 and in the mean timc to integrate the abovc two control schemes. To prevent low frcquency ripple on the input line current, thc voltagc controller must be opcrated with a constant low frequency gain. In addition, the current controller should be operated with high frequency gain and bandwidth to enable the line currcnt to follow the pro- grammed linc current command as closcly a s possible.

(EPROM 2732A) address bus

waveform generator

zero crossing generator detector

L ~ y Lf pq controller vo+v;

signal generator

-r- : 2(k- 1 )X

sin(oJt - _ _ - 3 $I

At each time instant of Fig. 2 each switch of the con- verter is connected or discoiiiiected depending on whether U, is greater or less tliaii zero and the interval status or thc input current commands togethcr with the chosen control strategy. For more detailed cxplanation of the control, define the following notation:

(28) I me-boost iiiode scliernc 0 two-boost niotlt’s sc.licwic

M D = { where the definitions or the notation can be understood from Fig. IO.

Table 2: Partial switching pattern when the proposed con- verter is operated with one boost-mode control strategy

Input address bus signal

MD GI G2 G3 F1 F2 F3

1 0 1 0 0 0 0 1 0 1 0 0 0 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 1

Output data bus signal

Sm SI, sw3 sw4 Sm s m 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1

1 1 0 0 0 1 1 1 1 0 0 0

For example, during interval 4 of Fig. 2 (GI = 0, C;, = 1 and G3 = 0) suppose that one-boost mode is chosen ( M D = I) , then this time interval can be characterised a5 ( I , 0, I , 0) corresponding to the sequence (MD, GI, G2, G3). Hence, if a sequence (1, 0, 1 , 0) is obtained, then one knows that a one-boost mode control schemc is chosen and the currents are controlled separately by the status of vPx, k = 1, 2, 3.

292

Thcrefore, to obtain the states S , - S, in Fig. 10, onc can construct a table as shown in Table 2 where, due to limita- tions of space, only partial results are listed. It is seen that thc proposed ROM-based current controller is siniple in both concept and implementation. Additionally. desirablc chal-acteristics such a s fixed switching frequency, fast rcsponse and insensitivity to source imbalance and/or dis- tortion arc still maintained.

2msldiv i (2msldiv)

, . . . , . . . . . ......... I ......... j ......... i ......... : ......... ................... i...... NORM.500kS/s . . . . .

............................................ ................................................ . . . . . . . . . . . . . . . . . .

I

a

1 Omsldiv i i (lOms/div) I I N0RM:IOOkSls

. . . . . .

............................................................................

top:40V/div, bottom:2Vldiv b

ciarccnl tiid oiitpiir iwlicige,fur .stei?-up i~torlc Fig. 12 ( i phmc I input current h DC and ripplc componcnts of lhe oulptit vollagc

To illustrate the significance and facilitate the undcrsand- ing of the theoretical results obtained in the previous scc- tions a prototype with unity power fiictor and one boost- mode control strategy having the following parameters was constructed: V,,, = 50V, <, = 80V,,f; = 3.0kHz, w = 377rad/s L,, = 6.5niH, X,\ = 0.458, I,, = 1.25niH

Fig. 1 1 shows the waveform of the three-phase input current. From Fig. I 1 one can see that tlie three-phase currents are sinusoidal and balaiiccd. Fig. 12 shows phase 1 input current and the output voltage. From Fig. 12 one can sec that the input current is in phase with the corre- sponding input phase voltage. In addition, tlie input currciit harmonic is small and the output voltage is clean DC as expected. To show the step-down capability of the proposed converter, the voltage command Vi,'' is changed from 8OV to 40V. The waveform of the phase 1 current and the output voltage arc shown in Fig. 13. From Fig. 13 one can sec that even when thc outpiit power is very low, the line current is still sinusoidal. Additionally, the input power factor and output voltage arc iiiaintaincd at unity and with a clean DC output voltage. Finally, Fig. 14 shows the efficiency of the proposed converter. It is worth mentioning here that when V77 is applied the converter

C , E 1 1 O O , f i , C', 47OyF

. .

lOms/div (1 Omsidiv j

NORM.1 OOkSis +

....................................................................................................

25V/div, 1.25A/div a

. . . . .

. . . . . . . . .

.................................................................................................... . . . . . . .

load power is supplied by the output capacitor. Hence, the maxiniuni output power at reasonable cost is geiicrally limited when compared to lid1 hricige boost types.

loo 90 [I

10

0 L I power, W I

M 0 200 400 600 800 1000

6 Conclusions

In this paper, a SEPIC derived three-phase rectilier is proposed such that control of thc AC and DC parts of the converter circuit can be integrated to achieve the ideal char- acteristic of 21 single-stage three-phase SEPIC ACiDC recti- fh-. In other wolds, the input current can be made pure sinusoidal with unity power factor and the characteristics of the DC part are the same as with a conventional DC/ DC SEPIC converter. In fact, the above mentioned features are ohtaiiicd with the Cuk type three-phase AC/ DC converter [ 161. Hence, the main advantages and disad- vantages of the conventional DC/DC SEPIC (Cuk) converter [I91 still exist in the SEPlC (Cuk) derived three- phase rectifier. I t is seen that, depending upon how many boost modes are chosen and which class of gencralised zero voltage spacc vector is selected to obtain the equivalent DC duty cycle, one can obtain different control strategies. Although the generalised zero voltagc vector V,, was chosen in the boost niode(s) in the previous Section as an example, any other suitable generalised zero voltage vector of class B, C, D 01- E can be applied (say to reduce the switching number or from other considerations) to obtain different control strategies. It is seen that control of the switches used can be simplified and the lock-out circuit or the converter can be elirninatcd.

The input-to-output transfer ratio for the examples con- sidered was derived and linally, a prototype was con- structed and experimental results obtained to verify the validity of the proposcd converter.

7 Acknowledgment

The author thanks C.T. Pan of the Tsing Hua Uuiverity in Taiwan for his valuable suggestions and kindly assistancc.

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