SERIAL COMMUNICATION INTERFACE (SCI)

Serial Communications Interface Module MTT48 7-1

SERIALCOMMUNICATION

INTERFACE(SCI)


Module Objective

Understand serial communications format

Understand serial communications options

Configure SCI for desired baud rate

Set desired character bit length and parity

Enable transmitter, receiver and interrupt control

Transmit and receive data

Module exercise:

Configure the SCI to transmit and receive characters to/from

another device under interrupt control.


Serial Communication Interface Module

68HC08CPU

SystemIntegration

Module(SIM)

ClockGeneration

Module(CGM)

TimerInterfaceModule(TIM)

DirectMemoryAccessModule(DMA)

SerialCommunications

Interface(SCI)

Internal Bus (IBUS)

SerialPeripheralInterface

(SPI)

RandomAccess

Memory(RAM)

ElectronicallyProgrammable

ROM

LVI

COP

Monitor ROM

IRQ

BREAK

RESET

Full duplex high-speed asynchronous

Programmable 8 or 9 bit character lengths

Two receiver wakeup methods

Separate Receiver and Transmitter DMA Service Requests

Separate Receiver and Transmitter CPU Interrupt Requests

Separately Enabled Transmitter and Receiver

Programmable Transmitter Output Polarity

Interrupt-driven operation with Eight Interrupt Flags:

•Transmitter Empty

•Transmission Complete

•Receiver Full

•Idle Receiver Input

•Receiver Overrun

•Noise Error

•Framing Error

•Parity Error

Low power operation mode

Receiver Framing Error Detection

Hardware Parity Checking


Double Buffering

SCRF Flag sets each time new data is transferred from the serial shift register to the RDR Buffer.

DATA OUT

TDR BUFFER

RDR BUFFERSHIFT REGISTER

SHIFT REGISTER

DATA IN

DATAOUT

DATAIN

R8

T8

TRANSMITTER: RECEIVER:

SCTE Flag sets each time new data is transferred from the TDR Buffer to the transmit serial shift register.

••

WRITE to SCDR writes TDRx BufferREAD to SCDR reads RDRx Buffer


SCI Data Formats

8 - Bit Data Format (10 bit total length)

STARTBIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

STARTBIT

NEXT

STOPBIT

Extra Stop Bit or Parity Bit

9 - Bit Data Format(11 bit total length)

STARTBIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8

STARTBIT

NEXT

STOPBIT

Extra Stop Bit or Parity Bit

Serial Communications Basics


Serial Communications Basics

Special Data Characters

Break - Has no Start or Stop bits, exists as a logic zero for 10 or 11 bit times ( 8 or 9

data format respectively )

Idle - Has no Start or Stop bits, exists as a logic one for 10 or 11 bit times ( 8 or 9

data format respectively )

Preamble - A synchronizing Idle character


SCI I/O Registers

Seven I/O registers control and monitor SCI operation

• SCI Control Register 1 (SCC1)



• SCI Status Register 1 (SCS1)

• SCI Status Register 2 (SCS2)

• SCI Data Register (SCDR)

• SCI Baud Rate Register (SCBR)


Baud Rate Selection

SCI Baud Rate Register

• Selects baud rate for SCI transmitter

• SCI baud rate prescaler bits (SCP1,SCP0)– Divide crystal frequency by multiple of 64

1, 3, 4, or 13

• SCI baud rate select bits (SCR2 - SCR0)– Selects transmit baud rate from prescaler output – Divide prescaler output frequency

1, 2, 4, 8, 16, 32, 64, or 128

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ: SCP1 SCP0 SCR2 SCR1 SCR0SCBR


Baud Rate Selection Example:

0 0 1 76.80K Baud

0 1 3 25.833K Baud

1 0 4 19.20K Baud

1 1 13 5.908K Baud

SCP1 SCP0 Divisor Maximum Baud Rate

Prescaler Table (Crystal Frequency = 4.9152 MHz)

0 0 0 1 76.80K Baud 19.20K Baud

0 0 1 2 38.40K Baud 9600 Baud

0 1 0 4 19.20K Baud 4800 Baud

0 1 1 8 9600 Baud 2400 Baud

1 0 0 16 4800 Baud 1200 Baud

1 0 1 32 2400 Baud 600 Baud

1 1 0 64 1200 Baud 300 Baud

1 1 1 128 600 Baud 150 Baud

SCR1 SCR0 Divisor

Highest Baud Rate (from prescaler table)Crystal Frequency = 4.9152 Mhz

SCR2 76.80K Baud 19.20K Baud


RESET: 0 0 0 0 0 0 0 0

WRITE:

READ:

LOOPS ENSCI TXINV M WAKE ILTY PEN PTY SCC1

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ:

SCTIE TCIE SCRIE ILIE TE RE RWU SBK

SCC2

SCI Transmitter Configuration & Interrupts

• Transmitter Enable (TE)– Enables transmission operation – Sends preamble

1 = Enable transmitter0 = Disable transmitter

• SCI Transmit Interrupt Enable (SCTIE)– Interrupt on Transmit Data Register becoming empty– Next byte can be loaded into transmit data register

1 = Enable interrupt0 = Disable interrupt

• Transmission Complete Interrupt Enable (TCIE)– Interrupt on Transmit Complete– A byte has just been sent


• Parity Enable (PEN)1 = Enable0 = Disable

• Parity Type (PTY)1 = Odd Parity0 = Even Parity

• SCI Enable (ENSCI)– Enable SCI and SCI baud rate generator– Allows SCI to be disabled for lower power1 = SCI enabled0 = SCI disabled

• Character Length Select (M)1 = 9-bit SCI characters0 = 8-bit SCI characters


Character Length Selection

0 0 x 1 start + 8 (7) data + 1 (2) stop1 0 x 1 start + 9 (8) data + 1 (2) stop0 1 0 1 start + 7 data + Even +1 stop0 1 1 1 start + 7 data + Odd +1 stop1 1 0 1 start + 8 data + Even +1 stop1 1 1 1 start + 8 data + Odd +1 stop

M PEN PTY Character Length


Initialization Flow Diagram

Configure M, PEN, and PTY

Calculate baud

Enable SCI


RESET: 1 1 0 0 0 0 0 0

WRITE:

READ:

SCTE TC SCRF IDLE OR NF FE PE SCS1

RESET: UNAFFECTED BY RESET

WRITE: T7 T6 T5 T4 T3 T2 T1 T0

READ: R7 R6 R5 R4 R3 R2 R1 R0 SCDR

SCI Data Register (SCDR)• Buffers data for the transmit/receive shift registers• Writing to the SCDR writes data to be transmitted

– Initiates transmit operation

SCI Status Register 1 (SCS1)• SCI Transmitter Empty (SCTE)

– Indicates SCD register contents have been moved to transmit serial shift register– Cleared by reading SCS1 then writing to SCDR1 = Data register empty0 = Data register not empty

• Transmission Complete (TC)– Indicates SCDR is empty and no transmission in progress– Cleared by reading SCS1 and then writing to SCDR

1 = No transmission in progress0 = Transmission in progress

Transmitter Status Flags

SCI Data Register


Transmit Flow Diagram

Enable Transmitter

Load Transmit Byte

MoreData? SCTE?

TransmitComplete?

Disable Transmitter

NO

YES

YES

NO


Receiver, Start Bit Search

START BIT CONFIRMEDPOTENTIAL START BIT

POTENTIAL START BIT

POTENTIAL START BITS

START BIT ERROR

NOISE

SET NOISE FLAG

• RECEIVE SAMPLE CLOCK = 16 x BAUD RATE. • 3 SAMPLES ARE TAKEN FOR EACH START, STOP AND DATA BIT.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


DATA BIT SAMPLE

BIT LOGICAL VALUE IS THE VALUE OF 2 OUT OF THE 3 SAMPLES

IF ALL THREE SAMPLES DO NOT AGREE, THEN THE NOISE FLAG IS SET

PREVIOUS BIT

NEXT BIT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Receiver, Data Bit Detect


RESET: 0 0 0 0 0 0 0 0

WRITE:

READ: SCTIE TCIE SCRIE ILIE TE RE RWU SBK

SCC2

SCI Receiver Interrupts & Status

• Receiver Enable (RE)– Enables the receiver operation

1 = Enable receiver0 = Disable receiver

SCI Control Register 2 (SCC2)

• SCI Receive Interrupt enable (SCRIE)– Interrupt on Receive Data Register filling– Just received a transmitted byte


SCI Status Register 1

• SCI Receiver Full (SCRF)– Indicates data in the receive shift register transferred to SCI receive data register– Cleared by reading the SCS1 and then reading the SCD

1 = Receive data available0 = Data not available

RESET: 1 1 0 0 0 0 0 0

WRITE:

READ:

SCTE TC SCRF IDLE OR NF FE PE SCS1


SCI Data Register

SCI Data Register (SCDR)

• Buffers data for the transmit/receive shift registers

• Reading the SCDR accesses received data bits– Received data automatically placed here

RESET: UNAFFECTED BY RESET

WRITE: T7 T6 T5 T4 T3 T2 T1 T0

READ: R7 R6 R5 R4 R3 R2 R1 R0 SCDR


Receiver Flow Diagram

MoreBytes?

NO

YES

SCRF?

Empty Data Register

NO

YES Receiver must already be enabled

May want to enable/disable receiver

• Data reception must be synchronized


SC

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issi

on o

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I.

The

SC

I is

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ed to

a M

odem

ope

ratin

g at

240

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dat

a bi

ts, a

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ven.

C

ryst

al O

scill

ator

Fre

quen

cy =

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DR

reg

iste

r w

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, and

ret

urns

fro

m th

e in

terr

upt.

Su

gges

ted

prog

ram

ste

ps:

O

rigi

nate

SC

I T

rans

mit

Vec

tor

Add

ress

= $

FF

F2

Con

tent

s of

tran

smit

vec

tor

= A

ddr.

of

TR

AN

S S

ervi

ce R

outi

ne

Ori

gina

te S

CI

Rec

eive

Vec

tor

Add

ress

= $

FF

F4

Con

tent

s of

rec

eive

vec

tor

= A

ddr.

of

RC

VS

ervi

ce R

outi

ne

A

ddre

sses

for

: B

aud

Rat

e C

ontr

ol r

egis

ter

SC

I D

ata

(Rea

d=rc

v, W

rite

=xm

t)

SC

I C

ontr

ol 1

reg

iste

r

S

CI

Con

trol

2 r

egis

ter

SC

I S

tatu

s 1

regi

ster

Wri

te y

our

prog

ram

her

e:

ORG $FFF2

TRVEC FDB SCITRAN_IRQ

ORG $FFF4

RCVEC FDB SCIRECV_IRQ

SCBR EQU $19

SCDR EQU $18

SCC1 EQU $13

SCC2 EQU $14

SCS1 EQU $16

HC

08-S

CIE

xer

CO

NF

IGU

RA

TIO

N:

Sel

ect b

aud

rate

= 2

400:

1. L

oad

accu

mul

ator

wit

h "2

400

baud

val

ue".

2. S

tore

acc

umul

ator

to S

CB

R r

egis

ter.

Sel

ect w

ord

leng

th &

wak

eup

mod

e:

3.

Loa

d ac

cum

ulat

or w

ith

"8 d

ata

bit s

ize"

,

ena

ble

SC

I, n

o pa

rity

, no

wak

e-up

val

ue.

4. S

tore

acc

umul

ator

to S

CC

1 re

gist

er.

E

nabl

e tr

ansm

itte

r, r

ecei

ver

& in

terr

upts

:

5.

Loa

d ac

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ith

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a

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nd

T

CIE

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inte

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val

ue.

6. S

tore

acc

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to S

CC

2 re

gist

er.

7.

Don

e, s

tay

here

. (B

RA

SE

LF

)

SC

I R

EC

EIV

ER

SE

RV

ICE

:

9. L

oad

accu

mul

ator

wit

h S

CI

rece

ive

regi

ster

.

10. C

all R

ecei

ve D

ata

Rou

tine

.

11. R

etur

n fr

om I

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rupt

.

SC

I T

RA

NS

MIT

TE

R S

ER

VIC

E:

12

. Cal

l Tra

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it D

ata

Rou

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.

13. S

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acc

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to S

CI

tran

smit

reg

iste

r

14. R

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rupt

.


9 Data Bit Transmissions- Plus Start and Stop -


• M bit in SCC1 set

• R8 - Bit 8 ( Received )– Ninth bit of the received character

• T8 - Bit 8 ( Transmitted )– Ninth bit of the transmitted character

READ: R8

RESET: U U 0 0 0 0 0 0

WRITE:

T8 DMARE DMATE ORIE NEIE FEIE PEIESCC3


Sending Break Signal

SCI Control Register 2

• Send Break (SBK)

• Used to gain control of bus

1 = Transmit break character

0 = Do not transmit break characters

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ: SCTIE TCIE SCRIE ILIE TE RE RWU SBK SCC2


Additional Status Flags


• Receiver idle (IDLE) Receiver overrun (OR)

• Noise Flag (NF) Framing Error (FE)

• Parity Error (PE)

SCS1

RESET: 1 1 0 0 0 0 0 0

WRITE:

READ: SCTE TC SCRF IDLE OR NF FE PE

SCS2

RESET: 0 0 0 0 0 0 0 0

BKF RPF READ:

WRITE:


• Break (BKF)– Set when a break character is detected

• Cleared by reading SCS2 then reading SCDR

• Reception in Progress (RPF)– Set during start bit search – Reset after the stop bit or false start bit detected


Additional Information- Error Interrupt Enables -


• Overrun interrupt enable (ORIE)

• Noise error interrupt enable (NEIE)

• Framing error interrupt enable (FEIE)

• Parity error interrupt enable (PEIE)

READ: R8

RESET: U U 0 0 0 0 0 0

WRITE:



Additional Information- Idle Line Detection and Interrupt -

Idle Line Interrupt Enable (ILIE)

• Interrupts upon idle character being detected

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ: TIE TCIE RIE ILIE TE RE RWU SBK SCC2

Idle line type (ILTY)

• Selects when to start timing idle character

• After start or stop bit

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ: LOOPS ENSCI TXINV M WAKE ILTY PEN PTY SCC1


Additional Information- DMA Servicing -

DMA Receive Enable (DMARE)

• Enable DMA to service SCI receiver interrupts (SCRF)

• Disables CPU receiver interrupt

DMA Transmit Enable (DMATE)

• Enable DMA to service SCI transmit interrupts (SCTE)

• Disables CPU transmit interrupt

READ: R8

RESET: U U 0 0 0 0 0 0

WRITE:



Additional Information- Wake Up -

Receiver Wakeup Enable (RWU)

• Puts receiver in standby mode

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ: SCTIE TCIE SCRIE ILIE TE RE RWU SBK SCC2

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ: LOOP ENSCI SCIB M WAKE ILTY PEN PTY SCC1

Wakeup Method (WAKE)

• Selects wakeup criteria


Receiver Wake Up

Receiver selects wake up criteria

• Idle line (WAKE = 0)– Detection of idle character causes wake up

• Address mark (WAKE = 1)– Detection of most significant bit set causes wake up

• Most significant bit of first byte indicates an address• All remaining bytes have MSB set to logic zero


Wake Up Methods

TxD

RxD RxD RxD

SCI0 SCI1 SCI2

SCI

DATA DATA DATA DATA ADDRESS DATAIDLE LINE

ADDRESS DATA DATA DATA ADDRESS DATA DATA1 0 0 0 1 0

frame

frame

10 or 11 ONES

IDLE LINE WAKE UP:

ADDRESS MARK WAKE UP:

0b0 b8


Additional Information- Special Test Mode -

Loop mode operation (LOOPS)

• PTE1/RxD pin is disconnected from the SCI, and the transmitter output goes into the

receiver input.– Internal to SCI– Both transmitter and receiver must be enabled

Transmit Inversion Bit (TXINV)

• Polarity of Transmitted data is inverted

• Intended for external test and loop back

RESET: 0 0 0 0 0 0 0 0

WRITE:



- Low Power Modes -

WAIT

• SCI module remains active

• SCI registers are not accessible– Except to DMA

• SCI module interrupt can wake MCU

STOP

• SCI module is inactive

• Can not wake MCU


Register Summary

WRITE:


WRITE:

READ: SCP1 SCP0 SCR2 SCR1 SCR0SCBR

WRITE:

READ: SCTIE TCIE SCRIE ILIE TE RE RWU

SBKSCC2

SCS2 BKF RPF

WRITE:

SCS1WRITE:

READ: SCTE TC SCRF IDLE OR NF FE PE

READ: R8

WRITE:


SCDWRITE: T7 T6 T5 T4 T3 T2 T1 T0

READ: R7 R6 R5 R4 R3 R2 R1 R0

READ:


SC

I C

onfi

g &

Ser

vice

Rou

tin

e S

olu

tion

Wri

te a

rou

tine

that

con

figu

res

and

prov

ides

ser

vice

for

rec

eptio

n an

d tr

ansm

issi

on o

f th

e SC

I.

The

SC

I is

con

nect

ed to

a M

odem

ope

ratin

g at

240

0 ba

ud, 8

dat

a bi

ts, a

nd is

inte

rrup

t dri

ven.

C

ryst

al O

scill

ator

Fre

quen

cy =

4.9

152

MH

z. Y

our

rout

ine

calls

a R

ecei

ve o

r a

Tra

nsm

it ro

utin

e an

d ac

cess

es th

e SC

DR

reg

iste

r w

ith a

ccum

ulat

or A

, and

ret

urns

fro

m th

e in

terr

upt.

Sugg

este

d pr

ogra

m s

teps

: O

rigi

nate

SC

I T

rans

mit

Vec

tor

Add

ress

= $

FF

F2

Con

tent

s of

tran

smit

vec

tor

= A

ddr.

of

TR

AN

S S

ervi

ce R

outi

ne

Ori

gina

te S

CI

Rec

eive

Vec

tor

Add

ress

= $

FF

F4

Con

tent

s of

rec

eive

vec

tor

= A

ddr.

of

RC

VS

ervi

ce R

outi

ne

A

ddre

sses

for

: B

aud

Rat

e C

ontr

ol r

egis

ter

SC

I D

ata

(Rea

d=rc

v, W

rite

=xm

t)

SC

I C

ontr

ol 1

reg

iste

r

S

CI

Con

trol

2 r

egis

ter

SC

I S

tatu

s 1

regi

ster

Wri

te y

our

prog

ram

her

e:

ORG $FFF2

TRVEC FDB SCITRAN_IRQ

ORG $FFF4

RCVEC FDB SCIRECV_IRQ

SCBR EQU $19

SCDR EQU $18

SCC1 EQU $13

SCC2 EQU $14

SCS1 EQU $16

HC

08-S

CIS

ol

LDA #$05

STA SCBR

LDA #$40

STA SCC1

LDA #$AC

STA SCC2

SELF BRA SELF

SCIRECV_IRQ:

LDA SCDR

JSR RCVDAT

RTI

SCITRAN_IRQ:

JSR TXDAT

STA SCDR

RTI

CO

NF

IGU

RA

TIO

N:

Sel

ect b

aud

rate

= 2

400:

1. L

oad

accu

mul

ator

wit

h "2

400

baud

val

ue".

2. S

tore

acc

umul

ator

to S

CB

R r

egis

ter.

Sel

ect w

ord

leng

th &

wak

eup

mod

e:

3.

Loa

d ac

cum

ulat

or w

ith

"8 d

ata

bit s

ize"

,

ena

ble

SC

I, n

o pa

rity

, no

wak

e-up

val

ue.

4. S

tore

acc

umul

ator

to S

CC

1 re

gist

er.

Ena

ble

tran

smit

ter,

rec

eive

r &

inte

rrup

ts:

5. L

oad

accu

mul

ator

wit

h "r

cvr

& x

mtr

ena

bled

,

and

rcv

r &

xm

tr in

terr

upts

ena

bled

, and

TC

IE &

IL

IE in

terr

upts

dis

able

d" v

alue

.

6.

Sto

re a

ccum

ulat

or to

SC

C2

regi

ster

.

7. D

one,

sta

y he

re. (

BR

A S

EL

F)

SC

I R

EC

EIV

ER

SE

RV

ICE

:

9. L

oad

accu

mul

ator

wit

h S

CI

rece

ive

regi

ster

.

10. C

all R

ecei

ve D

ata

Rou

tine

.

11. R

etur

n fr

om I

nter

rupt

.

SC

I T

RA

NS

MIT

TE

R S

ER

VIC

E:

12. C

all T

rans

mit

Dat

a R

outi

ne.

13

. Sto

re a

ccum

ulat

or to

SC

I tr

ansm

it r

egis

ter

14. R

etur

n fr

om I

nter

rupt

.

Date post:	08-Jan-2016
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SERIAL COMMUNICATION INTERFACE (SCI)

Documents