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MODEL UP-700SRV Key : LKGIM7113RCZZPRINTER : PR-58HM(For "U & A" version)
CHAPTER 1. SPECIFICATIONS ................................................................1 - 1
CHAPTER 2. OPTIONS ..............................................................................2 - 1
CHAPTER 3. SERVICE PRECAUTION......................................................3 - 1
CHAPTER 4. SRV. RESET AND MASTER RESET ....................................... 4 - 1
CHAPTER 5. DIAGNOSTICS SPECIFICATIONS.......................................5 - 1
CHAPTER 6. CIRCUIT DESCRIPTION ......................................................6 - 1
CHAPTER 7. TCP/IP I/F PWB DESCRIPTION...........................................7 - 1
CHAPTER 8. CIRCUIT DIAGRAM..............................................................8 - 1
CHAPTER 9. PWB LAYOUT.......................................................................9 - 1
PARTS GUIDE
CONTENTS
Parts marked with " " are important for maintaining the safety of the set. Be sure to replace these parts with specifiedones for maintaining the safety and performance of the set.
SHARP CORPORATIONThis document has been published to be used for after sales service only.The contents are subject to change without notice.
SERVICE MANUAL
CHAPTER 1. SPECIFICATION
1. APPEARANCE
External view
2. RATING
External dimensions :With a drawer
445 (W) x 485 (D) x 312 (H) mm
Weight : With a drawer 16.4kg
Power source 120V AC 10%, 60Hz
Power consumption Stand-by : 16 WOperating : 57 W (max.)
Working temperatures 0 to 40 °C
3. KEYBOARD
1) STANDARD KEYBOARD LAYOUT
2) KEY TOP NAMEStandard key top
KEY TOP DESCRIPTION
0-9,00,000 Numeric keys
Decimal Point key
CL Clear key
@/FOR Multiplication key
RECEIPT Receipt paper feed key
JOURNAL Journal paper feed key
PAGE UP Page up key
PAGE DOWN Page down key
CANCEL Cancel key
Cursor keys
ENTER Enter key
RFND Refund Key
SERV# Server code entry key
RCPT Receipt print Key
TAX SHIFT Tax 1 shift key
VOID Void Key
PLU/SUB PLU/SUB dept./UPC code entry key
(D-PLU) 1 to 100 Direct PLU 1 to 100 keys
P.SHIFT# Price shift menu key
AUTO1, 2 Automatic sequencing 1 and 2 keys
MISC FUNC Miscellaneous function key
CONV# Currency conversion menu key
CHK# Check Menu Key
CH# Charge Menu Key
SBTL Subtotal Key
CA/AT Cash / amount tendered key
FINAL Tentative finalization key
LEVEL# PLU level shift menu key
SRVC Service key
GLU Guest Look-up key
Front view
Rear view
Receipt paper
Drawer lock
Drawer
Journal coverOperator display
Contrast control
Power switch
Mode switch
Keyboard
Customer display (Pop-up type)
Power switch
Rear cover
90
76
63
53
43
33
23
14
6
91
77
64
54
44
34
24
15
7
92
78
65
55
45
35
25
16
8
93
79
66
56
46
36
26
17
94
80
67
57
47
37
27
100
86
95
81
68
98
84
96
82
69
99
85
97
83
70MISCFUNC
TAXSHIFT
P-SHIFT#
ENTER
CANCEL
SBTL
GLU
FINAL
RCPT
SERV#
CONV#
PAGEUP
PAGEDOWN
PLU/SUB
AUTO2
CH#
AUTO1
00 0 000
1
4
7
CL
RECEIPT JOURNAL
VOID
@ FOR
RFND LEVEL#
CHK#
CA/AT
SRVC
87
73
60
50
40
30
20
11
3
88
74
61
51
41
31
21
12
4
89
75
62
52
42
32
22
13
5
71
58
48
38
28
18
9
1
72
59
49
39
29
19
10
2
2
5
8
4
6
9
*1
*1 Note:August Production:The [Auto 2] Key will be the [NC] Key.
Optional key top
KEY TOP DESCRIPTION
(D-PLU) 101 to 123 Direct PLU 101 to 123 Keys
(Dept) 1 to 99 Department 1 to 99 Keys
%1 to 5 Percent 1 to 5 keys
(-)1 to 5 Discount 1 to 5 keys
CH1 to 9 Charge 1 to 9 keys
CASH# Cash menu key
FUNC. MENU Function menu key
RP SEND Remote printer send key
GRT EX Gratuity exempt key
CA2 to 5 Cash 2 to 5 keys
CONV1 to 4 Conversion 1 to 4 keys
RA1 to 2 Received-on-Account 1 and 2 keys
PO1 to 2 Paid out key 1 and 2 keys
AUTO3 to 25 Automatic sequencing 3 and 25 keys
CHK1 to 5 Check 1 to 5 keys
P1 to 6 Price level shift 1 to 6 keys
LEVEL1 to 5 Menu level shift 1 to 5 keys
FS SHIFT Food stamp shift key
FS TEND Food stamp tender key
GD1 to 3 SHIFT Group discount shift 1 to 3 keys
CASH TIP Cash tip key
CHARGE TIP Charge tip key
TIP PAID Tip paid key
EAT IN1 to 3 Eat in 1 to 3 keys
TAX2 to 4 SHIFT Tax 2 to 4 shift keys
NS No sale key
SCALE Scale entry key
OPEN TARE Tare entry key
BAL Balance key
DEPOSIT Deposit key
DEPOSIT RF Deposit refund key
DEPT# Department number key
TAX Manual tax key
BACL SPACE Back space key
TRANS OUT Transfer out key
TRANS IN Transfer in key
RCP SW Receipt ON/OFF key
WASTE Waste mode key
BS Bill separation key
BT Bill totalize / bill transfer key (CHECK-ADD)
PRINT Validation print key
BILL Bill print key
PAST VOID Past void key
SBTL VOID Subtotal void key
KEY TOP DESCRIPTION
GDSC %1 to %3 Group discount %1 to 3 keys
COVER CNT Cover count key
N.C New check key
C_NEXT Condiments next key
EDIT TIP Edit tip key
RP ROUND Repeat round key
PLU MENU1 to 50 PLU menu 1 to 50 keys
MACRO1 to 4 Macro 1 to 4 keys
UPSIZE Upsize key
CAP.1 to 10 Data capture 1 to 10 keys
GLU RECALL Table # recall key
MSG1 to 5 Message 1 to 5 keys
MSG# Message menu key
DELETE Delete key
NEXT $ Next higher dollar key
MDSE SBTL Merchandise subtotal key
TRAY SBTL Tray subtotal key
RTN Return key
GAS SBTL Gasoline sales subtotal key
AMT Amount entry key
#/TM Non-add code / Date & Time display key
REPEAT Repeat key
IND. PAYMENT Individual payment key
INQ Inquiry key
CUST Customer code entry key
PRICE CHANGE UPC price change key
BIRTH Birthday entry key
TABLE # Table no. (seat no.) entry key
VOID MENU Void menu key
RFND SALE Refund sale key
>>>>> USE FONT <<<<<
Helvetica/ Helvetica-Condensed/ Century-Schoolbook/ Symbol & OriginalFonts: (RingWorld2/RingFont2/Pa
Symbol/PartsCod)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3) TEST PROGRAMMING KEY SHEET LAYOUT
: The shaded area contains the character keys which areused for programming characters.
KEY TOP DESCRIPTION
SHIFT Used for programming characters.Entering upper-case lettersYou can enter an upper-case letter by using thiskey. Press this key just before you enter theupper-case letter. You should press this key eachtime you enter an upper-case letter.
DC Used for programming characters.Entering double-size charactersThis key toggles the double-size character modeand the normal-size character mode. The defaultis the normal-size character mode. When thedouble-size character mode is selected, the letter"W" appears at the bottom of the display.
INS Used for programming characters.To select a text editing modeToggles between the insert mode ("_") and theoverwrite mode ("■").
DEL Used for programming characters.To delete a character or figureDeletes a character or figure in the cursor position.
BACK SPACE Used for programming characters.To delete a character or figureBacks up the cursor for deleting the character orfigure at the left of the cursor. When your POSterminal is in the insert mode, this key deletes thecharacter or the value at the cursor position.
Used to move the cursor.
ENTER Used to program each setting.
TL Used to finalize programming.
CANCEL Used to cancel programming and to get back tothe previous screen.
PREVRECORD
Used to go back to the previous record, e.g. fromthe department 2 programming window back tothe department 1 programming window.
NEXTRECORD
Used to go to the next record, for example, inorder to program unit prices for sequentialdepartments.
PAGE DOWN Used to scroll the window to go to the next page.
PAGE UP Used to scroll the window to go back to theprevious page.
CL Used to clear the last setting you haveprogrammed or clear the error state.
Used to toggle between two or more options.
SBTL Used to list those options which you can toggle bythe [ ] key.
RECALL Used to call up a desired code.
Numeric keys Used for entering figures.
4) BLANK KEY SHEET LAYOUT
3. DISPLAY
1) OPERATOR DISPLAY• Screen example 1 (REG mode)
Price level shift indicator(P1-P6)
: Shows the PLU/UPC price levelcurrently selected.
PLU level shift indicator(L1-L5)
: Shows the PLU level currently se-lected.
Receipt shift indicator (r) : Shows the receipt shift status.
Stock alarm indicator ( ! ) : Appears when the stock of the PLUwhich you entered is zero, negativeor reaches the minimum stock.
Electronic message indi-cator (M)
: Appears when an electronic mes-sage is received. (Status 1 area)
Receipt ON/OFF status in-dicator (R)
: Appears when the receipt ON-OFFfunction signs OFF.
Sentinel mark (X) : Appears in the lower right corner ofthe screen when the cash in drawerexceeds a programmed sentinelamount.The sentinel check is performed forthe total cash in drawer.
I (CANCEL)
(SHIFT)
(ENTER)
SBTL CA/AT
@ FOR
PAGEUP
PAGEDOWN
(INS) (DEL)
(RECALL)
(DC)
00 0
¥
1
4
7
G H J K L
E R T Y
_ - + { }
?
U /
# $ % ^ ) =
Z M
CL
(UPDATE)
000
RECEIPT JOURNAL
” < >
[ ]
! @
Q W
A S
C VX
FD
, .B N
; :O P
& (
Ñ
,¿
2
5
8
3
6
9
RECEIPT JOURNAL
Scroll guidance:
Server code
Mode name
Status area 1:
Time
Status area 2:
Numeric entry
When a transaction information occupies more than 5 lines, scrollkey(s) appears to indicate you canscroll to the direction.
Sales informationarea: Sales information you have just enteredsuch as items and prices will appearbetween 2nd line and6th line. Total is always appearat 7th line.
• Screen example 2 (PGM mode)
Screen save modeWhen you want to save the electric power or save the display’s life,use the screen save function. This function can turn the LCD off whena server does not operate the POS terminal for an extended period oftime. You can program the time for which your POS terminal shouldkeep the normal status (in which the backlight is "ON") before it goesinto the screen save mode.To go back to the normal mode, press any key.
Device type LCD display
Dot format 320(W) x 240(H) Full dot
Dot size 0.24 (W) x 0.21 (H) mm
Dot space 0.02 mm
Dot color White
Back color Dark blue
2) DISPLAY ADJUSTMENT (OPERATION DISPLAY)You can adjust the contrast of the display by using the contrastcontrol, and also you can adjust the display angle. Pull up the tab, thedisplay will head up.
The backlight in the display is a consumable part.When the LCD display may no longer be adjusted and becomesdarker, you should change the backlight.
3) CUSTOMER DISPLAY (Pop-up-type)
4. KEYS AND SWITCHES
1) MODE SWITCH AND MODE KEYS
The mode switch has these settings:
OFF: This mode locks all register operations.No change occurs to register data.
OP X/Z: This setting allows cashiers/clerks to take X or Z reports fortheir sales information. (This setting may be used onlywhen your register has been programmed for "OP X/Zmode available" in the PGM2 mode.)
REG: For entering sales
PGM1: To program those items that need to be changed often:e.g., unit prices of departments, PLUs or UPCs, and per-centages
PGM2: To program all PGM1 items and those items that do notrequire frequent changes: e.g., date, time, or a variety ofregister functions
MGR: For manager’s and submanager’s entriesThe manager can use this mode to make entries that arenot permitted to be made by cashiers/servers -for example,after-transaction voiding and override entry.
X1/Z1: To take the X/Z report for various daily totals
X2/Z2: To take the X/Z report for various periodic (weekly ormonthly) consolidation
2) DRAWER LOCK KEYThis key locks and unlocks the drawer. To lock it, turn 90 degreescounterclockwise. To unlock it, turn 90 degrees clockwise.
Programming iteminformation area
Programming area: Programmable itemsare listed.
Double-size character modeindicator (W):Appears when the double-sizecharacter mode isselected during text programming.
Caps lock indicator(A/a):
The upper-case letter “A” appears when caps lock is on,and the lower-case letter “a” appears when caps lock is offduring text programming.
Tab
Contrast controlTurning the control backwardsdarkens the display andturning it forwards lightens thedisplay.
REGOP X / Z MGR
X1/Z1
X2/Z2PGM1
PGM2
MA
SM
OFF
MA
SM
SR
V
• Manager key (MA) • Submanager key (SM)
• Service key (SRV)
OP
• Operator key (OP)
SK
1-2
4) PRINTER COVER LOCK KEYThis key locks and unlocks the printer cover. To lock it, turn 90degrees counterclockwise. To unlock, turn 90 degrees clockwise.
5. PRINTER
1) PRINTER (PR-58HA)
Item Description
No. of station 2: Receipt and Journal
Validation No
Printing system Line thermal
No. of dot Receipt: 360 dots
Journal 360 dots
Dot pitch Horizontal: 0.125 mm
Vertical: 0.125 mm
Font 10 dots (W) x 24 dots (H)
Printing capacity Receipt: Max. 30 characters
Journal: Max. 30 characters
Character size 1.25 mm (W) x 3.0 mm (H): At 10 x 24 dots
Print pitch Column distance: 1.5 mm
Row distance: 3.75 mm
Paper feed speed Approximate 65 mm/s
Reliability Mechanism: MCBF 5 milion lines
Paper end sensor Yes (Receipt and Journal)
Cutter Manual
Paper near end sensor No
Printing area
0.125 (7.0)
(7.0) (5.5)360dots(45)
57.5 ±0.5 5.0
(5.5)
UNIT: mm
106(848dots)
Item Description
Printing format 12 x 24 font
2) PAPER
Item DescriptionName Heat-quality paperRoll dimension 57.5 0.5 mm in widthThickness 0.06 mm to 0.08 mm
6. DRAWER
1) SPECIFICATION
(1) Drawer box and drawer
Model name SK-460Size 445 (W) x 464 (L) x 118 (H)Color GRAY 368Material MetalBell —Release lever Standard equipment; Front keyDrawer open sensor Standard equipment
2) MONEY CASE
U version A versionSeparation from the drawerAllowed
Allowed Allowed
Separation of the coincompartments from the money case
Disallowed Disallowed
Bill separator No Standard (1 pcs)Number of compartments 7B/5C 4B/8C
3) LOCK
Location of the lock Front
Method of locking and unlocking
Locking: Insert the drawer lock key intothe lock and turn it 90 degreescounterclockwise.
Unlocking: Insert the drawer lock key intothe lock and turn it 90 degreesclockwise.
Key No. SK1-2
1.5 (12dots) 1.5 (12dots)
0.1250.12
5
3.0
(24d
ots)
3.75
(30
dots
)3.
75 (
30do
ts)
UNIT: mm
Bill separator
A version : 4B/8CU version : 7B/5C
7. RS232 INTERFACE
This machine has two RS232 standard ports for communication to PC, Hand scanner (ER-A6HS1) and etc.
1) PORT 1 (CH1) (CN402)Connector type: D-SUB 9pinData rate: max. 38,400 bps
2) PORT2 (CH2) (CN403)Connector type: Modular jack RJ45 8pinData rate: max. 115,200 bps
3) OPTIONAL DEVICES THAT CAN BE CONNECTED
Standard port Option port (ER-A5RS)
Port No. Port1: CH1 Port2: CH2 Port3: Port4:
Type D-SUB 9pin Moduler RJ45 D-SUB 9pin D-SUB 9pin
CI/+5V selectable – – –
ER-A6HS1 (+5V necessary) – – –
Scanner (+5V not necessary)
Modem –
PC
Printer, Scale
POS utility, 02fd.exe – – –
The ER-A6HS1 cannot be connected to port 2, 3 or 4 because itrequires +5V.
The modem cannot be connected to port 2 because it uses adifferent signal line.
For the modular RJ45 to D-Sub 9pin conversion cable, see thefollowing.
1
2
3
4
5
6
7
8
9
/CD
RD
SD
/ER
GND
/DR
/RS
/CS
/CIVCC(+5V)
S401
1
2
3
4
5
6
7
8
/RS
/ER
SD
GND
RD
/DR
/CS
CICD
S404
S403
VCC(+5V)
GND
CD CI
S404
7
4
3
1
5
2
6
8
9
/RS
/ER
SD
/CD
GND
RD
/RS
/CS
/CI
1
2
3
4
5
6
7
8
/RS
/ER
SD
GND
RD
/DR
/CS
(Open)
Moduler RJ45 D-sub 9pin
VCC(+5V)
S403
GND
CH
AP
TE
R 2
. OP
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2. SALES OPTIONS
No. CLASSIFICATION COMPONENT NAME MODEL NAME REMARK
1 Memory Expansion RAM board UP-S02MB 2M bytes PS-RAM board
UP-S04MB 4M bytes PS-RAM board
2 Display Remote display (Pole type) UP-P16DP 11-Dig.7-Seg. + 16-Dig.Dot
3 Drawer Remote drawer ER-03DW 7B/5C coin case
ER-04DW 5B/5C coin case
4 On-line function RS232 I/F board ER-A5RS 2 ports RS232 I/F
5 Card reader MCR (Magnetic Card Reader) UP-E13MR ISO Type 1 : 3 stripe card
6 Scanner Bar code hand scanner ER-A6HS1
3. LOCAL PURCHASE OPTIONS
No. COMPONENT NAME MODEL NAME REMARK
1 External printer TM-T88/85, TM-88 (2), TM-T80TM-U200, TM-300
2 Slip printer TM-295
3 Scale I/F
4 Coin dispenser
5 Color kitchen monitor
6 CAT terminal
1: Please consult with your Sharp regional sales manager.
4. SERVICE OPTIONS
No. NAME PARTS CODE PRICE DESCRIPTION
1 Mode key grip cover AX For MA key only
2 Drip proof mode switch cover BA
5. SERVICE TOOLS
No. NAME PARTS CODE PRICE DESCRIPTION
1 Service key AF
2 RS232 Loop Back Connector BC For RS232 D-SUB 9pin connector
3 RS232 modular Loop Back Connector BC For RS232 RJ45 Modular jack connector
4 Expansion PWB for option board BU For ER-A5RS
5 MCR test card BL For UP-E13MR
6. SUPPLIES
No. NAME PARTS CODE PRICE DESCRIPTION
1 Thermal roll paper BA 5 Rolls / pack
2 Thermal roll paper (High preservative type) BD 5 Rolls / pack
3 Key sheet (Normal key layout) AR
4 Key sheet (Character key layout) AH
5 Key sheet (Blank key layout) AG
>>>>> USE FONT <<<<<
Helvetica/ Helvetica-Condensed/ Century-Schoolbook/ Symbol & OriginalFonts: (RingWorld2/RingFont2/Pa
Symbol/PartsCod)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7. HOW TO USE SERVICE TOOLS
1) EXPANSION PWB : CKOG-6708RCZZ• External view
Purpose 1 : Used for servicing and repairing of options (such as theER-A5RS) which are connected with the main body op-tion connector.
[Procedure 1]Use an insulator base as shown in the shaded section when perform-ing servicing.
To check the option I/F PWB from the solder side, connect the I/FPWB to OPTCN2. To check from the parts side, connect to OPTCN3.
(Note) The option I/F PWB should be held horizontally so that noexcessive stress is applied to connecting section .
[Procedure 2]
Put a string between the pop up and the option PWB. Adjust thelength of the string so that the CKOG-6708RCZZ and the option PWBare not binding. Once verified, then you may proceed with performingservice.
2) MCR TEST CARD : UKOG-2357RCZZ• Used when executing the diagnostics of the UP-E13MR.
• External view
UP-700
Main PWB
Expansion PWB(CKOG-6708RCZZ)
ER-A5RSPWB
Loop back connectorsUKOG-6705RCZZ
BaseA
UP-700
Main PWB
Expansion PWB(CKOG-6708RCZZ)
ER-A5RSPWB
Control ROM
Pop up
String
Loop back connectorsUKOG-6705RCZZ
CHAPTER 3. SERVICE PRECAUTION
1. IPL (Initial Program Loading) FUNCTION
1) INTRODUCTIONThe application software of the UP-700 is written in the flash ROM.In the following cases, writing of the application software into the flashROM is required.
• When the flash ROM is replaced with a new one. The service partflash ROM does not include the application software in it.
• When IPL writing is required because of a change in the software.
The service part of the main PWB unit includes the flash ROM withthe application software written in it, and there is no need forwriting the application software when replacing the main PWB unit.
2) IPL PROCEDUREThere are two ways for the IPL procedures.
• IPL from P-ROM
• IPL from PC communication (Please refer to the next section)
The detailed descriptions on the above procedures are given below.
3) IPL FROM P-ROMMaster ROM-1 : VHI27801RAU1AMaster ROM-2 : VHI27801RAV1A
Before installation, turn off the power switch on the UP-700 and un-plug the AC cord from the AC outlet.
1. Insert a screwdriver into the slit on the right side of the lowercabinet to remove the option RAM case.
2. IPL switch (SW301) on the IPL ROM PWB: Set the IPL switch(SW301) to ON position.
3. Install the ROMs into the IC sockets on the IPL ROM PWB asshown below.
4. Place the mode key to any position except OFF or SRV’.
5. Turn on the power switch of the UP-700.
6. The following display is shown and the IPL procedure is started.When the procedure is completed, the message of "Completed"is shown.
7. Turn off the power switch of UP-700.
8. Remove the ROMs IC sockets on the IPL ROM PWB.
9. IPL switch (SW301) on the IPL ROM PWB: Set the IPL switch(SW301) to the OFF position.
10. Perform one of the master reset procedures.
ROM1 ROM2
ROM1 ROM2
on off
SW301
IPL from PROM
Version check…
Erase …
IPL write start
26 27 28 29 2A 2B
2C 2D 2E 2F 30 31
38 39 3A 3B 3C 3D
3E 3F
Verify … IPL write completed
32 33 34 35 36 37
Completed.
2. UP-700 UTILITY TOOLS
1) OUTLINEThis Specification document describes the explanation about "POSU-TILITYTOOL.EXE and "02FD.EXE".
"POSUTILITYTOOL.EXE"and "02FD.EXE" works on Windows 95/98of PC and they have the followingFunctions by connecting UP-700 with RS232.
POSUTILITYTOOL.EXE : IPL of UP-700 Program Object
02FD.EXE : All RAM Data Upload/Download(PC software tool instead of the cur-rent ER-02FD.)
2) CONNECTIONPC and UP-700 are connected by RS232.
Connect the CH2 port of the UP-700 to the RS-232 interface of thePC.
RS232 Cable Connecting:
3) PROCEDURE
3) -1. POS UTILITY TOOL
No Procedure on P.C. side No Procedure on UP-700 side
1 Install "POSUTILITYTOOL.EXE" on the P.C.
2 Turn OFF the power.
3 Select "IPL Mode".Set the "IPL Switch" (SW302) of the UP-700 to "ON".
4 Turn ON the power.
5 Starting of "IPL Mode".The UP-700 displays."IPL from Serial I/O"
6 Connect the P.C. and the UP-700 (CH2) via RS232. (Fig 1)
UP-700:CH2PC
D-SUB 9pin - D-SUB 9pincable
D-SUB 9pin - modular RJ-45conversion cable
(Open)
CDD-sub 9pin
1
2
34
5
6
7
89
/CD
RD
SD/ER
GND
/DR
/RS
/CS/CI
RD
SD/ER
GND
/DR
/RS
/CS
12345678
1
2
34
5
6
7
89
1
2
34
5
6
7
89
RD
SD
GND
CI
GND
S404
VCC(+5V)
[UP-700]Moduler RJ45
[PC]D-sub 9pin
S403
on off
SW302
on off
IPL from Serial I/O
>>>>> USE FONT <<<<<
Helvetica/ Helvetica-Condensed/ Century-Schoolbook/ Symbol & OriginalFonts: (RingWorld2/RingFont2/Pa
Symbol/PartsCod)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
No Procedure on P.C. side No Procedure on UP-700 side
7 Execute the "POSUTILITUTOOL.EXE" on the P.C.*Please close all other applications while using this utility.
8 Select the ROM object Files by clicking the "Add Files.." button.
9 Push the "SEND" button.Program data is sent to the UP-700 automatically.
9Program data is received from P.C. automatically.The UP-700 display.
10 When data sending is completed,the initial Window is shown after "Complete" window.
10The UP-700 displays"Completed."
11 Turn OFF the power.
12Select "Normal Mode".Set the "IPL switch" to "OFF".(Ref. Hardware manual)
13 Execute the "Service Reset" on UP-700.
IPL from serial I/OConnected IRDA 11520021 22 23 24 25 26 27 28
IPL from Serial I/OConnected IRDA 11520021 22 23 24 25 26 27 2829 2A 2B 2C 2D 2E 2FCompleted.
IPL from Serial I/OConnected IRDA 11520030 31 32 33 34 35 36 3738 39 3A 3B 3C 3D 3E 3FCompleted.
3) -2. 02FD
No Procedure on P.C. side No Procedure on UP-700 side
1 Install the "02FD.EXE" on the P.C.ALL RAM Data UpLoad : Go to "2"ALL RAM Data DownLoad : Go to "9"
2 ALL RAM Data UpLoadConnect the P.C. and the UP-700 (CH2) via RS232. (Fig 1)
2 Enter the SRV mode.Select " 2 SETTING ".Select " 14 BACKUP SEND"
3 displays
4 Execute the "02FD.EXE" on the P.C.*Please close all other apprications while using this utility.
5 Set the Communication method by pushing the "Setting" Button.
Push the "OK" Button.
6 Push the "Receive Start" Button.And Select the Receiving File.
7 Communication starts. 7 Push CA/AT key. The UP-700 displays
8 The UpLoad is completed.The initial Window is shown.Push the "Exit" Button.
8 The UpLoad is completed.The SETTING menu is shown.
9 ALL RAM Data UpLoadConnect the P.C. and the UP-700 (CH2) via RS232. (Fig 1)
9 Enter the SRV mode.Select " 2 SETTING".Select " 15 BACKUP RECEIVE"
10 The UP-700 shows
Push the CA/AT key.
SEND DATA ALL RAM
SPEED PROGRAMMED SPEED
BACKUP SEND
SENDING 00000
BACKUP RECEIVE
SPEED PROGRAMMED SPEED
No Procedure on P.C. side No Procedure on UP-700 side
11 Execute the "02FD.EXE" on the P.C.*Please close all other apprications while using this utility.
12 Set the Communication method by pushing the "Setting" Button.
Push the "OK" Button.
13 Push the "Transmit Start" Button.And Select the Sending File.
14 Communication starts. 14 The UP-700 displays
15 The DownLoad is completed.The initial Window is shown.Push the "Exit" Button.
15 DownLoad is completed.The SETTING menu is shown.
16 Execute the " Service Reset " on the UP-700
3. NOTE FOR HANDLING OF LCD
• The LCD elements are made of glass. Use extreme care whenhandling the LCD.Any strong shock applied to the LCD can cause damage.
• If the LCD element is broken and the liquid has leaked, do notcome in contact with it. If the liquid is attached to your skin or cloth,immediately clean with soap.
• Use the unit under the rated conditions to prevent against damage.
• Be careful not to drop water or other liquids on the display surface.
• The reflection plate and the polarizing plate are easily scratched.Be careful not to touch them with hard objects such as glass,tweezers etc. Never hit, push, or rub the surface with hard objects.
• When installing the unit, be careful not to apply stress to the LCDmodule. If excessive stress is applied, abnormal display or unevencolor may result.
RECEIVING 00000
CHAPTER 4. SRV. RESET AND MASTER RESET
The SRV key is used for operating in the SRV mode.
1. SRV. RESET (Program Loop Reset)
Procedure• Method 1
1) Turn off the AC switch.
2) Set the mode switch to (SRV’) position.
3) Turn on the AC switch.
4) Turn to (SRV) position from (SRV’) position.
• Method 2
1) Set the mode switch to PGM2 position.
2) Turn off the AC switch.
3) While holding down the JOURNAL FEED key and RECEIPTFEED keys, turn on the AC switch.
Note: When disassembling and reassembling always power up us-ing method 1 only. Method 2 will not reset the CKDC9.
Note: SRV programming job#926-B must be set to a "4" to allow thePGM program loop reset.
PRG. RESET
2. MASTER RESET (All memory clear)
There are three possible methods to perform a master reset.
MRS-1 (Master resetting 1)Used to clear all memory contents and return the machine back to itsinitial settings.
Return the keyboard back to the default layout.
Procedure1) Turn off the AC switch.
2) Set the MODE switch to the (SRV’) position.
3) Turn on the AC switch.
4) While holding down the JOURNAL FEED key, turn to the(SRV) position from the (SRV’) position.
MRS-2 (Master resetting 2)Used to clear all memory and keyboard contents.
This reset returns all programming back to defaults. The keyboardmust be entered by hand.
This reset is used if an application needs a different keyboard layoutother than that supplied by a normal MRS-1.
Procedure1) Turn off the AC switch.
2) Set the MODE switch to the (SRV’) position.
3) Turn on the AC switch.
4) While holding down the JOURNAL FEED and RECEIPT FEEDkeys, turn to the (SRV) position from the (SRV’) position.
5) Key position assignment:
After the execution of a MRS-2, only the RECEIPT FEED andJOURNAL FEED keys can remain effective on key assignment.Any key can be assigned on any key position on the main key-board.
[key setup procedure]
MASTER RESETNOTES:
*1: When the 0 key is pressed, the key of the key number on thedisplay is disabled.
*2: Push the key on the position to be assigned. With this, the key ofthe key number on the display is assigned to that key position.
*3: When relocating the keyboard, the PGM 1/2 modes use thestandard key layout.
KeyNo.
Keyname
KeyNo.
Keyname
KeyNo.
Keyname
001 011 021
002 012 022
003 013 023
004 014
005 015
006 016
007 017
008 018
009 019
010 020
MRS-2 executed Key position set Free key
Disable
Free key setupcomplete.
*2
*1
0
0
MRS-3 (Master resetting 3)Master resetting 3 requires the entry of Serial No. data in addition toMaster resetting 2.
After completion of the MRS-3, the following operations and program-ming will be inhibited.
1. GT programming.
2. All memory download via RS-232.
3. GT resets with Z report. (Z report can be made, but the GT will notbe reset.)
Procedure1) Turn off the AC switch.
2) Set the reset switch to the "SRV" position.
3) Turn on the AC switch.
4) While holding down the JOURNAL FEED key and MRS-3 key,turn to the (SRV) position from the (SRV’) position.
MRS-3 key : UP-700=[PLU72] key
5) The product serial No. input window is displayed as shownbelow.
DISPLAY:
Enter the product serial No. of this POS and enter the [CA/AT]key.
6) Key position assignment:
After the execution of MRS-2, only the RECEIPT FEED andJOURNAL FEED keys can remain effective on key assignment.Any key can be assigned on any key position on the main key-board.
[key setup procedure]
MASTER RESETNOTES:
*1: When the 0 key is pressed, the key of the key number on thedisplay is disabled.
*2: Push the key on the position to be assigned. With this, the key ofthe key number the on display is assigned to that key position.
*3: When relocating the keyboard, the PGM 1/2 modes use thestandard key layout.
KeyNo.
Keyname
KeyNo.
Keyname
KeyNo.
Keyname
001 011 021
002 012 022
003 013 023
004 014
005 015
006 016
007 017
008 018
009 019
010 020
SERIAL No. 00000000
MRS-2 executed Key position set Free key
Disable
Free key setupcomplete.
*2
*1
0
0
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CHAPTER 5. DIAGNOSTICS SPECIFICATIONS
1. GENERAL DESCRIPTION
This Diag Program consists of a number of Diag. programs for theUP-700, which facilitate the PWB check, process check and the op-eration check of the system during servicing.
The Service Diag. programs are all contained in the standard ROM.
2. SYSTEM COMPOSITION
UP-700 only
3. DIAG.
Starting the Diag. ProgramThe Diag. Program is written on the external ROM, which is executedby the CPU (H8/510) and runs under the following conditions:
The logic power supply is normal.(+5V, VCKDC, POFF, +24V)
Both the I/O pins of the CPU and the CPU internal logic arenormal, and the CKDC9 and MPCA9, system bus, and standardROM/RAM are normal.
1) EXECUTING DIAG PROGRAMTo start the Diag. Program, enter the SRV mode. Select the optionitem DIAGNOSTICS from the MENU using the cursor keys and pressthe ENTER key.
The DIAG. MAIN MENU appears on the screen as shown below. Thecursor is displayed in reverse video and can be moved using theup/down arrow keys. Move the cursor to the menu item you want andpress the ENTER key to execute the corresponding Diag. program.When each Diag. program is completed, the screen returns to theDIAG. MAIN MENU. Press the CANCEL key to exit the Diag. Pro-gram and the screen returns to the SRV mode menu screen.
2) RAM & ROM & SSP DIAGNOSITCSThis program tests the standard RAM, expanded RAM, standard andservice ROMs, and SSp circuit. RAM&ROM&SSP is selected on theMAIN MENU, the following sub-menu screen appears. The cursorshown in reverse video can be moved using the up/down arrow keys.Move the cursor to the menu item you want and press the ENTERkey to execute the corresponding program. Press the CANCEL key toreturn the screen to this submenu.
2)-1. Standard RAM checkChecking
The program performs the following checks on the standard512KB of RAM. Data in memory remains unchanged before andafter the checks.
The following operations are performed for the memory addressesto be checked (780000H - 7FFFFFH).
PASS1 : Save data in memory
PASS2 : Write data "0000H"
PASS3 : Read and compare data "0000H" and write data "5555H".
PASS4 : Read and compare data "5555H" and write data "AAAAH"
PASS5 : Read and compare data "AAAAH"
PASS6 : Return data into memory
If any comparison is not normal during the check sequence fromPASS 1 through 6, the error message appears.
If any error is not found up to the final address, the sequenceends normally.
Then, another round of address checks is carried out using theabove check sequence
If an error occurs, the error message appears and the checkstops. The read/write of the address where the error occurs isrepeated.
Check point address = 780000H, 780001H780002H, 780004H780008H, 780010H780020H, 780040H780080H, 780100H780200H, 780400H780800H, 781000H782000H, 784000H788000H, 790000H7A0000H, 7C0000H
UP-700
Fig 2-1. Service
UP-700 DIAG V1.0A
PRODUCT&TESTRAM&ROM&SSP
CLOCK&KEY&SWITCH
SERIAL I/O
DISPLAY&PRINTER
MCR&DRAWER
TCP/IP
SSP Check
Service ROM Check
Standard ROM Check
UP-S02MB Check
UP-S04MB Check
Standard RAM Check
RAM&ROM&SSP DIAG
Display
The capacity checked is displayed in units of 64KB.
The error address and bit are displayed only when an error occurs(They are not displayed if there is no error.)
How to exit the program
You can exit the program by pressing the CANCEL key after theresults are displayed.
2)-2. UP-S02MB CheckChecking
The program checks for the presence of the UP-S02MB in thefollowing procedure.
Data in memory remains unchanged before and after checking.
i. Write 55AAH in 9FFFFEH.
ii. Read 9FFFFEH and compare the data with 55AAH.If both dataare correct and BFFFFEH is the same as 55AAH, perform thefollowing tests are performed. If not correct, the message"0KB: ERROR!!" appears and checking ends.
The following checks are performed on the UP-S02MB.
The following operations are performed for the address space tobe checked (800000H - 9FFFFFH).
PASS1 : Save data in memory.
PASS2 : Write data "0000H".
PASS3 : Read and compare data "0000H" and write data "5555H".
PASS4 : Read and compare data "5555H" and write data "AAAAH".
PASS5 : Read and compare data "AAAAH".
PASS6 : Return data into memory.
If any comparison is not normal during the check sequence fromPASS 1 through 6, the error message appears.
If any error is not found up to the final address, the sequenceends normally.
Then, another round of address checks is carried out using theabove check sequence.
If an error occurs, the error message appears and the checkingstops. The read/write of the address where the error occurs isrepeated.
Check point address = 800000H, 800001H800002H, 800004H800008H, 800010H800020H, 800040H800080H, 800100H800200H, 800400H800800H, 801000H802000H, 804000H808000H, 810000H820000H, 840000H880000H, 900000H
Display
The capacity checked is displayed in units of 64KB.
The error address and bit are displayed only when an error occurs(They are not displayed if there is no error.)
How to exit the program
You can exit the program by pressing the CANCEL key after theresults are displayed.
2)-3. UP-S04MB CheckChecking
The program checks for the presence of the UP-S04MB in thefollowing procedure. Data in memory remains unchanged beforeand after checking.
i. After writing 55AAH in BFFFFEH, write AA55H in 9FFFFEH.
ii. Read BFFFFEH and compare the data with 55AAH. Data inBFFFEH is correct, the following checks are performed. Dataread is AA55H, the message "UP-S02MB!!" appears and thecheck ends. If the data read is not either 55AAH or AA55H, themessage "0KB:ERROR!!" appears and the check ends.
The following checks are performed on the UP-S04MB.
The following operations are performed for the address space tobe checked (800000H - BFFFFFH).
PASS1 : Save data in memory.
PASS2 : Write data "0000H".
PASS3 : Read and compare data "0000H" and write data "5555H".
PASS4 : Read and compare data "5555H" and write data "AAAAH".
PASS5 : Read and compare data "AAAAH".
PASS6 : Return data into memory.
If any comparison is not normal during the check sequence fromPASS 1 through 6, the error message appears.
If any error is not found up to the final address, the sequenceends normally.
Then, another round of address checks is carried out in the abovecheck sequence.
If an error occurs, the error message appears and the checkingstops. The read/write of the address where the error occurs isrepeated.
Check point address = 800000H, 800001H800002H, 800004H800008H, 800010H800020H, 800040H800080H, 800100H800200H, 800400H800800H, 801000H802000H, 804000H808000H, 810000H820000H, 840000H880000H, 900000HA00000H
Read:XXXXH
Write:XXXXH
Error:XXXXXXH
512KB:PASS!!(or ERROR!!)
Standard RAM Check
Read:XXXXH
Write:XXXXH
Error:XXXXXXH
2048KB:PASS!!(or ERROR!!)
UP-S02MB Check
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Display
The capacity checked is displayed in units of 64KB.
The error address and bit are displayed only when an error occurs(They are not displayed if there is no error.)
How to exit the program
You can exit the program by pressing the CANCEL key after theresults are displayed.
2)-4. Standard ROM CheckChecking
The standard ROM area (200000H - 3FFFFFH) is added in unitsof bytes. When the lowest 2 digits of the result is 20H, it is re-garded as normal.
In addition, the ROM version and model name code stored in theaddresses 31FFE0H - 31FFFFH where the ROM version andchecksum correction data are stored are displayed. Data (ASCII)is stored in the following formats:
31FFE0H~31FFEFH : Model name CODE (Example: "UP-600",to be displayed until DATA becomes 00H.)
31FFF0H~31FFF9H : 27801R****(****=PROGRAM VERSION)
31FFFAH~31FFFBH : BLOCK NO.("20"~"3F")
31FFFCH : TERMINATOR ("=")
31FFFDH~31FFFEH : BLOCK VERSION (Example: "00")
31FFFFH : CHECK SUM correction DATA
FLASH ROM used as the standard ROM has 64K-byte-unit re-write BLOCKs. To perform VERSION management in the BLOCKunit, these BLOCKs have the same 16 byte organization as thoseafter the previous 31FFF0H and arranged every 64KBYTE. At thistime, the checksum for each BLOCK is corrected to be 01H sothat the entire 2MBYTE become a total of 20H.
Regarding the display of the PROGRAM VERSION, the FLASHwrite MASTER EPROM has 2-chip 8Mbits to allow managementof the block units of the chip. The PROGRAM VERSION stored inblocks at 21H and 31H are displayed.
0 PAGE (BLOCK) where the IPL is stored, displays the PRO-GRAM VERSION of the IPL to make it possible to manage individ-ual programs.
Display
The capacity checked is displayed in units of 64KB.
JOURNAL print
How to exit the program
You can exit the program by pressing the CANCEL key after theresult of checking is displayed.
2)-5. SERVICE ROM CheckChecking
The SERVICE ROM area composed of two EPROMs (D00000H -EFFFFFH) is added in units of bytes for each chip. If the lowest 2digits are 10H, it is regarded as normal.
In addition, the ROM version and model name code stored in theaddresses D1FFE0H - D1FFFFH where the ROM version andchecksum correction data are stored are displayed. Data (ASCII)is stored in the following formats:
D1FFE0H~D1FFEFH : Model name CODE(Example: "UP-600",to be displayed until data is 00H.)
D1FFF0H~D1FFF9H : 27801R****(****=PROGRAM VERSION)
D1FFFAH~D1FFFBH : BLOCK NO.("20"~"2F")
D1FFFCH : TERMINATOR("=")
D1FFFDH~D1FFFEH : BLOCK VERSION(Example:"00")
D1FFFFH : CHECK SUM correction DATA
This SERVICE ROM is used to write data into FLASH ROM and ifany error occurs during rewriting of the FLASH ROM, and it is notpossible to resume the operation. Its configuration is the same asthe standard ROM.
0 PAGE (BLOCK) where the IPL is stored displays the PRO-GRAM VERSION of the IPL to make it possible to manage individ-ual programs.
Display
The capacity checked is displayed in units of 64KB.
JOURNAL print
How to exit the program
You can exit the program by pressing the CANCEL key after theresult of checking is displayed.
Read:XXXXH
Write:XXXXH
Error:XXXXXXH
4096KB:PASS!!(or ERROR!!)
UP-S04MB Check
IPL:**
27801R****
APL: 27801R****
PASS!!(or ERROR!!)
Service ROM Check
3C=** 3D=** 3E=** 3F=**
. . . . . . . . . . .24=** 25=** 26=** 27=**
20=** 21=** 22=** 23=**
BLOCK Version.
IPL:**
27801R****
APL: 27801R****
ROM2:PASS!!(or ERROR!!)
ROM1:PASS!!(or ERROR!!)
Service ROM Check
3C=** 3D=** 3E=** 3F=**
. . . . . . . . . . .24=** 25=** 26=** 27=**
20=** 21=** 22=** 23=**
BLOCK Version.
2)-6. SSP CheckChecking
When started, this check program automatically sets the test SSP,performs SSP check and displays the check result.
The SSP check sets check data in the empty space in the SSPentry register. After checking is completed, only the check data iserased. Any setting remains intact before and after this checkprogram is executed.
Display
How to exit the program
You can exit the program by pressing the CANCEL key after theresults are displayed.
3) TIMER & KEYBOARD & CLERK SWITCHDIAGNOSTICS
This program checks the operation of the CKDC’s clock crystal, key-board and tests the clerk switch and mode switch.
You can return to the Diag menu screen by pressing the CANCELkey.
3)-1. Timer CheckChecking
Check the operation of the CKDC9’s clock crystal.
The area showing "YY/MM/DD & MM:HH" is continuously dis-played. Check whether the display blinks in black and white every0.5 seconds and the time shown is updated.
3)-2. Keyboard CheckChecking
The program check the input through the keyboard of the UP-700.
A 3-digit position code corresponding to a key pressed appears onscreen, along with a catch sound.
3)-3. Clerk SW Check (not for U version)Checking
The code of the key inserted into the clerk key switch appears in adecimal number.
3)-4. Mode Switch CheckChecking
The mode switch position code is displayed in a hexadecimalnumber.SRV:0, PGM2:1, PGM1:2, OFF:E, OP X/Z:3, REG:4, MGR:5,X1/Z1:6, X2/Z2:7
Intermediate code:E, Multiple error F
4) RS232 I/F DIAGNOSTICSThe program tests the RS232 interface for the main PWB and theoptional board ER-A5RS. Attach a 9-pin D-sub loop back connector(UKOG-6717RCZZ) wired as shown in Fig. 3-11, to the port you aregoing to test.
Fig. 3-11. Wiring diagram of loop back connector (UKOG-6717RCZZ)
The following menu appears on the screen. The cursor shown inreverse video can be moved using the up/down arrow keys. Move thecursor to the menu item you want to execute and select by pressingthe Enter key to the corresponding Diag. Program. Press the CAN-CEL key to return the screen to this submenu.
When setting the channel for the RS232 interface, do not set morethan two ports to the same channel. The UP-700 accommodates upto one ER-A5RS board, but use caution not to allow each port tohave the same channel; otherwise the hardware might be destroyed.
When Diag. is started, the channel check is performed and only thechannels already set appear on screen.
Note: The channel numbers displayed are logical numbers on soft-ware, In practical terms, CH1 means the CH1 of the rear con-nector of the POS and CH8 means the CH2 of the rear con-nector of the POS. If options are installed, only the ones (CH2- CH7) which have been set will be added and displayed.
4)-1. CHANNEL CheckChecking
The screen shows only the channels for which have been set andare connected to the ECR. Compare the channels shown on thescreen and the settings of the channel setting DIP SW of theRS232 interface board.
The RS232 on the main PWB of the UP-700 is fixed to CH1 andCH8. It is therefore necessary for the ER-A5RS to set the channelto any of CH2 - CH7.
(Ref) ER-A5RS channel settings ("1" = SW OFF, "0" = SW ON)
PASS!!(or ERROR!!)
SSP Check
CLERK CODE=***
KEY CODE=***
YY/MM/DD&HH:MM:SS
Timer&Key&Clerk DIAG
MODE SWITCH=* (0~7,E:Intermediate position, F:Multiple ERROR)
1pinCD
2pinRD
3pinSD
4pinER
5pinGND6pinDR
7pinRS
8pinCS
9pinCI
CH8 Check
CH1 Check
RS232 I/F DIAG
ER-A5RS CON3 (RSCN1)
S1-1 S1-2 S1-3 CHANNEL
0 0 0 Disabled
0 0 1 No setting allowed (Standard RS)
0 1 0 CHANNEL 2
0 1 1 CHANNEL 3
1 0 0 CHANNEL 4
1 0 1 CHANNEL 5
1 1 0 CHANNEL 6
1 1 1 CHANNEL 7
ER-A5RS CON4 (RSCN2)
S1-4 S1-5 S1-6 CHANNEL
0 0 0 Disabled
0 0 1 No setting is allowed (Standard RS)
0 1 0 CHANNEL 2
0 1 1 CHANNEL 3
1 0 0 CHANNEL 4
1 0 1 CHANNEL 5
1 1 0 CHANNEL 6
1 1 1 CHANNEL 7
How to exit the program
Press the CANCEL key to exit the program.
4)-2. CH1 CheckChecking
If any channel is not set, the error message (ERROR: CHx) ap-pears. When the channel is set, the following checks are per-formed.
i. Control signal check
ERn RSn DRn Cin CDn CSn
OFF OFF OFF OFF OFF OFF
OFF ON OFF OFF ON ON
ON OFF ON ON OFF OFF
ON ON ON ON ON ON
The program performs the read checks of the above inputs andinterrupt checks of CS, CI, and CD.
During the read check, ER and RS are changed over in the aboveorder, checking the logic of DR, CI, CD and CS.
If the check result does not agree with the logic in the table, theerror message appears. "ON" in the table means active low and"OFF" means active high.
In the interrupt check, the CS, CI and CD interrupts are permittedone by one (The mask is canceled.).
The error message appears if an interrupt does not occur wheneach signal is active or if an interrupt occurs when each signal isnot active.
Four cycles of the above check is performed.
ii. Data transfer check
As check data, loop back data transfer of 256 bytes of 00H - 0FFHis performed. The baud rate is 38400 bps.
iii. TIMER CHECK (RS232 ON BOARD TIMER)
Before starting the check ii, perform the RCVDT start of the timeryou want to check and set to 5 ms. Make sure::
• No TRQ- is generated during the implementation of check ii.
• TRQ- is generated at 5 ms after check ii is completed.
Display
Details of the errors are printed on the journal.
ERRORNo.
ERROR print Details of ERROR
1 ER-DR : ERROR ER-DR LOOP ERROR
2 ER-CI : ERROR ER-CI LOOP ERROR
3 RS-CD : ERROR RS-CD LOOP ERROR
4 RS-CS : ERROR RS-CS LOOP ERROR
5 CI INT : ERROR No CI interrupt occurs.
6 CD INT : ERROR No CD interrupt occurs.
7 CS INT : ERROR No CD interrupt occurs.
8 TXEMP : ERROR TXEMP is not set.
9 TXEMP INT : ERROR TXEMP interrupt does notoccur.
10 TXRDY : ERROR TXRDY is not set.
11 TXRDY INT : ERROR TXRDY interrupt does notoccur.
12 RCVRDY : ERROR RCVRDY is not set.(Not possible to receive.TRQ- occurs during theimplementation of check ii.)
13 RCVRDY INT : ERROR RCVRDY interrupt does notoccur.
14 SD-RD : ERROR SD-RD LOOP ERROR(DATA ERROR)
15 SD-RD : ERROR SD-RD LOOP ERROR(DATA ERROR)
16 TIMER : ERROR TIMER ERROR(After check ii is completed)
17 TIMER INT : ERROR TRQ1- interrupt does notoccur.
How to exit the program
Press the CANCEL key to exit the program.
PASS!!(or ERROR!!)
RS232 CH1 Check
4)-3. CH2 CheckChecking
The procedure for checking, display and the method of exiting theprograms are the same as for the CH1 check.
4)-4. CH3 CheckChecking
The procedure for checking, display and the method of exiting theprogram are the same as for the CH1 check.
4)-5. CH4 CheckChecking
The procedure for checking, display and the method of exiting theprogram are the same as for the CH1 check.
4)-6. CH5 CheckChecking
The procedure for checking, display and the mothod of exiting theprograms are the same as for the CH1 check.
4)-7. CH6 CheckChecking
The procedure for checking, display and the method of exiting theprograms are the same as for the CH1 check.
4)-8. CH7 CheckChecking
The procedure for checking, display and the method of exiting theprograms are the same as for the CH1 check.
4)-9. CH8 CheckFor checking CH8, the following loop-back connectors are used.
Checking
The following checks are performed.
i. Control signal check
ER8 RS8 DR8 Ci8 CD8 CS8
OFF OFF OFF OFF OFF OFF
OFF ON OFF ON
ON OFF ON OFF
ON ON ON ON
The program performs the read checks of the above inputs.
During the read check, ER and RS are changed over in the aboveorder, checking the logic of DR, CI, CD and CS.
If the logic is different from those listed in the table, the errormessage appears.
PATTERN 1
ER8 RS8 CI8 CD8
OFF ON OFF OFF
ON OFF OFF OFF
ON ON OFF OFF
"No Connect" is displayed on the next line of PASS!!.
PATTERN 2
ER8 RS8 CI8 CD8
OFF ON OFF OFF
ON OFF ON OFF
ON ON ON OFF
"CI Connect is displayed on the next line of PASS!!
PATTERN 3
ER8 RS8 CI8 CD8
OFF ON OFF OFF
ON OFF OFF ON
ON ON OFF ON
"CD Connect! is displayed on the next line of PASS!!If the logic is different from those in PATTERN 1 - 3, the errormessage appears."ON" means active low and "OFF" active high.The above checks are repeated for four cycles.
ii. Data transfer check
As check data, loop back data transfer of 256 bytes of 00H - 0FFHis performed, the baud rate is set for115200 bps.
Display
Details of the errors are printed on the journal.
ERRORNo.
ERROR print Details of ERROR
1 ER-DR : ERROR ER-DR LOOP ERROR
2 ER-CI : ERROR ER-CI LOOP ERROR
3 RS-CD : ERROR RS-CD LOOP ERROR
4 RS-CS : ERROR RS-CS LOOP ERROR
5
6
7
8 TXEMP : ERROR TXEMP is not set.
9 TXEMP INT : ERROR TXEMP interrupt does notoccur.
10 TXRDY : ERROR TXRDY is not set.
11 TXRDY INT : ERROR TXRDY interrupt does notoccur.
1pinRS
2pinER
3pinSD
4pinCI/CD
5pinGND6pinRD
7pinDR
8pinCS
PASS!!(or ERROR!!)
RS232 CH8 Check
CD Connect(or CI Connect, No Connect)
ERRORNo.
ERROR print Details of ERROR
12 RCVRDY : ERROR RCVRDY is not set.(Not possible to receive. TRQ-occurs during theimplementation of check ii.)
13 RCVRDY INT : ERROR RCVRDY interrupt does notoccur.
14 SD-RD : ERROR SD-RD LOOP ERROR(DATA ERROR)
15 SD-RD : ERROR SD-RD LOOP ERROR(DATA ERROR, FRAMINGERROR, and others)
16
17
18 CI : ERROR The logic of C1 is ON, butdifferent from those in 1~3.
19 CD : ERROR The logic of CD is ON, butdifferent from those in 1~3.
How to exit the program.Press the CANCEL key to exit the program.
5) LCD/POPUP/POLE DISPLAY & PRINTERDIAGNOSTICS
The program tests the LCD, popup and pole displays of the UP-700.
The following menu appears on screen. The cursor shown in reversevideo can be moved using the up/down arrow keys. Move the cursorto the menu item you want to execute and select by pressing theEnter key to execute the corresponding Diag. program. You can re-turn the screen to this submenu by pressing the CANCEL key.
The test program displays the following test patterns in the ordershown below. You can move to the next pattern by pressing theENTER key.
You can return the screen to this submenu by pressing the ENTERkey when the final test pattern is shown on the screen or by pressingthe CANCEL key during the implementation of the check.
5)-1. Liquid Crystal Display CheckChecking
The screen shows the following test patterns. Press the ENTERkey to move to the next test pattern.
i. Black and white checkered pattern with 1-dot spacing.
ii. Reverse-videoed test pattern of i
iii. Vertical stripe pattern with 1-dot spacing
iv. Reverse-videoed test pattern of iii
v. Horizontal stripe pattern with 1-dot spacing
vi. Reserve-videoed test pattern of v
vii. The outermost periphery of LCD’s active area is displayed in1-dot line.
viii. "H" pattern. "H" is displayed in 20 digits and 8 lines."H" is displayed in 19 digits only in the 8th line.
PES&NES SENSOR Check
PRINTER CG Check
PRINTER Check
POLE Check
POPUP Check
LCD Check
DISPLAY&PRINTER DIAG
A/D CONVERTER Check
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
How to exit the program.
You can exit the program by pressing the ENTER key when thefinal test pattern is shown on the screen or by pressing the CAN-CEL key during checking.
5)-2. Pole Display CheckChecking
The screen shows the following test patterns in the order givenbelow. Press the ENTER key to move to the next pattern.
i. The following test patterns are displayed.
ii. The test pattern where all digits are turned ON is displayed.
Display
How to exit the program.
You can return to the Diag. submenu by pressing the ENTER keyafter the 2nd test pattern where all digits are turned ON and aredisplayed. Or press the CANCEL key to erase the screen to exitthe program.
5)-3. Popup Display CheckChecking
The screen shows the following test patterns in the order givenbelow. Press ENTER to move to the next pattern.
i. The following test patterns are displayed.
ii. The test pattern where all digits are turned ON is displayed.
Display
How to exit the program
You can return to the Diag. submenu by pressing the ENTER keyafter the 2nd test pattern where all digits are turned ON and aredisplayed. Or press the CANCEL key to erase the screen to exitthe program.
5)-4. PRINTER CheckChecking
The printer prints on the RECEIPT/JOURNAL PRINTER.
Display
JOURNAL/RECEIPT print
How to exit the program
One second after printing is completed, the screen returns to thePRINTER Check of the DISPLAY & PRINTER MENU.
5)-5. PRINTER CG CheckChecking
The printer prints the built-in CG onto the RECEIPT/JOURNALPRINTER.
For standard characters are printed in 16 characters/line and ex-tended ASCII characters (enlarged characters) are printed in 8characters/line.
Standard characters are printed first, followed by the extendedASCII characters.
Check the outputted print to see if CG is correctly printed.
Display
How to exit the program.
Press the CANCEL key to exit the program after 1 cycle of printingis completed.
DOT DISPLAY
7SEG DISPLAY
:
:
0 1 2 3 4 5 6 7 8 9 ; A a B b C
0 . 1 . 2 . 3 . 4 . 5 . 6 . 7 . 8 . 9 . - .
POLE Display Check
7 SEG DISPLAY : 0 . 1 . 2 . 3 . 4 . 5 . 6 .
POPUP Display Check
PRINTER Check
UP-600/700 DIAGNOSTICS V1.0A
30 digits areprinted
Enlargement
Enlargement
30 digits areprinted30 digits areprinted30 digits areprinted30 digits areprinted
PRINTER CG Check
5)-6. PES & NES SENSOR CheckChecking
The screen displays the operating status of the paper end sensorand paper near end sensor of the receipt/journal printer.
Display
Display Status Description
NES 0 Senses the near end of the journal paper roll.
1Does not sense the near end of the journalpaper roll.
RPES 0 Senses the end of the receipt paper roll.
1 Does not sense the end of the receipt paper roll.
JPES 0 Senses the end of the journal paper roll.
1 Does not sense the end of the journal paper roll.
OPBS 0 IPL ROM PWB not connected
1 IPL ROM PWB connected
How to exit the program
Press the CANCEL key to exit the program.
5)-7. A/D Converter CheckChecking
The digital values of signals inputted into the A/D converter of theCPU are displayed one by one. The data on the screen are up-dated at an interval of about 1 second by the timer.
Screen
Note 1: VRF means a VRF estimated voltage calculated on theassumption that VCC is +5V.
Note 2: In the *** section, 10-bit data of the A/D converter isindicated in hexadecimal numbers. The numbers are from"000" to "3FF".
How to exit the program
Press the CANCEL key to exit the program.
6) TCP/IP STACK NETWORK DIAGNOSTICS The program performs the TCP/IP stack test.The test requirements are as follows:
• UP-700
• 10BASE-T cable (for data transfer testing)
• HUB (for loop back test and data transfer test where 2 or moreunits are used.)
The following menu appears. The cursor shown in reverse video canbe moved using the up/down arrow keys. Move the cursor to themenu item you want to execute and press the ENTER key to executethe corresponding check program. After the selected Diag. program iscompleted, the screen returns to this menu.
Press the CANCEL key to return the screen to the Diag. submenu.
6)-1. SELF CheckChecking
The program executes Diag’s built in TCP/IP stack board anddisplays the results.
i. Execute the flash memory test command and display the re-sult.
ii. Execute the SRAM test command and display the result.
iii. Execute the dual-port RAM test and display the result.
iv. Execute the interrupt test command and display the result.
The information inside the error status is as follows:
b7 Reserved ("0" is always displayed)
b6 Reserved ( "0" is always displayed)
b5 Reserved ("0" is always displayed)
b4 Reserved ( "0" is always displayed)
b3 HR_RST : If /INTHR cannot be canceled
b2 HR_ACK:If /INTHR does not enter after waiting for 10 ms
b1 HW_RST : If /INTHW cannot be canceled
b0 Reserved ("0" is always displayed)
Display
How to exit the program.
Press the CANCEL key to exit the program.
NES : 0 (or 1)
RPES : 0 (or 1)
JPES : 0 (or 1)
OPBS : 0 (or 1)
PES&NES SENSOR Check
VP=***
VRF=***
TM=***
A/D CONVERTER Check
DATA Trans.(SA)
DATA Trans.(MA)
MAC ADDR&FIRM WRITE
MAC ADDR&FIRM Ver. Read
LOOPBACK Check
SELF Check
TCP/IP&PRINTER DIAG
XXXXXXXX
INTERRUPT : PASS (or ERROR)
XXXXXXXX : XX : XX
DPRAM : PASS (or ERROR)
XXXXXXXX : XX : XX
SRAM : PASS (or ERROR)
FLASH : PASS (or ERROR)
SELF Check
When an error occurs,the address and dataare displayed.
When an error occurs,the data is displayed.
When an error occurs,the address and dataare displayed.
6)-2. LOOPBACK CheckChecking
Install a straight cable between the RJ45 connector and the HUBand execute the loop back test command to send and receive 1packet of data.
Display
How to exit the program
Press the CANCEL key to exit the program.
6)-3. MAC ADDRESS&FIRM Ver. read CheckChecking
The program reads the version of the MAC address and firmwareand displays the result.
Display
How to exit the program
Press the CANCEL key to exit the program.
6)-4. MAC ADDRESS&FIRM write UTILITYOperation
This utility writes the MAC address and firmware.(Procedure)
Install master ROM EPROM on the TCP/IP board and turn the IPLswitch on the board to the "program write mode."
Turn on the ECR.
The IPL program on the TCP/IP board starts.
Input 3 sets of 3-digit decimal numbers through the keyboard ofthe ECR and press the ENTER key.
Following the SHARP maker code (08, 00, 1F), the 3 sets ofnumbers input through the keyboard are converted into hexadeci-mal numbers. The program then writes a total of 6 bytes of MACaddress into dual port RAM (800000H - ).
Turn off the power supply.
Remove the EPROM from the TCP/IP board and turn the IPLswitch to the "normal mode."
Input : DUAL PORT RAM (800000H‘)
MAC ADDRESS (XX, YY, ZZ are converted to 16 hexadecimalnumbers.)
Output : DUAL PORT RAM (800800H‘)
During writing
When writing is completed (The same applies when the copy isskipped at the first verification.)
When the writing process ends with an error.
Display
TCP/IP FIRM CHANGE :
While the address and firmware are being rewritten, the messageA and then B appears.
When the address and firmware have been rewritten, the mes-sage C is displayed.
The following screen appears when the IPL switch is not turned tothe write mode.
How to exit the program.
Press the CANCEL key to exit the program.
After rewriting, make sure to turn the power off and then turn iton again.
LANC ERROR
LOOPBACK ERROR
LOOPBACK : PASS (or ERROR)
LOOPBACK Check
Displayed when anerror occurs.Displayed when anerror occurs.
XXXXXXXXXX
FIRMWARE VERSION :
XX XX XX XX XX XX
MAC ADDRESS :
MAC ADDR&FIRM Ver. Read
Data of 6 bytes isdisplayed.
10 digits aredisplayed.
08 00 1F XX YY ZZ
I P L 0 0 0 7 0 0
I P L 0 0 0 7 O K
I P L 0 0 0 7 N G
IPL 00-07 XX (XX : 00~07 OK or NG)
TCP/IP FIRM CHANGE
08 00 1F XX YY ZZ
AAA BBB CCC
MAC ADDRESS
MAC ADDR&FIRM Write Decimal numbers areinput throughkeyboard.
Data of 6 bytes isdisplayed ashexadecimal numbers
A ERASE 00-07 00
B COPY 00-05 00
C FIRM CHANGE PASS!!
CHANGE IPL SW!!
MAC ADDR&FIRM Write
6)-5. Data Transmission CheckThe program performs a data transfer test using an actual estab-lished system.
The system consists of 1 master machine and up to 63 satellitemachines.Caution to be taken when starting the test.
• If this test is performed on the ECRs set for LAN, cancel thesettings before starting the test.
• If this test is performed using an established system, disconnectthe LAN cables from the ECRs you do not want to test or canceltheir LAN settings. If the test is performed with those ECRs set forLAN, their data might be destroyed.
• After canceling the LAN settings of all ECRs on the system, setthem for data the transfer test.Set the satellite machines first, and then set the master machine.
• The Diag of the UP-700 uses a private IP address. Each IP ad-dress is unique on the Internet. When building a private network,you should be careful not to allow your internal packet used foryour own network to leak to the Internet, because it might causeconfusion. The Internet Assigned Numbers Authority (IANA) speci-fies IP addresses that can be used without registration. Theseaddresses can only be used within a private network and are notroute controlled between sites of the Internet.
Class A : 10.x.x.xClass B : 172.16.x.x 172.31.x.xClass C : 192.168.0.x?192.168.255.x
It is strongly recommended to use addresses within the aboverange when building a private network.
In this Diag. program, the following private IP addresses are as-signed to the terminal Nos. (1 - 64).
TERMINAL NO.1 = 192.168.0.1TERMINAL NO.2 = 192.168.0.2......
TERMINAL NO.31 = 192.168.0.63TERMINAL NO.32 = 192.168.0.64
Setting
i. Setting satellite machines
On the menu screen, select DATA Trans. (SA). The screen isshown below:
Enter the terminal No. of the machine you are going to test (a2-digit number from 1 - 32) + Enter. The screen looks like this:
i. Setting the master machine.
On the menu screen, select DATA Trans. (MA). The screenlooks like this:
Enter the terminal No. of the machine you want to test (a2-digit number from 1 - 64)+ Enter. The screen looks like this:
Enter the terminal No. (a 2-digit number from 1 -64) of thesatellite machines which are connected to the test machine +Enter. The screen looks like this:
When performing the test with multiple satellite machines, type theirterminal numbers (2-digit numbers within the range from 1~64) andpress Enter. In addition, you specify the satellite machines using thearea specification function without typing terminal numbers. This isachieved by typing the first terminal number (2 digits) and the lastterminal number (2 digits) of the satellite machines and then pressEnter. For example, if you want to specify the terminal numbers ofsatellite machines from 5 to 15, type "0515" for T-No. and press Enter.When executing, press the Enter key without typing the terminalnumbers.The display appears like this:Note that the terminal numbers of the master machine and satel-lite machines should not be the same. When the terminal numbersare to be specified using the area specification function, any termi-nal number that is used for the master machine will be excludedfrom the specification of satellite machine terminal numbers.
With the above setting, data transfer is performed between themaster machine and the satellite machines.
INPUT SA T-NO.
DATA Trans.(SA)
Enter a numberwithin the rangefrom 1 64.
DATA SEQ.NO. : 0000
INPUT SA T-NO. : XX
DATA Trans.(SA)
The terminal No. youentered is displayed.
INPUT MA T-NO. :
DATA Trans.(MA)
Enter a numberwithin a rangefrom 1~64.
INPUT MA T-NO. : XX
DATA Trans.(MA)
INPUT SA T-NO. :
The terminal No. youentered is displayed.
INPUT MA T-NO. : XX
DATA Trans.(MA)
INPUT SA T-NO. : XX( or XXXX)
The terminal No. ofthe master machineyou entered isdisplayed.
The terminal No. ofthe satellite machineyou entered isdisplayed.
INPUT MA T-NO. : XX
DATA SEQ.NO. : 0000
The terminal No. ofthe master machineyou entered isdisplayed.
Checking
i. The master machine sends data of the following format con-sisting of 2-byte sequence No. and 254-byte AAH data to thesatellite machine. The master machine displays the sequenceNos.
Test data format (1 packet: 256 bytes)
XXXX : Sequence No. 2 bytes (4-digit binary coded decimalnumber)
AA : Transfer (AAH) ~ 254 bytes
ii. The satellite machine returns the data it has received, to themaster machine as it is. The satellite machine displays thesequence No. on the screen.
iii. The master machine receives the data and then checks thesequence Nos. and 254-byte AAH data. If an error occurs, themaster machine displays an error code and ends the test. Ifthere are multiple satellite machines, steps i and ii are re-peated.
The master machine advances the sequence No. when data istransferred successfully between it and the satellite machines.
Steps i - iii are repeated.
Error display
The following error codes are used (same as for TCP/IP HANDLER)
01 Command error (excluding the time when data is sent)
02 No data received
03 Received data size presentReceived data left
04 Receiving station not ready for receiving (when sending)"NRDY" is returned because the receiving station is notready for receiving.
05 Receiving buffer full(when sending)The receiving side’s controller receive buffer is full.
06 Resend error(When sending)The number of retries exceeds the setting (5 times) whenno response is obtained.
07 Collision error (When sending)If a collision occurs
08 Line busy time outData cannot be sent due to multiple stations communicating
09 Receiving data size over (when receiving)Insufficient size of receiving buffer.
0A Hardware errorInterface error (No SRN interface or defective SRNcontroller)
How to exit the programPress the CANCEL key to exit the program.
7) MCR & DRAWER DiagnosticsThe program checks the MCR and drawer.
The following menu appears on screen.
The cursor shown in reverse video can be moved using the up/downarrow keys. Move the cursor to the menu item you want to executeand select by pressing the ENTER key to execute the correspondingprogram. Press the CANCEL key to return the screen to this sub-menu.
7)-1. Magnetic Card Reader CheckThe program performs the read test of an optional UP-E13MR.
The test program reads a magnetic card using the ISO7811/1-5standard and prints data on the journal.
Press the CANCEL key to return the screen to the submenu.
Checking
The program reads tracks 1 - 3 of a magnetic card using theISO7811/1‘5 standard and prints the data with the ASCII codes.
JOURNAL print
Data read by the MCR is printed in the areas XXXXX. If an erroroccurs, the following error codes are displayed. Until the programis terminated, the error code is repeated, standing by for reading.
Display
How to exit the program.
Press the CANCEL key to exit the program.
XX XX AA AA AA AA AA AA
1 2 3 4 5 254 255 256 byte
TCP/IP ERROR : XX
XX XX XX XX XX XX
XX XX XX XX XX XX
XX XX XX XX XX XX
INPUT MA T-NO. : XX
The terminal No. ofthe master machineyou entered isdisplayed.
After executing, all theterminal Nos. of thesatellite machines aredisplayed.Up to 63 units.
The error codeappears on screen.
DRAWER 2 Check
DRAWER 1 Check
MCR Check
MCR&DRAWER Check
XXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXX
TRACK2:
TRACK1:MCR Check
XXXXXXXXXXXXXXXXXXXXXXXXXXX
TRACK3:
TRACK3 : PASS TRACK2 : MCR ERROR
TRACK1 : BUFFER EMPTY
MCR Check Receive data isempty
Data error afterdetecting card.
Data has been readsuccessfully.
7)-2. Drawer 1 CheckChecking
The program turns on the drawer 1 solenoid, senses the value of thedrawer open sensor every 100 ms, and displays the operating status.
Display
How to exit the program
Press the CANCEL key to exit the program.
7)-3. Drawer 2 CheckChecking
The program turns on the drawer 2 solenoid, senses the value of thedrawer to open the sensor every 100ms, and displays the operatingstatus. The procedure for displaying the menu and exiting the pro-gram are the same as for the drawer 1 check.
Open Sensor : OPEN (or CLOSE)
DRAWER 1 Check
CHAPTER 6. CIRCUIT DESCRIPTION
1. HARDWARE BLOCK DIAGRAM
DRAWER x 2
RS232 x 2
UP-P16DP(POLE-DISP)
ControllerCKDC9
CPU
H8/510
FLASHROM
Max.2MB
SYSTEMG/A
(MPCA9)
S-RAM(STD)Max.512KB
S-RAM(STD)Max.4MB
UP-S02MB:2MB
UP-S04MB:4MB
KEY/SW/POPControllerCKDC9
LCDControllerM66271
Thermal PRN.(PR-58HM)
MCR UNITUP-E13MR
LCD UNIT
RS232 x 2
10base-T
OptionalCARD
ER-A5RS
EthernetController
(TCP/IP stack)
UP-E10IN
2. DESCRIPTION OF MAIN LSI’s
1) CPU (HD6415108FX)
1)-1. Pin description
RESNMIVSSP10P11P12P13P14P15P16P17D8D9
D10D11D12D13D14D15VSS
A0A1A2A3A4A5A6A7
12345678910111213141516171819202122232425262728
ST
BY
MD
2M
D1
MD
0V
CC
RF
SH
LWR
HW
RR
DA
SE VS
SX
TA
LE
XT
AL
VS
ST
XD
2R
XD
2T
XD
1R
XD
1S
CK
2/IR
Q3
SC
K1/
IRQ
2IR
Q1
IRQ
0V
CC
AV
CC
P73
P72
112
111
110
109
108
107
106
105
104
103
102
101
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
P41P42P43P44P45P46P47VSSP50P51P52P53P54
P56P57P60P61P62P63P64P65P66P67VSSAVSSP70P71
57585960616263646566676869707172737475767778788081828384
A8
A9
A10
A11
A12
A13
A14
A15
VS
SA
16A
17A
18A
19A
20A
21A
22A
23V
SS
P30
/WA
ITP
31/B
AC
KP
32/B
RE
QP
33P
34P
35P
36P
37V
CC
P40
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
X
P55
>>>>> USE FONT <<<<<
Helvetica/ Helvetica-Condensed/ Century-Schoolbook/ Symbol & OriginalFonts: (RingWorld2/RingFont2/Pa
Symbol/PartsCod)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1)-2. Block diagram
P47
P46
P45
P44
P43
P42
P41/TMCI
P40
P37
P36
P35
P34
P33
BREQ
BACK
WAIT
P27/A23
P26/A22
P25/A21
P24/A20
P23/A19
P22/A18
P21/A17
P20/A16
A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AVCC
AVSS
MD2
MD1
MD0
RES
STBY
NMI
AS
RD
HWR
LWR
RFSH
EXTAL
XTAL
E
P17
P16
P15
P14
P13
P12
P11
P10
D15
D14
D13
D12
D11
D10
D9
D8
P57
P56
P55
P54
P53
P52
P51
P50
P67
P66
P65
P64
P63
P62
P61
P60
P73
P72
P71
P70
TX
D2
RX
D2
TX
D1
RX
D1
SC
K2/
IRQ
3
SC
K1/
IRQ
2
IRQ
1
IRQ
0
H8/500 CPU DTC
Serialcommunicationinterface x 2ch
8bit timer
16bit free runningtimer x 2ch
Refresh controller
Wait statecontroller
A/D convertor
Interruption controller
Clockoscillator
Watchdog timer
Data bus Port 1
Dat
a bu
s (L
ower
)
Dat
a bu
s (U
pper
)
Add
ress
bus
Por
t 2P
ort 3
Por
t 4
Port 5Port 6Port 7Port 8
Add
ress
bus
X
1)-3. Pin description
PinNo.
SymbolSignalname
In/Out
Function
1 /RES /RESET In Reset signal
2 NMI NMI InNon-maskable interrupt inputfor SSP interrupt input.
3 VSS GND In GND4 D0 D0 I/O Data bus 5 D1 D1 I/O Data bus 6 D2 D2 I/O Data bus 7 D3 D3 I/O Data bus 8 D4 D4 I/O Data bus 9 D5 D5 I/O Data bus
10 D6 D6 I/O Data bus 11 D7 D7 I/O Data bus 12 D8 D8 I/O Data bus 13 D9 D9 I/O Data bus 14 D10 D10 I/O Data bus 15 D11 D11 I/O Data bus 16 D12 D12 I/O Data bus 17 D13 D13 I/O Data bus 18 D14 D14 I/O Data bus 19 D15 D15 I/O Data bus 20 VSS GND In GND21 A0 A0 Out Address bus 22 A1 A1 Out Address bus 23 A2 A2 Out Address bus 24 A3 A3 Out Address bus 25 A4 A4 Out Address bus 26 A5 A5 Out Address bus 27 A6 A6 Out Address bus 28 A7 A7 Out Address bus 29 A8 A8 Out Address bus 30 A9 A9 Out Address bus 31 A10 A10 Out Address bus 32 A11 A11 Out Address bus 33 A12 A12 Out Address bus 34 A13 A13 Out Address bus 35 A14 A14 Out Address bus 36 A15 A15 Out Address bus 37 VSS GND In GND38 A16 A16 Out Address bus 39 A17 A17 Out Address bus 40 A18 A18 Out Address bus 41 A19 A19 Out Address bus 42 A20 A20 Out Address bus 43 A21 A21 Out Address bus 44 A22 A22 Out Address bus45 A23 A23 Out Address bus 46 VSS GND In GND47 P30 /WAIT In Wait signal
48 P31 /BACK OutBus control requestacknowledge signal
49 P32 /BREQ In Bus control request signal 50 P33 DOPS In Drawer open signal 51 P34 /DR0 Out Option drawer open signal 52 P35 /DR1 Out Option drawer open signal 53 P36 NC NC NC54 P37 NC NC NC 55 VCC VCC In +5V 56 P40 VCC In +5V 57 P41 GND In GND 58 P42 GND In GND
PinNo.
SymbolSignalname
In/Out
Function
59 P43 GND In GND 60 P44 MCRINT In MCR interrupt signal 61 P45 GND In GND
62 P46 /SHEN InCKDC interface shift enablesignal
63 P47 GND In GND 64 VSS GND In GND 65 P50 – Out /DTR2 : Data Terminal Ready266 P51 – In /DSR2 : Data Set Ready267 P52 – In /CTS2 : Clear To Send268 P53 – In /DCD2 : Carriar Detect269 P54 – In NC70 P55 NC Out /RTS2:Request To Send271 P56 – In /CI2:Calling Indicator272 P57 /STOP Out System reset output signal 73 P60 /IPLON0 In From IPL SW74 P61 /IPLON1 In From IPL SW75 P62 GND In GND 76 P63 NORDY In Flash Memory ready ("H" active)
77 P64 FVPON OutFlash Memory write protect ("L"active)
78 P65 BANK Out For IPL ROM79 P66 GND In GND80 P67 GND In GND81 VSS GND In GND82 AVSS GND In GND83 P70 GND In GND84 P71 GND In GND85 P72 GND In GND86 P73 GND In GND87 AVCC VCC In +5V88 VCC VCC In +5V89 /IRQ0 /IRQ0 In Interrupt signal 090 /IRQ1 /IRQ1 In Interrupt signal 1
91 /IRQ2 UASCK InSynchronizing shift clock signalfor USART
92 /IRQ3 SCKI OutCKDC interface synchronizingshift clock
93 RXD1 /RCVDT2 In RXD signal for RS23294 TXD1 TXD2 Out TXD signal for RS23295 RXD2 RXDI In CKDC interface shift input data
96 TXD2 TXDI OutCKDC interface shift outputdata
97 VSS GND In GND
98 EXTAL EXTAL InCrystal oscillator connection19.6MHz
99 XTAL XTAL InCrystal oscillator connection19.6MHz
100 VSS GND In GND101 X # Out System clock102 E NC NC NC103 /AS /AS Out Address strobe104 RD /RD Out Read signal105 /HWR /HWR Out Write signal (HIGH)106 /LWR /LWR Out Write signal (LOW) 107 /RFSH /RFSH Out Refresh cycle signal108 VCC VCC In +5V109 MD0 IPLON0 In From IPL SW110 MD1 IPLON0 In From IPL SW111 MD2 /IPLON0 In From IPL SW112 /STBY VCC In +5V
2) G.A.(MPCA9)
2)-1. Pin configuration
VD
DS
T4#
DO
T4
ST
5# D
OT
5G
ND
ST
6# D
OT
6LA
TC
H#
DO
T7
SO
DO
T8
GN
DC
LOC
K D
OT
9S
ID
TC
SW
O L
CD
WT
DT
ST
#IN
HD
EC
CS
EN
#T
TS
T2#
TT
ST
1#T
IRQ
#IN
H#
RP
EJP
EP
HU
P P
EP
CR
ES
PF
PV
HC
OM
GN
DV
DD
RV
PO
N T
RG
#JV
PO
N T
RG
CT
BO
PC
UT
#C
TA
O F
CU
T#
RD
S P
RS
T#
RC
S P
TM
G#
RB
S R
JMT
DR
AS
RJM
TS
JDS
ST
AM
P#
JCS
VF
#JB
S R
F#
JAS
JF
#P
TR
M R
JTM
GP
TJM
TR
GI
PO
PI R
JRS
TB
A15
BA
14G
ND
BA
13B
A12
BA
11B
A10
BA
9B
A8
VD
D
GNDGNDBA7BA6BA5BA4BA3BA2BA1GNDBA0BWR#BRD#BRASBRAS#BD7BD6BD5GNDBD4BD3GNDBD2BD1BD0GNDVDDINT3#INT2#INT1#INT0#HTS1SCK1#STH1IPLON#RESET#UTST#USEL0USEL1USEL2MCRINTWAIT#FROS1#RASPN1RASPN2EPROM1#DSEX#RXDHTXDHSCKHGNDGND
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152
VD
DA
23A
22A
21A
20A
19A
18A
17A
16A
15A
14A
13A
12A
11A
10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
GN
DV
DD D7
D6
D5
GN
D D4
D3
GN
D D2
D1
D0
GN
DS
SP
RQ
#IR
Q1#
IRQ
0#W
R#
RD
#A
S#
PH
AI
MD
0M
D1
UA
SC
KG
ND
OS
I1O
SO
1V
DD
GNDGND
ST3# DOT3ST2# DOT2ST1# DOT1
NCTTHR
RTS3#DTR3#
RXRDY3TRXRDY3
TXD3TXRDY3
TRXC3RXD3
BUSY3#EXINT3#EXINT2#EXINT1#EXINT0#
EXWAIT#DSF2#
VWAIT#DSF1#DSCX#
GNDVDD
OPTCS#IPLONRXC1RXD1
DSR1#RXC2RXD2
DSR2#RXC4RXD4
DSR4#STH2
SCK2#HTS2INT4#
RTS5#DTR5#
TXD5RXD5
CTS5#DSR5#
CI5#CD5#GNDGND
104
103
102
101
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
156155154153152151150149148147146145144143142141140139138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109108107106105
2)-2. Block diagram
A23~A0D7~D0
/AS,/RD,/WRPHAI,/RESET
MPCA9
MPCA
TPRC1
OPC
INT4#~INT0#
MCRINT
WAIT#
FROS1#,EPROM1#
RASPN1,2
DSEX#
RXDH,TXDH,SCKH
OSO1,OSI1
USACK
MD1,MD2
IRQ0#
SSPRQ#
HTS2,SCK2,STH2
RXD4,RXC4,DSR4#
RXD2,RXC2,DSR2#
RXD1,RXC1,DSR1#
IPLON
OPTCS#
VMEMC#,VIOC#DSF2#
VWAIT#,EXWAIT#
EXINT0#,EXINT1#EXINT2#,EXINT3#
BUSY3#,RXD3,TXD3TRXC3,TXRDY3TRXRDY3,RXRDY3DTR3#,RTS3#
VRESC
DTCS,DTST#
LCDWT
USEL2~USEL0, UTST#,
BA15~BA0
BD7~BD0
BWR#,BRD#
BRAS,BRAS#
ST1#~ST6#
LATCH#
SI,SO,CLOCK
PHUP,VHCOM
CSEN#,INH#
TIRQ#
RPE,JPE
PCRES,PFP
RVPON,JVPONCTBO,CTAO
RAS,RBS,RCS,RDS
JAS,JBS,JCS,JDS
PTRM,PTJM
POPI
TTST1#,TTST2#
IRQ1#
TXD5,RXD5
DTR5#,RTS5#
DSR5#,CTS5#
CD5#,CI5#
DBTST
2)-3. Pin description
PinNo.
Name IN/OUT Description
1 GND - GND
2 GND - GND
3 BA7 O Address bus 7 for PB-RAM
4 BA6 O Address bus 6 for PB-RAM
5 BA5 O Address bus 5 for PB-RAM
6 BA4 O Address bus 4 for PB-RAM
7 BA3 O Address bus 3 for PB-RAM
8 BA2 O Address bus 2 for PB-RAM
9 BA1 O Address bus 1 for PB-RAM
10 GND - GND
11 BA0 O Address bus 0 for PB-RAM
12 BWR# O PB-RAM write strobe signal
13 BRD# O PB-RAM read strobe signal
14 BRAS O PB-RAM chip select : Active High (NU)
15 BRAS# O PB-RAM chip select : Active Low
16 BD7 I/O Data Bus 7 for PB-RAM
17 BD6 I/O Data Bus 6 for PB-RAM
18 BD5 I/O Data Bus 5 for PB-RAM
19 GND - GND
20 BD4 I/O Data Bus 4 for PB-RAM
21 BD3 I/O Data Bus 3 for PB-RAM
22 GND - GND
23 BD2 I/O Data Bus 2 for PB-RAM
24 BD1 I/O Data Bus 1 for PB-RAM
25 BD0 I/O Data Bus 0 for PB-RAM
26 GND - GND
27 VDD - +3.3V
28 INT3# I Interrupt signal 3 (NU)
29 INT2# I Shift enable for CKDC9
30 INT1# I Keyboard request for CKDC9
31 INT0# I Power off signal input
32 HTS1 O 8 bit serial port output (for CKDC9)
33 SCK1# O Serial port shift clock output (for CKDC9)
34 STH1 I 8 bit serial port input (for CKDC9)
35 IPLON# I IPL switch 0 ON signal
36 RESET# I MPCA reset
37 UTST# I MPCA test pin (+3.3V)
38 USEL0 I MPCA test pin (GND)
39 USEL1 I MPCA test pin (GND)
40 USEL2 I MPCA test pin (GND)
41 MCRINT O MCR interrupt signal
42 WAIT# O Wait request signal
43 FROS1# O Flash ROM 1 chip select signal
44 RASPN1 O RAM 1 chip select signal
45 RASPN2 O RAM 2 chip select signal
46 EPROM1# O EP-ROM 1 chip select signal
47 DSEX# O EP-ROM 2 chip select signal
48 RXDH O 8 bit serial port output to CPU
49 TXDH I 8 bit serial port input from CPU
50 SCKH I Serial port shift clock input from CPU
51 GND - GND
52 GND - GND
53 VDD - +3.3V
54 OSO1 O System clock (7.37MHz)
PinNo.
Name IN/OUT Description
55 OSI1 I System clock (7.37MHz)
56 GND - GND
57 UASCK O USAT clock to CPU
58 MD1 I MPCA test pin (GND)
59 MD0 I MPCA test pin (GND)
60 PHAI I System clock (9.83MHz)
61 AS# I Address strobe
62 RD# I Read Strobe
63 WR# I Write Strobe
64 IRQ0# O Interrupt request 0 to CPU
65 IRQ1# O Interrupt request 1 to CPU
66 SSPRQ# O SSP interrupt request to CPU
67 GND - GND
68 D0 I/O Data Bus 0
69 D1 I/O Data Bus 1
70 D2 I/O Data Bus 2
71 GND - GND
72 D3 I/O Data Bus 3
73 D4 I/O Data Bus 4
74 GND - GND
75 D5 I/O Data Bus 5
76 D6 I/O Data Bus 6
77 D7 I/O Data Bus 7
78 VDD - +3.3V
79 GND - GND
80 A0 I Address bus 0
81 A1 I Address bus 1
82 A2 I Address bus 2
83 A3 I Address bus 3
84 A4 I Address bus 4
85 A5 I Address bus 5
86 A6 I Address bus 6
87 A7 I Address bus 7
88 A8 I Address bus 8
89 A9 I Address bus 9
90 A10 I Address bus 10
91 A11 I Address bus 11
92 A12 I Address bus 12
93 A13 I Address bus 13
94 A14 I Address bus 14
95 A15 I Address bus 15
96 A16 I Address bus 16
97 A17 I Address bus 17
98 A18 I Address bus 18
99 A19 I Address bus 19
100 A20 I Address bus 20
101 A21 I Address bus 21
102 A22 I Address bus 22
103 A23 I Address bus 23
104 VDD - +3.3V
105 GND - GND
106 GND - GND
107 CD5# I RS-232 ch1 CD signal
108 CI5# I RS-232 ch1 CI signal
PinNo.
Name IN/OUT Description
109 DSR5# I RS-232 ch1 DSR signal
110 CTS5# I RS-232 ch1 CTS signal
111 RXD5 I RS-232 ch1 RXD signal
112 TXD5 O RS-232 ch1 TXD signal
113 DTR5# O RS-232 ch1 DTR signal
114 RTS5# O RS-232 ch1 RTS signal
115 INT4# I Shift enable for option display
116 HTS2 O 8 bit serial port output (for option display)
117 SCK2# OSerial port shift clock output(for option display)
118 STH2 I 8 bit serial port input (for option display)
119 DSR4# I MCR track 3 CLS signal
120 RXD4 I MCR track 3 RDD signal
121 RXC4 I MCR track 3 RCP signal
122 DSR2# I MCR track 2 CLS signal
123 RXD2 I MCR track 2 RDD signal
124 RXC2 I MCR track 2 RCP signal
125 DSR1# I MCR track 1 CLS signal
126 RXD1 I MCR track 1 RDD signal
127 RXC1 I MCR track 1 RCP signal
128 IPLON O IPL switch 0 ON signal to CPU
129 OPTCS# OChip select base signal for expansionoption
130 VDD - +3.3V
131 GND - GND
132 VMEMC# O VRAM chip select signal
133 VIOC# O LCDC chip select signal
134 VWAIT# I LCDC wait signal
135 DSF2# O DPRAM chip select signal
136 EXWAIT# I External wait signal
137 EXINT0# I External interrupt signal 0
138 EXINT1# I External interrupt signal 1
139 EXINT2# I External interrupt signal 2
140 EXINT3# I External interrupt signal 3
141 BUSY3# I Fiscal memory BUZY signal (NU)
142 RXD3 I Fiscal memory RXD signal (NU)
143 TRXC3 I Fiscal memory CLOCK signal (NU)
144 TXD3 O Fiscal memory TXD signal (NU)
145 TXRDY3 O NU
146 TRXRDY3 O NU
147 RXRDY3 O Fiscal memory READY signal (NU)
148 DTR3# O Fiscal memory DTR signal (NU)
149 RTS3# O Fiscal memory RTS signal (NU)
150 DBTST I MPCA test pin (GND)
151 VRESC O NU
152 ST1# O Thermal head drive strobe signal 1
153 ST2# O Thermal head drive strobe signal 2
154 ST3# O Thermal head drive strobe signal 3
155 GND - GND
156 GND - GND
157 VDD - +3.3V
158 ST4# O Thermal head drive strobe signal 4
159 ST5# O Thermal head drive strobe signal 5 (NU)
160 GND - GND
161 ST6# O Thermal head drive strobe signal 6 (NU)
162 LATCH# O Thermal head latch signal
PinNo.
Name IN/OUT Description
163 SO O Thermal head serial output data
164 GND - GND
165 CLOCK O Thermal head clock signal
166 SI I Thermal head serial return data
167 DTCS O Printer control select signal (GND)
168 LCDWT I Wait request signal to CPU (+3.3V)
169 DTST# I MPCA test pin (+3.3V)
170 INHDEC I CSEN# enable signal (GND)
171 CSEN# I TPRC chip select (GND)
172 TTST2# I MPCA test pin (+3.3V)
173 TTST1# I MPCA test pin (+3.3V)
174 TIRQ# O TPRC interrupt request
175 INH# I Thermal head drive inhibit
176 RPE I Receipt paper end signal
177 JPE I Journal paper end signal
178 PHUP I Printer head up signal
179 PCRES I Auto cutter unit reset signal
180 PFP I Auto cutter unit FP signal
181 VHCOM I Head drive common power control
182 GND - GND
183 VDD - +3.3V
184 RVPON OReceipt side paper feed pulse motorcommon power control signal
185 JVPON OJournal side paper feed pulse motorcommon power control signal (NU)
186 CTBO O Cutter motor control signal
187 CTAO O Cutter motor control signal
188 RDS OReceipt side paper feed pulse motordrive signal, phase D
189 RCS OReceipt side paper feed pulse motordrive signal, phase C
190 RBS OReceipt side paper feed pulse motordrive signal, phase B
191 RAS OReceipt side paper feed pulse motordrive signal, phase A
192 JDS OJournal side paper feed pulse motordrive signal, phase D
193 JCS OJournal side paper feed pulse motordrive signal, phase C
194 JBS OJournal side paper feed pulse motordrive signal, phase B
195 JAS OJournal side paper feed pulse motordrive signal, phase A
196 PTRM I Receipt motor connector sens signal
197 PTJM I Journal motor connector sense signal
198 POPI I GND
199 BA15 O Address bus 15 for PB-RAM
200 BA14 O Address bus 14 for PB-RAM
201 GND - GND
202 BA13 O Address bus 13 for PB-RAM
203 BA12 O Address bus 12 for PB-RAM
204 BA11 O Address bus 11 for PB-RAM
205 BA10 O Address bus 10 for PB-RAM
206 BA9 O Address bus 9 for PB-RAM
207 BA8 O Address bus 8 for PB-RAM
208 VDD - +3.3V
3) CKDC9 (HD404728B02FS)
3)-1. General descriptionThe CKDC9 is a 4-bit microcomputer developed for the UP-700 andprovides functions to control the real-time clock, keys, and displays.The basic functions of the CKDC7 are shown below.
Keys: The CKDC9 is capable of controlling a maximum of 256momentary keys. (Sharp 2-key rollover control)Simultaneous scanning of key and switch(When a key is scanned, the state of a mode and clerkswitch is also buffered. The host can scan the state ofswitch together with the key entry data at the same timethe key is scanned.)
Switches: Mode switch with 14 positions maximum8-bit clerk (cashier) switch2-bit feed switch1-bit receipt on/off switch1-bit option switch4-bit general-purpose switch (1-bit is used for keyboardselect)
Displays: 16-column dot display12-column 7-segment display (column digit selectable)All column blink controlled for the dot and 7-segment dis-play decimal point and indicatorsProgrammable patterns for 7-segment display:Four patternsInternal driver for 7-segment display
Buzzer: Single tone control
Clock: Year, month, day of month, day of week, hour, minute
Alarm: Hour, minute
Interrupt request (event control):
Detection of key input, switch position change, alarm is-sue, and counter overflow
3)-2. Pin description
PinNo.
SymbolSignalname
In/Out
Function
1 SB SB Out Segment B2 SC SC Out Segment C3 SD SD Out Segment D4 SE SE Out Segment E5 SF SF Out Segment F6 SG SG Out Segment G7 P4 AP Out8 P0 NC — NC9 P1 NC — NC
10 P2 DP Out Decimal point11 P3 ID Out Indicator12 MODR VCC — +5V
13 CFSR CFSR InClerk key, Feed key, Switchreturn signal
14 KEX0 NC Out NC15 KEX1 NC Out NC16 RQ GND — GND17 SKR0 VCC — +5V18 ST0 ST0 Out Key strobe signal19 ST1 ST1 Out Key strobe signal20 ST2 ST2 Out Key strobe signal21 ST3 ST3 Out Key strobe signal22 POFF POFF In Power off signal23 STOP STOP In STOP signal24 DDIG VCC — +5V
PinNo.
SymbolSignalname
In/Out
Function
25 DCS DCS —Dot display controller chip selectDCS
26 VCC VCKDC — +5V27 SCK SCK In Clock signal28 HTS HTS In Key data from host29 STH STH Out Key data to host30 SDISP GND — GND31 BUZZ BUZZ Out Buzzer32 DSCK DSCK — Dot display controller SCK33 SRES RESET Out Reset signal34 DS0 DSO — Dot display controller SO35 SHEN SHEN Out Shift enable signal36 IRQ KRQ Out Key request signal37 KR0 KR0 In Key return signal38 KR1 KR1 In Key return signal39 KR2 KR2 In Key return signal40 KR3 KR3 In Key return signal41 RESET CKDCR In CKDC reset signal42 OSC2 OSC2 — Clock43 OSC1 OSC1 — Clock44 GND GND — GND45 CL1 CL1 — Time clock46 CL2 CL2 — Time clock47 TEST VCKDC — +5V48 G0 G1 Out Display digit signal49 G1 G2 Out Display digit signal50 G2 G3 Out Display digit signal51 G3 G4 Out Display digit signal52 G4 G5 Out Display digit signal53 G5 G6 Out Display digit signal54 G6 G7 Out Display digit signal55 G7 G8 Out Display digit signal56 G8 G9 Out Display digit signal57 G9 G10 Out Display digit signal58 G10 G11 Out Display digit signal59 G11 NC Out NC60 PO0 NC NC61 PO1 NC NC62 PO2 NC — NC63 PO3 NC — NC64 SA SA — Segment A
4) LCD CONTROLLER (M66271FB)
4)-1. Pin configration
9786667697071726811765432
31302928272622212019181716156261
14 60 59 58 57 56 55 54 53 50 49 48 47 46 45 44 43 77 63 52 42 34 23 8
12 79 76 74 73 75 32 39 38 37 36 33 51 80 65 1 40 35 24 13 25 64 41 10
A13A12A11A10A9A8A7A6A5A4A3A2A1A0MLCDENB
MPUCLKOSC1
CPLP
UD0UD1UD2UD3FLM
RESETWAITMCS
RDLWRHWRIOCS
MP
US
EL
OS
C2
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
BH
ED
15D
14D
13D
12D
11D
10D
9D
8D
7D
6D
5D
4D
3D
2D
1D
0V
DD
VD
DV
DD
VD
DV
DD
VD
DV
DD
4)-2. Pin configration
PinNo.
Name Description
1 VSS GND
2 IOCS# Chip select input for control register
3 HWR# High write strobe input
4 LWR# Low write strobe input
5 RD# Read strobe input
6 MCS# Chip select input for VRAM
7 WAIT# WAIT output to MPU
8 VDD +5V
9 MPUCLK MPU clock
10 VSS GND
11 RESET# Reset input
12 MPUSEL 8/16-bit selective input to MPU
13 VSS GND
14 BHE# Bus high enable input
15 A0 MPU address bus 0
16 A1 MPU address bus 1
17 A2 MPU address bus 2
18 A3 MPU address bus 3
19 A4 MPU address bus 4
20 A5 MPU address bus 5
21 A6 MPU address bus 6
22 A7 MPU address bus 7
23 VDD +5V
24 VSS GND
25 VSS GND
26 A8 MPU address bus 8
27 A9 MPU address bus 9
28 A10 MPU address bus 10
29 A11 MPU address bus 11
30 A12 MPU address bus 12
31 A13 MPU address bus 13
32 N.C
33 N.C
34 VDD +5V
35 VSS GND
36 N.C
37 N.C
38 N.C
39 N.C
40 VSS GND
41 VSS GND
42 VDD +5V
43 D0 MPU data bus 0
44 D1 MPU data bus 1
45 D2 MPU data bus 2
46 D3 MPU data bus 3
47 D4 MPU data bus 4
48 D5 MPU data bus 5
49 D6 MPU data bus 6
50 D7 MPU data bus 7
51 VSS GND
52 VDD +5V
53 D8 MPU data bus 8
54 D9 MPU data bus 9
PinNo.
Name Description
55 D10 MPU data bus 10
56 D11 MPU data bus 11
57 D12 MPU data bus 12
58 D13 MPU data bus 13
59 D14 MPU data bus 14
60 D15 MPU data bus 15
61 LCDENB LCD (ON/OFF) control signal input
62 M LCD AC-conversion signal output
63 VDD +5V
64 VSS GND
65 VSS GND
66 CP Display data transfer clock
67 LP Display data clutch pulse
68 FLM FIRST LINE MARKER signal output
69 UD0 LCD display data bus 0
70 UD1 LCD display data bus 1
71 UD2 LCD display data bus 2
72 UD3 LCD display data bus 3
73 N.C
74 N.C
75 N.C
76 N.C
77 VDD +5V
78 OSC1 Oscillation input terminal
79 OSC2 Oscillation output terminal
80 VSS GND
3. ADDRESS MAP
1) TOTAL MEMORY SPACEThe address map of the total memory space is shown below. As youcan see, the memory space is divided into the following 5 blocks:
0page area (including the I/O area)
• VRAM
• RAM
• ROM
• Extended I/O area
2) 0PAGE AREAThe 0page area consists of four spaces: the ROM mapped area,internal and external I/O areas. The ROM mapped area has been devised for the following purposes:
Simplifying the procedure for booting the IPL program
Achieving high-speed accessing, and accessing by abbreviatedinstructions.
3) I/O AREASThe addresses from 00FF80h to 00FFFFh are called the internal I/Oarea.The internal I/O area is a space where the control registers andbuilt-in ports inside the CPU are addressed.The external I/O area is a space where the peripheral devices outsidethe CPU or devices on an optional card are addressed.
000000h0 page area
(64KB)00FFFFh
200000h
600000h
800000h
C00000hC20000h
F00000h
FFFFFFh
Extended I/O area
(1MB)
(2MB)
Flash
EXTEND RAM(4MB)
STD RAM (2MB)
(4MB)
VRAM (128KB)
EP-ROM
D00000h* The expanded I/O area means the space for the I/O device addressed in the area excluding the 0 page one. MPCA8 uses FFFF00h to FFFFFFh for the addressed register (BAR) of SSP. The I/O register for VGAC is included.
* In the 0 page area, lower 64KB or less of the flash area is mapped. By mapping the ROM area, the reset start and other vectors become addressable.
000000h
00FFFFh
00FF80h
00FE80hInternal I/O area
External I/O area
ROM mapping area
I/O area
* The ROM area 200000h to 20FFFFh (ROS1 lower 64KB) is mapped on the ROMmapping area.
* The internal I/O area is used for peripheral modules inside the CPU; the external I/O area is used for peripheral modules outside the CPU. For more information, refer to the H8/510 hardware manual and peripheral device specification.
00FE80h
00FF80h
00FFA0h
00FFB0h
00FFB4h
00FFB8h
00FFBCh
00FFC0h
00FFD0h
00FFE0h
00FFF0h
00FFFFh
Internal I/O area
MPCCS
MCR1Z
MCR2Z
OPCCS2
OPCCS1
T/PZ
OPTCSZ
Expanded MPC(not used)
MCR3Z
CPCSZ (not used)
TPRC1 * CPCSZ is CPC select for Centronics Interface.
* MPCCS and expanded MPC signals are base signals for MPCA9 internal register decode. There is no external signal.
* MCR1Z, MCR2Z and MCR3Z
* MCR1Z and MCR2Z are chip
are chip select signals for the magnet card reader. (Use lower 2bytes.)
* T/PZ is the internal decode signal for USART built in MPCA9. Thereis no external signal. (Use lower 2bytes.)
* OPCCS1 and OPCCS2 signals are decoded inside the OPC (OPTION PERIP- HERAL CONTROLLER) using the option decode signal OPTCS. There is no external signal.
TPRC1 is built in byMPCA9.
4) ROM SPACEFig.5 shows the ROM space. The UP-700 uses 2MB of NOR-typeflash memory instead of conventional ROM, so that the FROS1# fromthe MPCA9 is input into the chip enable of the flash memory.
5) VRAM & RAM SPACEThe VRAM is the display memory of the LCD.
6) EXTENDED I/O AREAThe addresses from F00000h to FFFFFFh are called an extended I/Oarea. The UP-700 uses the following addresses as the break addressregister (BAR) for SSP.
• FFFF00h ∼ FFFFFFh
4. LCD DISPLAY
The UP-700 uses a 320 x 240 dot monochromatic LCD for the maindisplay and VGAC (M66271) for the display controller which is con-nected to H8/510 in the ISA bus connection mode.
1) BLOCK DIAGRAMHere is the block diagram of the LCD and its allied components.
2) LCD PANEL The LCD panel uses a dot-matrix liquid crystal module with mono-chromatic STN and CCFT backlight. The resolution is 320 x 240.
3) DISPLAY CONTROLLERMatsushita VGAC (M66271) is used for the display controller.
VRAM is present on the address space of the CPU and it is possibleto write and read data from the CPU side through the lower 9600 byteaddress of 128 KB size in addresses C00000H ~ C1FFFFH.C00000H - C1FFFH:
4) LCD ON CONTROLThe LCD is turned on and off by controlling the bias power supply forthe LCD using the terminal LCDENB of the M66271.LCDENB is in low level when resetting. When bit 0 of the moderesistor of the M66271 by software is set to high level, the power issupplied to the LCD, thus turning on the LCD.
5) BACK LIGHT CONTROLThe backlight ON/OFF is controlled by the same LCDENB used forcontrolling the LCD ON mode.
6) LUMINANCE AND CONTRAST ADJUSTMENT• Luminance: Luminance is adjusted with an inverter which controls
the dimming function. (Fixed)
• Contrast: Contrast is adjusted by controlling the contrast adjust-ment voltage (VO) of the LCD.
5. CUSTOMER DISPLAY
The UP-700 can incorporate a UP-P16DP for the customer display.
6. SRAM (Standard)
The device is HYUNDAI 4MB SRAM (HY628400ALLT2-70 512K 8bit)with an access time of 70ns.
200000h
(MAX4MB)
ROS1
5FFFFF
* Lower 64KB of the ROS1 is mapped on the 0 page area.
* ROS1 is decoded by MPCA9.
600000h
C00000h
800000h
A00000h
CFFFFFh
RASPN1
VRAM
(2MB)
RASPN2
(4MB)
(1MB)
* All the decode signals in the area in the figure are supported by MPCA9.
* RAS1 signals from MPCA9 correspond to 2MB 600000h to 7FFFFFh.
* OPTION RAM board (2MB and 4MB) interfaces using RAS2 as the base signal.
* The actual VRAM is 128KB, but it is accessed by every 128KB of bank according to VGAC specification.
CPU H8/510 SD0-7 A0-13 RD#
RD#
HWR# LWR#
PHAI CLK
WAIT#
UD0-3 LD0-3
WAIT# LCD (320 x 240)
MPCA8 LP LP LCDWT FLM FP
VIO# IOCS# DCLK DCLK VMEM# MCS# VEE BACKLIGHT
M66271
M BIAS POWER
LCDENB
8bitMPU connection setting
HWR# : "H"
BHE# : "H"
MPUSEL : "L"
1) CPU INTERFACEThe figure below shows a typical pseudo SRAM interface in the UP-700.
2) SRAM ADDRESSStandard SRAM is decoded as follows by the RASPN1 signal.
780000h ∼ 7FFFFFh
The base signal is 2MB. It thus wraparounds with 600000H ∼7FFFFFH 1.5MB.
7. NOR-type FLASH MEMORY
Here is the explanation for the interface of NOR-type flash memory.The device is Sharp’s LH28F016SU flash memory which consists of512 K words × 16 or 1 MB × 8, with 32 blocks of 64 KB.
1) CPU INTERFACEThe figure below shows a typical interface for the LH28F016SU of theUP-700 system.
2) DEVICE CONTROLAfter resetting, the device automatically enters the array read modeand performs the same action as the usual ROM, thus requiring nospecial consideration when reading data.
Data can be written at a high speed by using the page buffer.
8. SSP CONTROL
The UP-700 uses flash memory in the place of EPROM, so it ispossible to rewrite the contents of the flash memory in changing theprogram. However, since the existing gate array MPCA8 is used, it isalso possible to use the conventional SSP.
1) OPERATIONLike the MPCA5 ~ 8, the MPCA9 adopts the break address registercomparison method for detecting addresses. The operation of thismethod is briefly explained below.
The gate array always compares the break address register (BAR)built in the gate array, with the address bus to monitor the addressbus.
If both agree, the gate array outputs the NMI signal to the CPU, whichin turn shifts from normal handling to exception handling.
In both the MPCA5 ~ 8 and the MPCA9, SSP is achieved by theabove operation.
The setting of the break address register (BAR) is directly written inthe addresses from FFFF00h to FFFFFFh.
9. INTERRUPT CONTROL
There are roughly two types of interrupts:
• Internal interrupts: Controlled inside the CPU
• External interrupts: Input into the CPU from outside
1) INTERNAL INTERRUPTSDevice interrupts built in the CPU are used for the following applica-tions:
Event factor ApplicationSC11 Interrupt source as RS232 : CH8SC12 Not used (SC1 is used for CKDC interface.)FRT1 (ICI)
(OCRA)(OCRB)(OVF)
INTMCR ∼ MCR interrupt (to FT11 terminal)
FRT2 (ICI) Standard SHEN event (for CKDC)(OCRA) Simple IRC timer event(OCRB) RS232 timer event(OVF) System timer (53 ms)
TMR (CMA)(CMB)(OVF)
WDT (OVF) Drawer open timerA/D Not usedNMI SSP request
2) EXTERNAL INTERRUPTSThe following types of external interrupts are available:• NMI (SSP)
• IRQ0 (Standard I/O interrupt)
• IRQ1 (RS232 interrupt)
• IRQ2 (Not Used)
• IRQ3 (Used as SCK terminal)
S RAM(Standard)A0~A18
A0~A18 A0~A21
D0~D7 D8~D15
/RD /RD MPCA9
/WR /HWR
/CE
S RAM(Option)A0~A18 RASPN2
74LV138A19~A21
A,B,CY
/G
/RESET
RASPN1
RESET-
5V
FVPON
NORDY
H8/510
DATA
RD-
PORT64
PORT63
MPCA8 FROS1-
WE#
OE#
CE0#
GND
VPP
CE1#
RP#
3/5#
VCC
BYTE#
RY/BY#
A0~A2
DQ0~DQ1
WP#
LH28F 016SUT
ADDRES
HWR-
10. WAIT CONTROL
The weight control function built in the MPCA9 is used to provide aninterface with low-speed devices.
1) BLOCK DIAGRAMThe block diagram of the wait control function is shown.
In the figure, the decoder, wait enabling register, AND-OR sectionsare the same as those in the MPCA6 or 7, but other components arenewly incorporated in the MPCA5.
EXWAITZ and WAITZ are external weight signals which are to beORed inside the MPCA9 and output to the WAITZ. The EXWAITZ is ageneral-purpose wait request terminal, and WAITZ is the wait requestsignal from the VGA controller.
11. CKDC9
The UP-700 uses one CKDC9 for the CKDC PWB and one CKDC9for the POLE display (option) to carry out the following control opera-tions.
CKDC PWB CKDC9:
• Clock (second data readable)
• Buzzer
• System reset
• Key/Clerk switch
POLE DISPLAY PWB (UP-P16DP)
• Customer display tube
1) INTERFACEThe CKDC9 is connected through the MPCA8.
Selector
/AS
CLK WAIT RESET Counter
START
/RESET
/EXWAIT
/VWAIT/LCDWAIT
/WAITZ
φ
WAITenable
ForRASP-
/RESET for 1,2,3WAIT
WAITenable
ForMISC
WAITCount
ForRASP
D
/QSelector Selector
/RESET /RESETfor 1WAIT
/RESETWAITCount
ForMISC
WAITCount
ForRASPN
WAITCount
ForRASPN
D
/Q
D
/Q
WAITenable
ForVRAM
•VGAI/O
D
/Q
Terminal autoweight signal
TXD2(P87)SCK2(P83)RXD2(P84)
TXDISCKIRXDI
H8/510 MPCA8
INT1
IRQ0IRQ0
RES
STOP(P57)
RESET
RESET
STH
HTSSCK
CKDC9KRQSHEN
STOP
HTS2SCK2STH2
HTSSCKSTH
SRESRESET SW
FTI2
CKDC9
HTS1SCK1STH1
HTSSCKSTH
INT4 SHENRESET reset from MAIN
VFDCVFD
UP-P16DP
Key
Buzzer
12. OPTION RAM INTERFACE
1) INTERFACEThe expanded RAM connector terminals are shown in the table below.
The 40-pin RAM is used for the connector.
Extension RAM connector terminals
Signal Name Pin No. Pin No. Signal Name
+5V 1 2 N.C.
HWR 3 4 N.C.
GND 5 6 A21
A20 7 8 A19
A18 9 10 A17
A16 11 12 A15
A14 13 14 A13
A12 15 16 A11
A10 17 18 A9
A8 19 20 A7
A6 21 22 A5
A4 23 24 A3
A2 25 26 A1
A0 27 28 RD
D7 29 30 D6
D5 31 32 D4
D3 33 34 D2
D1 35 36 D0
RASPN2 37 38 VCKDC
GND 39 40 GND
13. RESET SEQUENCE
The reset sequence block diagram is shown below. Note that theRESET signal (system reset) and CKDCR signal (CKDC reset) aredifferent from each other.
1) POWER ON/OFFThe flow of signal processing at the time of the power supply turningOn/Off is as follows:
Table 19<Power OFF>
Power supply MPCA9 CPU CKDC9
1 POFF L
2 IRQ0 L
3 STOP L
4RESET L
(System reset)
Table 20<Power ON>
Power supply MPCA9 CPU CKDC9
1 POFF H
2 STOP H
3RESET H
(System reset)
The table below shows the timing chart.
14. DRAWER
The UP-700 can use up to 2 optional external drawers.
1) DRAWER SOLENOID DRIVEP34 ∼ P37 inside the CPU are allocated for the port output of thedrawer solenoid drive.
Built-in port Signal name Remarks
P34 DR0 Drawer 1 (optional drawer)
P35 DR1 Drawer 2 (optional drawer)
P36 DR2 Reserved
P37 DR3 Reserved
One port corresponds to one drawer. If a power failure is detected,the drawer solenoid drive must be stopped as soon as possible.
The drawer solenoid drive time must be controlled in the range of40 ms to 50 ms by the timer.
2) DRAWER OPEN/CLOSE SENSEThe drawer open/close sense signal is input into the built-in port ofthe CPU. The sense signal of an optional drawer sensor is also wiredORed before inputting.
• P33=1: Any of the drawers is open.
POFF
CKDCR (CKDC reset)
VCC
POFF
INT0 IRQ0
STOP
RESET (System reset)
SLIDE SW
CKDC9
MPCA9
POWER SUPPLY
CPU
PG GOOD
RESET
STOP
SHEN
SCK
+5V,+12V
(POFF)
10ms MIN
8 PULSE
(System)
Power supply On Power supply Off
15. TCP/IP STACK
The LAN of the UP-700 uses as the protocol Ethernet, which supportsTCP/IP.
The interface with the TCP/IP board is achieved through 2 interruptsignals and dual-port RAM.
The decode of dual-port RAM is located in the following space:
DP-RAM: F20000H - F2FFFFH (max. 64 KB)
The interruption from the TCP/IP is allocated as follows:
EXINTO: INTSW (SLAVE WRITE interrupt) bit 6 of 00FF81H
EXINT1: INTSR (SLAVE READ interrupt) bit 0 of 00FF80H
<TCP/IP connector terminals>
Signal Name Pin No. Pin No. Signal Name+5V 2 1 +5V+5V 4 3 +5VA14 6 5 A15A12 8 7 A13
HWR 10 9 DPCSA10 12 11 A11A0 14 13 RDA2 16 15 A1A4 18 17 A3A6 20 19 A5A8 22 21 A7D7 24 23 A9D5 26 25 D6D3 28 27 D4D1 30 29 D2
LRES 32 31 D0INTSW 34 33 INTSR
- 36 35 -GND 38 37 GNDGND 40 39 GND
16. RS232
Two standard RS232 channels are compatible with the ER-A5RS.However, while the ER-A5RS uses the IRQ2 terminal of the CPU forinterruption of the RS232, the UP-700 cannot use the IRQ1 terminalinstead of it. (The IRQ2 terminal is used for IR as the SCK1 terminal.)The standard RS232 is fixed to the logic channels 1 and 8. Use thechannels 2, 3, 4, 5, 6 and 7 for the ER-A5RS.
17. MCR
This paragraph describes the MCR option (UP-E13MR) control de-fined by the UP-700 hardware architecture.3 channels of the serial port (interchangeable with 8251) built in theMPCA9 are used. 3 tracks of data are read simultaneously. (UP-E13MR)
1) CPU INTERFACEThe CPU interface for the USART (8251) and magnetic card reader(MCM-21) in the UP-700 system is shown below.
Signal description
RCP1 TRACK 1 CLOCK PULSERDD1 TRACK 1 DATA SIGNALRCP2 TRACK 2 CLOCK PULSERDD2 TRACK 2 DATA SIGNALRCP3 TRACK 3 CLOCK PULSERCD3 TRACK 3 DATA SIGNALCLS1 TRACK 1 CARD DETECTION SIGNALCLS2 TRACK 2 CARD DETECTION SIGNALCLS3 TRACK 3 CARD DETECTION SIGNALRCVRDY1 TRACK 1 DATA RECEIVING SIGNALRCVRDY2 TRACK 2 DATA RECEIVING SIGNALRCVRDY3 TRACK 3 DATA RECEIVING SIGNALINTMCR INTERRUPT SIGNAL OR-SYNTHESIZED from
RCVRDY and SYNC input
2 chip select signals for the 8251 are generated inside MPCA8.
2) MCR INTERFACEThe operating timing of the MCR interface signals is given below.
(1) Example of timing
(2) Detailed timing (relation between DATA and CLOCK PULSE)
The "NULL" CODE is basically written prior to the opening code. Theopening code detection algorithm is considered because data maybecome corrupt before and after the CARD detection signal due to aworn magnet stripe.
CPU
ICI INTMCR
RCVRDY1
RCVCLK2
RDD1
RCP2
RDD2
CLS1
RCVDT1
RCP1
/DSR1
CLS2
RCVDT2
8251 x 2
Integrated as MPCA8 in the UP-700 system.
RCVCLK1
/DSR2
CLS1, CLS2
RCVRDY1
RCVRDY2
INTMCR
SYNC
MPCA7
RCP1
CLS2
RCVRDY3
RCVRDY2
RDD3 RCVDT3
/DSR3
RCVCLK3
CLS3
RCP3
RDD1/RDD2
RCP1/RCP2
CLS1/CLS2
RDD3
RCP3
CLS3
"0" "1" "1"
Approx. 16µ s Min. 5µs
RDD1/RDD2
RCP1/RCP2
RDD3
RCP3
CHAPTER 7. TCP/IP I/F PWB DESCRIPTION
1. GENERAL DESCRIPTION
This control board is an Ethernet board that supports the TCP/IPprotocol.
2. BLOCK DIAGRAM
When writing data into FLASH, switch /CS0to EP-ROM and /CS3to FLASH Memory.
3. CONFIGURATION
CPU :[HitachiSH-2 Series SH7014 (20MHz)]
As external memory spaces, CS0 - CS3 and DRAM space are pro-vided. This board assigns FLASH Memory to CS0, SRAM to CS1,dual-port SRAM to CS2, and LAN controller to CS3.
LAN Controller : [RealtekRTL8019AS(20MHz)]LAN controller is assigned to CS space.
Because of pseudo ISA connection, each register is assigned to ad-dresses of H00C00300 and after.
ROM(FLASH Memory) :[SharpLH28F004BVT(4Mbits)] <Access Time = 90ns>
ROM (FLASH Memory) is assigned to CS0 space.
Data is written onto FLASH Memory from UV-EPROM by switchingthe CSO space to UV-EPROM and the CS3 space to FALSH Mem-ory.
MAC Address is written on FLASH Memory.
• Company code is assigned to "08001FH".
• The serial number and adjustment byte are stored in an area of 4bytes from the address H’0007C000.<The serial number is acquired according to Sharp’s in-housespecification(SS).>
RAM : [S-RAM 1Mbits] <Access Time=70ns>
Assigned to CS1 space.
[IDT Dual-Port SRAM IDT7134]<Access Time=55ns>Assigned to CS2 space.
The IDT7134 does not have any LOGICiBusy or Semaphorej, accessto the same address from both sides is inhibited.
Pulse Trans : [Pulse78Z034]It is used for the 10Base-T standard and has a choke coil built in atthe output side.
Dual-Port
RAM
4k byte
CN
RJ-45
Data Bus
Address B
us
Data B
us
LOGIC
/CS1
/CS2
/INTHR
/INTHW
/INTSR
/INTSW
10MHz
/CS0
/CS0/CS3
/CS3
/CS2
/CS1
/CS0
/HWACK
/HRACK
/SWRQ
/SRRQ
CPU (SH-2)
/DPCS, /WR,/RD
Address Bus LD0~LD7
LA0~LA11
FLASH 512k byte
LD0~LD7
LA0~LA18
LD0~LD7
LA0~LA18
SRAM 128k byte
LD0~LD7
LA0~LA19
LD0~LD7
LA0~LA18
LAN Cnt.(8bit-Bus)
EP-ROM(Writing into FLASH)512k byte
4. MAIN LSI DESCRIPTION
1) CPU (SH7014)
1)-1. SH7014 OverviewThe SH7014 CMOS single-chip microprocessors integrate a Hitachi-original architecture, high-speed CPU with peripheral functions re-quired for system configuration.
The CPU has a RISC-type instruction set. Most instructions can beexecuted in one clock cycle, which greatly improves instruction exe-cution speed. In addition, the 32-bit internal-bus architecture en-hances data processing power. With this CPU, it has become possi-ble to assemble low cost, high performance/high-functioning systems,even for applications that were previously impossible with microproc-essors, such as real-time control, which demands high speeds. Inparticular, the SH7040 series has a 1-kbyte on-chip cache, whichallows an improvement in CPU performance during external memoryaccess.
In addition, this LSI includes on-chip peripheral functions necessaryfor system configuration, such as large-capacity ROM (except theSH7014, which is ROMless) and RAM, timers, a serial communica-tion interface (SCI), an A/D converter, an interrupt controller, and I/Oports. Memory or peripheral LSIs can be connected efficiently with anexternal memory access support function.This greatly reduces system cost.
1)-1-1. SH7014 FeaturesCPU:
• Original Hitachi architecture
• 32-bit internal data bus
• General-register machine
– Sixteen 32-bit general registers
– Three 32-bit control registers
– Four 32-bit system registers
• RISC-type instruction set
– Instruction length: 16-bit fixed length for improved code effi-ciency
– Load-store architecture (basic operations are executed be-tween registers)
– Delayed branch instructions reduce pipeline disruption duringbranch
– Instruction set based on C language
• Instruction execution time: one instruction/cycle (35 ns/instructionat 28.7-MHz operation)
• Address space: Architecture supports 4 Gbytes
• On-chip multiplier: multiplication operations (32 bits x 32 bits 64bits) and multiplication/accumulation operations (32 bits x 32 bits +64 bits 64 bits) executed in two to four cycles
• Five-stage pipeline
Cache Memory:
• 1-kbyte instruction cache
• Caching of instruction codes and PC relative read data
• 4-byte line length (1 longword: 2 instruction lengths)
• 256 entry cache tags
• Direct map method
• On-chip RAM, and on-chip I/O areas not objects of cache
• Used in common with on-chip RAM; 2 kbytes of on-chip RAM usedas address array/data array when cache is enabled
Interrupt Controller (INTC):
• Seven external interrupt pins (NMI, IRQ x 6)
• Twenty-eight internal interrupt sources
• Sixteen programmable priority levels
Bus State Controller (BSC):
• Supports external extended memory access
– 8-bit, or 16-bit external data bus
• Memory address space divided into five areas (four areas ofSRAM space, one area of DRAM space) with the following settablefeatures:
– Number of wait cycles
– Outputs chip-select signals for each area
– During DRAM space access:
• Outputs RAS and CAS signals for DRAM
• Can generate a RAS precharge time assurance Tp cycle
• DRAM burst access function
– Supports high-speed access mode for DRAM
• DRAM refresh function
– Programmable refresh interval
– Supports CAS-before-RAS refresh and self-refresh modes
• Wait cycles can be inserted using an external WAIT signal
• Address data multiplex I/O devices can be accessed
Note: No bus release
Direct Memory Access Controller (DMAC) (2 Channels):
• Supports cycle-steal and burst transfers
• Supports single address mode and dual address mode transfers
• Priority order: fixed at channel 0 > channel 1
• Transfer counter: 16 bits
• Transfer request sources: external DREQ input, auto-request, andon-chip supporting modules
• Address space: 4 Gbytes
• Choice of 8-, 16-, or 32-bit transfer data size
Multifunction Timer/Pulse Unit (MTU) (3 Channels):
• Maximum 8 types of waveform output or maximum 16 types ofpulse I/O processing possible based on 16-bit timer, 3 channels
• 8 dual-use output compare/input capture registers
• 8 independent comparators
• 8 types of counter input clock
• Input capture function
• Pulse output mode
– One shot, toggle, PWM
>>>>> USE FONT <<<<<
Helvetica/ Helvetica-Condensed/ Century-Schoolbook/ Symbol & OriginalFonts: (RingWorld2/RingFont2/Pa
Symbol/PartsCod)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
• Phase calculation mode
– 2-phase encoder calculation processing
Compare Match Timer (CMT) (Two Channels):
• 16-bit free-running counter
• One compare register
• Generates an interrupt request upon compare match
Watchdog Timer (WDT) (One Channel):
• Watchdog timer or interval timer
• Count overflow can generate an internal reset, external signal, orinterrupt
Serial Communication Interface (SCI) (Two Channels):
(Per Channel):
• Asynchronous or clock-synchronous mode is selectable
• Can transmit and receive simultaneously (full duplex)
• On-chip dedicated baud rate generator
• Multiprocessor communication function
I/O Ports:
• SH7014
– Input/output: 35
– Input: 8
– Total: 43
A/D Converter:
• 10 bits 8 channels
• The SH7014 has a high-speed A/D converter.
On-Chip Memory:
• ROM
– SH7014: ROMless
• RAM: SH7014: 3 kbytes (1 kbyte when cache is used)
Operating Modes:
• Operating modes
– Non-extended ROM mode
• Processing states
– Program execution state
– Exception processing state
• Power-down modes
– Sleep mode
– Software standby mode
Clock Pulse Generator (CPG):
• On-chip clock pulse generator
– On-chip clock-doubling PLL circuit
1)-2. Block DiagramFigure 1. is a block diagram of the SH7014.
1)-3. Pin Arrangement and Pin Functions
1)-3-1. Pin ArrangmentFigure 2. shows the pin arrangement for the SH7014 (top view).
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MD3MD2MD1MD0NMI
EXTALXTAL
VCC
VCC
VCC
PLLVCC
PLLCAP
PLLVSS
VCCVCCVSSVSSVSSVSSVSSVSSVSSVSS
AVCCAVSS
RES WDTOVR
PB
9/IR
Q7/
A21
PB
8/IR
Q6/
A20
/WA
IT
PB
7/A
19
PB
6/A
18
PB
5/IR
Q3/
RD
WR
PB
4/IR
Q2/
CA
SH
PB
3/IR
Q1/
CA
SL
PB
2/IR
Q0/
RA
S
A17
A16
PA
15/C
K
RD
WR
H
WR
L
CS
1
CS
0
PA
9/T
CLK
D/IR
Q3
PA
8/T
CLK
C/IR
Q2
PA
7/T
CLK
B/C
S3
PA
6/T
CLK
A/C
S2
PA
5/S
CK
1/D
RE
Q1/
IRQ
1
PA
4/T
XD
1
PA
3/R
XD
1
PA
2/S
CK
0/D
RE
Q0/
IRQ
0
PA
1/T
XD
0
PA
0/R
XD
0
PE
15/D
AC
K1
PE
14/D
AC
K0/
AH
PE
13
PE
12
PE
11
PE
10
PE
9
PE
8
PE
7/T
IOC
2B
PE
6/T
IOC
2A
PE
5/T
IOC
1B
PE
4/T
IOC
1A
PE
3/T
IOC
0D/D
RA
K1
PE
2/T
IOC
0C/D
RE
Q1
PE
1/T
IOC
0B/D
RA
K0
PE
0/T
IOC
0A/D
RE
Q0
: Peripheral address bus
: Peripheral data bus
: Internal address bus: Internal upper data bus: Internal lower data bus
PLL
PF
7/A
N7
PF
6/A
N6
PF
5/A
N5
PF
4/A
N4
PF
3/A
N3
PF
2/A
N2
PF
1/A
N1
PF
0/A
N0
RAM (3 kB)/ cache (1 kB)
CPUDirect memory
access controller
Interruptcontroller
Bus state controller
Serial communi-cation interface(• 2 channels)
Multifunction timer/pulse unit
Compare matchtimer (• 2 channels)
A/Dconverter
Watch-dog
timerVSSVSSVSS
Figure 1. Block Diagram of the SH7014
PB13PE12PE11
VSS
PE10PE9PE8
PE7/TIOC2BPE6/TIOC2A
VCC
PE5/TIOC1BVSS
AVCC
PF7/AN7PF6/AN6
AVSS
PF5/AN5PF4/AN4PF3/AN3PF2/AN2PF1/AN1PF0/AN0
VSS
PE4/TIOC1APE3/TIOC0D/DRAK1PE2/TIOC0C/DREQ1PE1/TIOC0B/DRAK0PE0/TIOC0A/DREQ0 56
555453525150494847464544434241403938373635343332313029
858687888990919293949596979899100101102103104105106107108109110111112 PB6/A18
PB7/A19PB8/IRQ6/A20/WAITPB9/IRQ7/A21
VSSRDWDTOVFWRHVCCWRL
VSS
CS0PA9/TCLKD/IRQ3
PA7/TCLKB/CS3PA6/TCLKA/CS2PA5/SCK1/DREQ1/IRQ1PA4/TXD1PA3/RXD1PA2/SCK0/DREQ0/IRQ0PA1/TXD0PA0/RXD0D15D14D13VSS
D12
RE
SP
A15
/CK
PLL
VS
SP
LLC
AP
PLL
VC
CM
D0
MD
1V
CC
NM
IM
D2
EX
TA
LM
D3
XT
AL
VS
SD
0D
1D
2D
3D
4V
CC
D5
D6
D7
VS
SD
8D
9D
10D
11
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
CS1
PA8/TCLKC/IRQ2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
PE
14/D
AC
K0/
AH
PE
15/D
AC
K1
VS
SA
0A
1A
2A
3A
4A
5A
6A
7
A11
A12
A13
A14
A15
A16
VC
CA
17
PB
2/IR
Q0/
RA
SP
B3/
IRQ
1/C
AS
LP
B4/
IRQ
2/C
AS
HV
SS
PB
5/IR
Q3/
RD
WRA8
A9
A10
VS
S
QFP-112
Figure 2. SH7014 Pin Arrangement (QFP-112 Top View)
CPU
No. CPUSignalname
I/O Remarks
1 PE14 PE14 I N.U. (GND)2 PE15 /WP I FLASH write Status3 Vss GND4 A0 LA0 O Address Bus5 A1 LA1 O6 A2 LA2 O7 A3 LA3 O8 A4 LA4 O9 A5 LA5 O10 A6 LA6 O11 A7 LA7 O12 A8 LA8 O13 A9 LA9 O14 A10 LA10 O15 A11 LA11 O16 A12 LA12 O17 A13 LA13 O18 A14 LA14 O19 A15 LA15 O20 A16 LA16 O21 Vcc +5V22 A17 LA17 O Address Bus23 Vss GND24 /IRQ0 /INTHW I Host write end interrupt25 /IRQ1 /INTHR I Host write end interrupt 26 /IRQ2 /INTLAN I Interrupt from LANC27 Vss GND28 /IRQ3 /IRQ3 I N.U. (+5V)29 A18 LA18 O Address Bus30 A19 LA19 O Address Bus31 /WAIT IOCHRDY I Wait from LANC32 PB9 PB9 I N.U. (GND)33 Vss GND34 /RD /MRD O Memory Read35 /WDTOVF /WDTOVF O N.U. (OPEN)36 /WRH /WRH O N.U. (OPEN)37 Vcc +5V38 /WRL /MWE O Memory Write39 Vss GND40 /CS1 /CS1 O SRAM Chip Select41 /CS0 /CS0 O FLASH Chip Select42 PA9 PA9 I N.U. (GND)43 PA8 PA8 I N.U. (GND)44 /CS3 /CS3 O LANC Chip Select45 /CS2 /CS2 O DP-RAM Chip Select46 PA5 PA5 I N.U. (GND)47 PA4 PA4 I N.U. (GND)48 PA3 PA3 I N.U. (GND)49 PA2 PA2 I N.U. (GND)50 PA1 PA1 I N.U. (GND)51 PA0 PA0 I N.U. (GND)52 D15 HD15 I/O N.U. (Pull-Down)53 D14 HD14 I/O N.U. (Pull-Down)54 D13 HD13 I/O N.U. (Pull-Down)55 Vss GND56 D12 HD12 I/O N.U. (Pull-Down)57 D11 HD11 I/O N.U. (Pull-Down)58 D10 HD10 I/O N.U. (Pull-Down)59 D9 HD9 I/O N.U. (Pull-Down)60 D8 HD8 I/O N.U. (Pull-Down)
No. CPUSignalname
I/O Remarks
61 Vss GND62 D7 HD7 I/O DATA Bus63 D6 HD6 I/O64 D5 HD5 I/O65 Vcc +5V66 D4 HD4 I/O DATA Bus67 D3 HD3 I/O68 D2 HD2 I/O69 D1 HD1 I/O70 D0 HD0 I/O71 Vss GND72 XTAL XTAL O Oscillator connection terminal73 MD3 MD3 I Mode terminal74 EXTAL EXTAL I Oscillator connection terminal75 MD2 MD2 I Mode terminal 276 NMI NMI I N.U. (+5V)77 Vcc +5V78 MD1 MD1 I Mode terminal 179 MD0 MD0 I Mode terminal 080 PLLVcc PLLVcc81 PLLCAP PLLCAP82 PLLVss PLLVss83 PA15 PA15 I N.U.(Pull-Down)84 /RES /LRES I Hardware Reset85 PE0 PE0 I N.U. (GND)86 PE1 PE1 I N.U. (GND)87 PE2 PE2 I N.U. (GND)88 PE3 PE3 I N.U. (GND)89 PE4 PE4 I N.U. (GND)90 Vss GND91 PF0 PF0 I N.U. (GND)92 PF1 PF1 I N.U. (GND)93 PF2 PF2 I N.U. (GND)94 PF3 PF3 I N.U. (GND)95 PF4 PF4 I N.U. (GND)96 PF5 PF5 I N.U. (GND)97 AVss GND98 PF6 PF6 I N.U. (GND)99 PF7 PF7 I N.U. (GND)
100 AVcc +5V101 Vss GND102 PE5 PE5 I N.U. (GND)103 Vcc +5V104 PE6 PE6 I N.U. (GND)105 PE7 PE7 I N.U. (GND)106 PE8 /SRRQ O Slave read end request107 PE9 /SWRQ O Slave write end request108 PE10 /HRACK O Host read interrupt cancel109 Vss GND110 PE11 /HWACK O Host write interrupt cancel 111 PE12 PE12 O N.U. (OPEN)112 PE13 /RSTDRV O Soft Reset for LANC
Note: Signals prefixed with a slash "/" are active in low level.
2) LAN CONTROLLER (RTL8019AS)
2)-1. Features:• 100-pin PQFP
• Supports PnP auto detect mode
• Compliant to Ethernet II and IEEE802.3 10Base5, 10Base2,10BaseT
• Software compatible with NE2000 on both 8 and 16-bit slots
• Supports both jumper and jumperless modes
• Supports Microsofts Plug and Play configuration for jumperlessmode
• Supports Full-Duplex Ethernet function to double channel band-width
• Supports three level power down modes:
– Sleep
– Power down with internal clock running
– Power down with internal clock halted
• Built-in data prefetch function to improve performance
• Supports UTP, AUI & BNC auto-detect
• Supports auto polarity correction for 10BaseT
• Supports 8 IRQ lines
• Supports 16 I/O base address options
--- and extra I/O address fully decode mode
• Supports 16K, 32K, 64K and 16K-page mode access to BROM (upto 256 pages with 16K bytes/page)
• Supports BROM disable command to release memory after remoteboot
• Supports flash memory read/write
• 16k byte SRAM built in
• Uses a 9346 (64*16-bit EEPROM) to store resource configurationsand ID parameters
• Capable of programming blank 9346 on board for manufacturingconvenience
• Support 4 diagnostic LED pins with programmable outputs
2)-2. General DescriptionThe RTL8019AS is a highly integrated Ethernet Controller which of-fers a simple solution to implement a Plug and Play NE2000 compat-ible adapter with full-duplex and power down features.
With the three level power down control features, the RTL8019AS ismade to be an ideal choice of the network device for a GREEN PCsystem. The full-duplex function enables simultaneously transmissionand reception on the twisted-pair link to a full-duplex Ethernet switch-ing hub. This feature not only increases the channel bandwidth from10 to 20 Mbps but also avoids the performance degrading problemdue to the channel contention characteristics of the EthernetCSMA/CD protocol.
The RTL8019AS provides the auto-detect capability between the inte-grated 10BaseT transceiver, BNC and AUI interface. Besides, the10BaseT transceiver can automatically correct the polarity error on itsreceiving pair.
The RTL8019AS is built in with 16K-byte SRAM in a single chip. It isdesigned not only to provide more friendly functions but also to savethe effort of SRAM sourcing and inventory.
2)-3. Pin Configuration
LAN Controller
No. CPUSignalname
I/O Remarks
1 INT3 INT3 O N.U. (Pull-Down)2 INT2 INT2 O N.U. (Pull-Down)3 INT1 INT1 O N.U. (Pull-Down)4 INT0 /INTLAN O Interrupt to CPU5 SA0 LA0 I Address Bus6 VDD +5V7 SA1 LA1 I Address Bus8 SA2 LA2 I9 SA3 LA3 I10 SA4 LA4 I11 SA5 LA5 I12 SA6 LA6 I13 SA7 LA7 I14 GND GND15 SA8 LA8 I Address Bus16 SA9 LA9 I17 VDD +5V18 SA10 LA10 I Address Bus19 SA11 LA11 I20 SA12 LA12 I21 SA13 LA13 I22 SA14 LA14 I23 SA15 LA15 I24 SA16 LA16 I25 SA17 LA17 I26 SA18 LA18 I27 SA19 LA19 I28 GND GND29 IORB /MRD I Memory Read
81 BD3 [IOS0]
82 BD2 [IOS1] 83 GND
84 BD1 [IOS2]85 BD0 [IOS3]86 GND87 SD15
89 VDD90 SD1391 SD1292 SD1193 SD1094 SD995 SD896 IOCS16B [SLOT16]
97 INT7 [IRQ15]98 INT6 [IRQ12]99 INT5 [IRQ11]100 INT4 [IRQ10]
88 SD14
2 INT2 [IRQ4]3 INT1 [IRQ3]4 INT0 [IRQ2/9]5 SA06 VDD7 SA18 SA29 SA310 SA411 SA512 SA613 SA714 GND15 SA8
29 IORB28 GND27 SA1926 SA1825 SA1724 SA1623 SA1522 SA1421 SA1320 SA12
30 IOWB
19 SA1118 SA1017 VDD16 SA9
64 AUI63 LED2 [LED_TX]62 LED1 [LED_RX] [LED_CRS]61 LED0 [LED_COL] [LED_LINK]
60 LEDBNC59 TPIN+58 TPIN-57 VDD56 RX+55 RX-54 CD+53 CD-52 GND51 X2
69 BA18 [BS2]70 VDD71 BA17 [BS3]72 BA16 [BS4]
73 BA1574 BA14 [PL0]75 BCSB76 EECS77 BD7 [PL1][EEDO]78 BD6 [IRQS0][EEDI]79 BD5 [IRQS1][EESK]80 BD4 [IRQS2]
RTL8019AS
1 INT3 [IRQ5]
68 BA19 [BS1]67 BA20 [BS0]66 BA21 [PNP]
50 X149 TX+48 TX-47 VDD46 TPOUT-45 TPOUT+44 GND43 SD742 SD6
39 SD338 SD237 SD136 SD0
34 AEN33 RSTDRV32 SMEMWB31 SMEMRB
41 SD540 SD4
35 IOCHRDY
65 JP
No. CPUSignalname
I/O Remarks
30 IOWB /MWE I Memory Write31 SMEMRB SMEMRB I N.U. (Pull-Up)32 SMEMWB SMEMWB I N.U. (Pull-Up)33 RSTDRV RSTDRV I Hardware Reset34 AEN /CS3 I Chip Select35 IOCHRDY /WAIT O Wait to CPU36 SD0 LD0 I/O DATA Bus37 SD1 LD1 I/O38 SD2 LD2 I/O39 SD3 LD3 I/O40 SD4 LD4 I/O41 SD5 LD5 I/O42 SD6 LD6 I/O43 SD7 LD7 I/O44 GND GND45 TPOUT+ TPOUT+ O 10Base-T output +46 TPOUT- TPOUT- O 10Base-T output -47 VDD +5V48 TX- TX- O N.U. (Pull-Down)49 TX+ TX+ O N.U. (Pull-Down)50 X1 X1 I Oscillator connection terminal51 X2 X2 O Oscillator connection terminal52 GND GND53 CD- CD- I N.U. (OPEN)54 CD+ CD+ I N.U. (OPEN)55 RX- RX- I N.U. (OPEN)56 RX+ RX+ I N.U. (OPEN)57 VDD +5V58 TPN- TPIN- I 10Base-T input -59 TPN+ TPIN+ I 10Base-T input +60 LEDBNC LEDBNC O N.U. (OPEN)61 LED0 LED0 O N.U. (OPEN)62 LED1 LED1 O N.U. (OPEN)63 LED2 LED2 O N.U. (OPEN)64 AUI AUI I GND65 JP JP I Pull-Up66 PNP PNP I OPEN67 BS0 BS0 I OPEN68 BS1 BS1 I OPEN69 BS2 BS2 I OPEN70 VDD +5V71 BS3 BS3 I OPEN72 BS4 BS4 I OPEN73 BA15 BA15 O N.U. (OPEN)74 PL0 PL0 I OPEN75 BCSB BCSB O N.U. (OPEN)76 EECS EECS O N.U. (OPEN)77 PL1 PL1 I OPEN78 IRQS0 IRQS0 I OPEN79 IRQS1 IRQS1 I OPEN80 IRQS2 IRQS2 I OPEN81 IOS0 IOS0 I OPEN82 IOS1 IOS1 I OPEN83 GND GND84 IOS2 IOS2 I OPEN85 IOS3 IOS3 I OPEN86 GND GND87 SD15 SD15 I/O N.U. (Pull-Down)
88 SD14 SD14 I/O N.U. (Pull-Down)89 VDD +5V90 SD13 SD13 I/O N.U. (Pull-Down)91 SD12 SD12 I/O N.U. (Pull-Down)92 SD11 SD11 I/O N.U. (Pull-Down)
No. CPUSignalname
I/O Remarks
93 SD10 SD10 I/O N.U. (Pull-Down)94 SD9 SD9 I/O N.U. (Pull-Down)95 SD8 SD8 I/O N.U. (Pull-Down)96 SLOT16 SLOT16 I Pull-Down97 INT7 INT7 O N.U. (Pull-Down)98 INT6 INT6 O N.U. (Pull-Down)99 INT5 INT5 O N.U. (Pull-Down)
100 INT4 INT4 O N.U. (Pull-Down)
Note: Signals suffixed with the letter "B" are active in low level.
5. MEMORY MAP
Flash
SRAM
CS0 SPACE
CS1 SPACE
CS2 SPACE
CS3 SPACE
Dual-Port SRAM
LAN Controller
H'FFFFFFFF
H'FFFFF000
H'FFFF8800
H'FFFF8000
H'02000000
H'01000000
H'00C*****
H'00C00000
H'00800FFF
H'00800000
H'00407FFF
H'00400000
H'0007FFFF
H'00000000
DRAMS space
Reserved
Reserved
Built-in peripheral
Module
Built-in RAM
2 The CS1 space is a physicalspace of 4 MB. Is uses LA0~LA14alone and thus LAP AROUNDoccurs. The data bus size is 8 bits.
1 The CS0 space is a physicalof 4 MB. It uses LA0~LA16alone and thus LAP AROUNDoccurs.In addition, the data bus size isset to 8 bits using the operationmode setting terminal of the CPU.
3 The CS2 space is a physicalspace of 4 MB. It uses LA0~LA11alone and thus LAPAROUND occurs. The data bus size is 8 bits.
4 The CS3 space is a physicalspace of 4 MB. Is uses LA0~LA19alone and thus LAP AROUNDoccurs.The data bus size of the LANcontroller is fixed to 8 bits.
6. INTERFACE WITH HOST CPU
1) SIGNAL LINESThe following signal lines are required for the interface with the host CPU.
Signal name I/O Description Connected to Connection pin
A0~A11 I Address Bus from host CPU DP-RAM A0R~A11R
D0~D7 I/O Data Bus from host CPU DP-RAM D0R~D7R
/RD I Read signal from host CPU DP-RAM /OER
/WR I Write signal from host CPU DP-RAM R/WR
/DPCS I Chip select from host CPU DP-RAM /CER
/LRES I Rest signal for this board from host CPU Board CPU /RES
/INTSR O Data read end interrupt from board CPU LOGIC
/INTSW O Data write end interrupt from board CPU LOGIC
A13~A15 I Address bus from host CPU (for decode) LOGIC
Vcc Power(+5V)
GND GND
Signals prefixed with a slash "/" are active in low level.
Cautions to be taken when designing the host side1. It is preferable that /LRES signal to be input into the board can
also be controlled by software.
2. The access timing satisfies the dual-port SRAM specification.
• Timing Waveform of Read Cycle No. 1, Either Side (1,2,4)
• Timing Waveform of Read Cycle No. 2, Either Side (1,3)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH.
4. Start of valid data depends on which timing becomes effective,tAOE, tACE or tAA
5. tAA for RAM Address Access and tSAA for Semaphore AddressAccess.
• Timing Waveform of Write Cycle No. 1, R/W Controlled Timing (1,5,8)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE =VIL andR/W = VIL.
3. tWR is measured from the earlier of CE or R/W going to VIH tothe end-of-write cycle.
4. During this period, the I/O pins are in the output state, and inputsignals must not be applied.
5. If the CE = VIL transition occurs simultaneously with or after theR/W = VIL transition, the outputs remain in the High-impedancestate.
6. Timing depends on which enable signal (CE or R/W) is assertedlast.
7. This parameter is guaranteed by device characterization, but isnot production tested. Transition is measured 500mV fromsteady state with the Output Test Load (Figure 2).
8. If OE = VIL during a R/W controlled write cycle, the write pulsewidth must be the larger of tWP or (tWZ + tDW) to allow the I/Odrivers to turn off data to be placed on the bus for the requiredtDW. If OE = VIH during an R/W controlled write cycle, this re-quirement does not apply and the write pulse can be as short asthe specified tWP.
ADDRESS
DATAOUT PREVIOUS DATA VALID DATA VALID
tRC
tAA(5)
tOH tOH
CE
OE
DATAOUT
CURRENTISB
ICC50%
VALID DATA(4)
50%
tACE
tAOE(4)
tLZ(1)
tLZ(1)
tPU
tHZ(2)
tHZ(2)
tPD
ADDRESS
R/W
DATAOUT
DATAIN
OE
CE
tWC
tAS(6)
tAW
tWP(2)
(4) (4)
tLZ(7)
tDWtDH
tOW
tHZ(7)
tHZ(7)
tWR(3)
tWZ(7)
2) DATA COMMUNICATIONData is transmitted from the host CPU to the TCP/IP board or viceversa through the dual-port SRAM. If data is written into the sameaddress of the dual-port SRAM from both sides or written into andread from the same address from both sides, data is not assured.The following procedure should be observed.
The format of data to be handled should meet the software specifica-tions.
• Interrupt signals from host to board : Write/INTHW (Host Write),Read/INTHR (Host Read)
/INTHW (Host Write) is generated by writing into the addressH’7*** of the dual-port SRAM and cancelled by outputting the/HWACK signal by 100ns LOW pulse.
/INTHR (Host Read) is generated by reading the address H’B*** ofthe dual-port SRAM and cancelled by outputting the /HRACK sig-nal by 100ns LOW pulse.
• Interrupt signals from board to host : Write /INTSW (Slave Write),Read /INTSR (Slave Read)
/INTSW (Slave Write) is generated by outputting the /SWRQ sig-nal by 100ns LOW pulse and cancelled by writing data into theaddress H’B*** of the dual-port SRAM from the host side..
/INTSR (Slave Read) is generated by outputting the /SRRQ signalby 100ns low pulse and cancelled by reading data from the ad-dress H’7*** of the dual-port SRAM.
7. LAN CONTROL
This board fixes RTL8019AS to the 8-bit mode on hardware.
The initial values of the items in the table are set as shown below byhardware.
Item Setting Remarks
I/O Base Address 300H IOS3~0=0,0,0,0
Network Media Type TP/CX automaticdetection
PL1~0=0,0
BROM Size & MemoryBase Address
Disable BS4~0=0,0,0,0,0
IRQ Select INT0 IRQS2~0=0,0,0
Any data loading EEPROM is not used. MAC address should bewritten by the CPU reading data on the flash memory and writing theregister of the LAN controller.
8. PORT SETTINGThe common pins of the CPU are set as shown below.
PinNo
I/OSelection
signalRemarks
2 I PE15 /WP(FLASH write STATUS)
24 I /IRQ0 Host write end interrupt ( Edge detection)
25 I /IRQ1 Host read end interrupt ( Edge detection)
26 I /IRQ2 Interrupt from LANC ( Edge detection)
28 I /IRQ3 Reserve ( Edge detection)
29 O A18 Address Bus
30 O A19 Address Bus
31 I /WAIT wait from LANC
44 O /CS3 Chip Select for LAN (Usual access space)
45 O /CS2 Chip Select for dual-port SRAM
106 O PE8 /SRRQ (Board side read end request)
107 O PE9 /SWRQ (Board side write end request)
108 O PE10 /HRACK(host side read end interrupt cancel)
110 O PE11 /HWACK(host side write end interrupt cancel)
112 O PE13 /RSTDRViActive Lowj
Write
Y
N
Read
Y
NPreceding data read
end interrupt?
Write data
Generation of writeend interrupt
Data write end interrupt?
Read data
Generation of readend interrupt
AEN
SA19-SA0
SD7-SD0
IORB
IOWB
INT0
IOCHRDY
CPU RTL8019AS
SLOT16 GND/CS3
A19-A0
D7-D0
/RD
/WRL
/IRQ2
/WAIT
9. CONNECTOR PIN TABLE
1) HOST I/F CONNECTOR
Pin No. Signal name Pin No. Signal name
1 +5V 2 +5V
3 +5V 4 +5V
5 A15 6 A14
7 A13 8 A12
9 /DPCS 10 /WR
11 A11 12 A10
13 /RD 14 A0
15 A1 16 A2
17 A3 18 A4
19 A5 20 A6
21 A7 22 A8
23 A9 24 D7
25 D6 26 D5
27 D4 28 D3
29 D2 30 D1
31 D0 32 /LRES
33 /INTSR 34 /INTSW
35 NC 36 NC
37 GND 38 GND
39 GND 40 GND
2) RELAY CABLE
Pin No. Signal name
1 TX+
2 TX-
3 RX+
4 RX-
5 GND
3) RJ-45 CONNECTOR
Pin No. Signal name
1 TX+
2 TX-
3 RX+
4 NC
5 NC
6 RX-
7 NC
8 NC
10. SWITCH SETTING
The board has two switches on it: program loading EPROM(Master ROM)selection switch (SW1) and flash memory write protect switch (SW2).
1) LOCATION OF SWITCHESThe two switches are located on the board as shown below.
2) SWITCH SETTING AT SHIPPINGThe factory setting of the switches are as follows:
Switch Setting Details of setting
SW1 4pin side Boot from FLASH MEMORY
SW2 GND side Write protect into FLASH MEMORY
3) FUNCTIONS OF THE SWITCHES
3)-1. Program loading EPROM(Master ROM) selection switch: SW1
SW1 selects booting from EPROM (Master ROM) to write programdata into flash memory.
When writing data from EPROM (Master ROM) to flash memory,switch over to 6-pin side.
Usually, SW1 is set to marking side.
3)-2. Flash memory write protect switch: SW2SW2 inhibits writing into flash memory.
When writing data from the EPROM (Master ROM) to the flash memory.
Usually, the switch is set to the marking side.
SW1
SW2
4
5
6
1
2
3
FLASH
EPROMSW1
Usual setting
Writing from EPROM(Master ROM)
SW2
GN
D
VC
C
Usual setting Writing from EPROM (Master ROM)
11. WRITING / READING THE MACADDRESS / FIRMWARE PROGRAM
1) WRITING THE MAC ADDRESS & FIRMWAREPROGRAM
1) Install the EPROM (Master ROM) to the TCP/IP I/F PWB (IC5:ICsocket).
2) Set the following switches to the (Writing mode) on the TCP/IP I/FPWB.
SW1 : [FLASH] [EPROM]SW2 : [GND] [VCC]
3) Set the mode switch of the UP-700 to SRV position.
4) Turn ON the AC switch of the UP-700.
5) Display : [SRV MODE]
Select the [5. DIAGNOSTIC] and press the ENTER key
Display : [5. DIAGNOSTIC]
Select the [TCP/IP] and press the ENTER key
Display : [TCP/IP]
Select the [MAC ADD&FIRM WRITE] and press the ENTER key
SW2
SW1:
IC5: IC socketNormal mode Writing mode
Normal mode
Writing mode
FLASH
EPROM
1
2
3
4
5
6
VC
C
GN
D
SRV
12345
READINGSETTINGIRC SET UPDOWN LOADDIAGNOSTIC
UP-600/700 DIAG V1.0APRODUCT & TESTRAM & ROM & SSPCLOCK & KEY & SWITCHSERIAL I/ODISPLAY & PRINTERMCR & DRAWERTCP/IP
TCP/IP & PRINTER DIAGSELF CheckLOOPBACK CheckMAC ADDR & FIRM Ver. ReadMAC ADDR & FIRM WRITEDATA Trans. (MA)DATA Trans. (SA)
Display : [MAC ADD&FIRM WRITE]
Input the MAC address and press the ENTER key.
• MAC address:
The TCP/IP I/F PWB has a seal carrying a MAC address of hexa-decimal number attached on its CPU.Enter this unique code (XXYYZZ) of hexadecimal number as thevalues (3 values of 3 digits) converted to decimal numbers,through the keyboard.Example: When XX,YY,ZZ = 10,00,EB, enter 016,000,224 as
decimal numbers.
Start the writing of the MAC address & Firmware program
When writing is completed, the following message is displayed asshown below.
Display :
6) Press the CANCEL key to exit.
7) Turn OFF the AC switch of the UP-700.
8) Remove the EPROM (Master ROM) from the TCP/IP I/F PWB(IC5: IC socket).
9) Set the following switches to the (Normal mode) on the TCP/IPI/F PWB.
SW1 : [EPROM] [FLASH]SW2 : [VCC] [GND]
10) Execute the "Service reset" .
MAC ADDR & FIRM WriteMAC ADDRESS:AAA BBB CCC08 00 1F XX YY ZZ
AAA BBB CCCMAC Address : Decimal number
XX YY ZZMAC Address : Hexadecimal number
08001FXXYYZZ
08001F : Fixed code
XXYYZZ : Unique code
MAC ADDRESS
IC1 CPU
SW1
SW2
MAC ADDR & FIRM WriteMAC ADDRESS:AAA BBB CCC08 00 1F XX YY ZZTCP/IP FIRM CHANGE:FIRM CHANGE PASS!!
2) READING THE MAC ADDRESS & FIRMWAREPROGRAM
1) Set the mode switch of the UP-700 to SRV position.
2) Display : [SRV MODE]
Select the [ 5. DIAGNOSTIC ] and press the ENTER key
Display : [ 5. DIAGNOSTIC ]
Select the [ TCP/IP ] and press the ENTER key
Display : [TCP/IP]
Select the [MAC ADDR&FIRM Ver. Read] and press the ENTER key
Display : [MAC ADD&FIRM Ver. Read]
3) Press the CANCEL key to exit .
SRV
12345
READINGSETTINGIRC SET UPDOWN LOADDIAGNOSTIC
UP-600/700 DIAG V1.0APRODUCT & TESTRAM & ROM & SSPCLOCK & KEY & SWITCHSERIAL I/ODISPLAY & PRINTERMCR & DRAWERTCP/IP
TCP/IP & PRINTER DIAGSELF CheckLOOPBACK CheckMAC ADDR & FIRM Ver. ReadMAC ADDR & FIRM WRITEDATA Trans. (MA)DATA Trans. (SA)
MAC ADDR & FIRM Ver. READMAC ADDRESS:08 00 1F XX YY ZZFIRMWARE VERSION:27040
: Version number
XX YY ZZMAC Address : Hexadecimal number
87
65
43
21
ABCD
12
34
56
78
D C B A
1/8
CH
AP
TE
R 8
. CIR
CU
IT D
IAG
RA
M1.
MA
IN P
WB
CIR
CU
IT D
IAG
RA
M1)
CP
U
100p
FX
3
NO
T U
SE
DN
OT
US
ED
R58
10K
R64
47
R66
47
R67
47
R68
47
R69
47
C46
C47
C48
C49
C50
X1
19.6
6MH
z
/AS
/RD
/RF
SH
#
IPLO
N0
/HW
R
VC
C
VC
C
18
27
36
45
BR
3910
K*4
RE
S 1
NM
I 2
VS
S 3
D0
4
D1
5
D2
6
D3
7
D4
8
D5
9
D6
10
D7
11
D8
12
D9
13
D10
14
D11
15
D12
16
D13
17
D14
18
D15
19
VS
S 2
0
A0
21
A1
22
A2
23
A3
24
A4
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A5
26
A6
27
A7
28
A8
29
A9
30
A10
31
A11
32
A12
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A13
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A14
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A15
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A17
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A18
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>>>>> USE FONT <<<<<
Helvetica/ Helvetica-Condensed/ Century-Schoolbook/ Symbol & OriginalFonts: (RingWorld2/RingFont2/Pa
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2 0 6IC
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GN
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OE
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JM
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FA
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2SK
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BD
[0..7
]
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EN
ST
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K1
HT
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MC
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T/W
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RX
DI
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IC17
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0
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D 8D 9
A 0A 1
A 2A 3
A 4A 5
A 6A 7
A 8A 9
A 1 0
A 1 1
A 1 2
A 1 3
A 1 4
A 1 5
A 1 6
A 1 7
A 1 8
A 1 9
A 2 0
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A 2 3# /A
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3]
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27
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BR
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C21
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C21
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C21
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C22
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C22
3C
224
C22
5C
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C22
7C
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C22
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C23
1C
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**
IPLO
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C24
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510
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9C
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C21
1C
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1 2 3
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08
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ET
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in--
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Pin
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9 10
8
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0.1u
FC
96
VC
C
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ET
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D S
G Q8
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1826
R23
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F
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For
TC
P/IP
CN
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11
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13
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D
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5 6 4
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R23
73.
09kF
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RB
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RA
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SD
OW
NR
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W)
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(1W
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12
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12
34
12
34
12
87
65
43
21
ABCD
12
34
56
78
D C B A
4/8
4) F
LAS
H R
OM
D[8
..15]
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D1
/A21
VC
C
A0
32
A1
28
A2
27
A3
26
A4
25
A5
24
A6
23
A7
22
A8
20
DQ
1552
DQ
033
DQ
135
DQ
238
DQ
340
DQ
444
DQ
546
DQ
649
DQ
751
DQ
834
DQ
936
DQ
1039
DQ
1141
DQ
1245
DQ
1347
DQ
1450
VC
C9
VC
C43
VC
C37
GN
D21
GN
D42
GN
D48
A9
19
A10
18
A11
17
A12
13
A13
12
A14
11
A15
10
A16
8
A17
7
A18
6
A19
5
A20
4
CE
014
CE
12
OE
54
WE
55
WP
56
RP
16
RY
/BY
53
BY
TE
31
3/5
1V
PP
15
NC
3
NC
29
NC
30
IC3
LH28
F01
6SU
T
A21
A[0
..21]
A21
NO
T U
SE
D 1 2 3
4
5
IC4
(7S
04F
U)
FV
PO
N
NO
RD
Y
/HW
R
/FR
OS
1
/RE
S
/IPLO
N0
VC
C
C64
100p
F
R93 0
R94
1K
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
/RD
D2
D3
D4
D5
D6
D7
/HW
R
/IPLO
N0
VC
C
A21
R92
/RD
FV
PO
N/R
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NO
RD
Y
D[0
..7]
VC
C
IC3
VC
C -
-- G
ND
C62
0.1u
FC
6310
uF/1
6V
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N0
A0
7Pin
: G
ND
* IC
35
14P
in :
VC
C
2 3
1
IC35
A(7
4LS
125)
5 6
4
IC35
B(7
4LS
125)
9 8
1 0
IC35
C(7
4LS
125)
A17
D7
/IPLO
N0
VC
C
A15
1
A14
2
A13
3
A12
4
A11
5
A10
6
A9
7
A8
8
A19
9
NC
10
/WE
11
/RE
SE
T12
NC
13
/WP
14
RY
/BY
15
A16
16
A17
17
A7
18
A6
19
A5
20
A4
21
A3
22
A2
23
A1
24A
025
/CE
26V
SS
27/O
E28
DQ
029
DQ
830
DQ
131
DQ
932
DQ
1034
DQ
335
DQ
1136
VC
C37
DQ
1239
DQ
540
DQ
1341
DQ
1443
DQ
744
DQ
1545
VS
S46
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TE
47A
1648
DQ
642
DQ
438
DQ
233
IC3A
(MB
M29
F16
0(F
LAS
H 1
6M))
A16
A15
A14
A13
A[0
..21]
A[0
..21]
A12
A11
A10
A9
A20
A21
A19
A18
A8
A7
A6
A5
A4
A3
A2
/HW
R/R
ES
FV
PO
N
/HW
R/R
ES
FV
PO
NN
OR
DY
A1
D15
D6
D14
D5
D13
D12
D11
D10
D9
D8
D0
D1
D2
D3
D4
/RD
/FR
OS
1
D[8
..15]
D[0
..7]
/FR
OS
1
/RD
D[8
..15]
D[0
..7]
12 1
1
1 3
IC35
D(7
4LS
125)
87
65
43
21
ABCD
12
34
56
78
D C B A
5/8
5) L
CD
C_M
EM
OR
Y
/PO
FF
VC
C
R22
6
56K
D10
(1S
S35
3)
R22
74.
7K
3 21
8 4
IC27
A
BA
1039
3
IC28
(KIA
7045
F)
[PO
FF
]
+24
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C18
91u
F/5
0V
R22
53.
9K(1
/4W
)
R22
29.
1KF
R22
39.
1KF
R22
44.
7KF
VC
C
A10
A11
A12
A13
A[0
..13]
D[8
..15]
D 1 2
D 1 1
D 1 0
D 9D 8
LPCP
D 1 5
D 1 4
D 1 3
V S S
6 5
V S S
4 0
V S S
6 4
CP
66
LP 6
7
N . C
3 9N . C
3 8N . C
3 7N . C
3 6
V S S
3 5
V D D
3 4
N . C
3 3
N . C
3 2
A13
31
A12
30
A11
29
A10
28
A9
27
A8
26
V S S
2 5
FLM
68
UD
0 6
9
UD
1 7
0
UD
2 7
1
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3 7
2
N . C
7 3
N . C
7 4
N . C
7 5
N . C
7 6
V D D
7 7
OS
C1
78
O S C 2
7 9
V S S
8 0
V D D
6 3
M62
LCD
EN
B61
D 1 5
6 0 D 1 4
5 9 D 1 3
5 8 D 1 2
5 7 D 1 1
5 6 D 1 0
5 5 D 9
5 4 D 8
5 3
V D D
5 2
V S S
5 1
D 7
5 0 D 6
4 9 D 5
4 8 D 4
4 7 D 3
4 6 D 2
4 5 D 1
4 4 D 0
4 3
V D D
4 2
V S S
4 1
V S S
1
IOC
S 2
HW
R 3
LWR
4R
D 5
MC
S 6
WA
IT 7
V D D
8
MP
UC
LK 9
RE
SE
T 1
1
M P U S E L
1 2
V S S
1 0
V S S
1 3
B H E
1 4
A0
15A
116
A2
17A
318
A4
19A
520
A6
21A
722
V D D
2 3
V S S
2 4
IC22
LCD
C(M
6627
1FP
)
##
FLM
LD3
LD2
LD1
LD0
/VIO
/HW
R/R
D/V
ME
M/V
WA
IT/V
WA
IT/V
ME
M /RD
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R
/VIO
LCD
Con
trol
ler
M66
271F
B
VC
C
/RE
SE
T/R
ES
ET
VC
C
C23
510
uF/1
6VC
236
0.1u
F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
M LCD
EN
BM LC
DE
NB
ZD
3R
D4.
3MB
1 VC
C
C24
00.
1uF
R24
3
2.2K
F
R24
4
2KF
R24
1
*150
F
R24
2
*150
F
C19
010
00pF
+24
V
5 67
8 4
IC27
B
BA
1039
3
R24
5
56K
/RA
SP
N1
/RE
SE
T
7PIN
:GN
D
VC
KD
CV
CK
DC
VC
KD
C
RA
SP
N1
C17
110
00pF
C17
310
00pF
9 10
8
1 4
IC24
C74
LV00
A
1 23
1 4
IC24
A74
LV00
A
4 56
1 4
IC24
B74
LV00
A
/RE
SE
TS
A15
A13
A8
A9
A11
A10
/RD
A17
/RD
VC
KD
C
R20
8
10K
/HW
R/H
WR
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A[0
..18]
A18
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
D8
13
D9
14
D10
15
GN
D 1
6
VC
C32
A15
31
A17
30
WR
29
A13
28
A8
27
A9
26
A11
25
RD
24
A10
23
CS
22
D15
21
D14
20
D13
19
D12
18
D11
17
IC23
4M-S
RA
M
TS
OP
A0
D8
D9
C16
80.
1uF
D[8
..15]
D10
C16
9(1
0uF
/16V
)
VC
KD
C
D11
D12
D13
D14
D15
/RA
SP
N1
C17
0
100p
F
VC
KD
C
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SP
N2
RA
SP
N2
RA
SP
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C17
2
1000
pF
12
13
11
1 4
IC24
D74
LV00
A
(OP
T R
AM
)
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SP
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87
65
43
21
ABCD
12
34
56
78
D C B A
6/8
6) R
S23
2C
CH
1
12
3
GN
DC
IAE
RA
CS
AS
DA
RS
AR
DA
DR
AC
DA
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C
S40
1
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S31
2
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1
(0)
(R1)
5 9 4 8 3 7 2 6 1
CN
402
D-S
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9P
in
TO
MA
INB
Y C
AB
LE
VC
C
VC
C
VC
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AC
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SD
AR
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RD
A
GN
D
< R
S23
2C R
ELA
Y P
WB
>
PF
401
PO
LY S
W
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CN
401
RS
232C
RE
LAY
CA
BLE
CN
(20P
in,2
mm
Pitc
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FB
38B
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4
T2I
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3
T3I
N 1
2
R1O
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1
R2O
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B 2
0
R1O
UT
19
R2O
UT
18
R3O
UT
17
R4O
UT
16
R5O
UT
15
EN
23
G N D
2 5
T1O
UT
9
T2O
UT
10
T3O
UT
11
R1I
N 4
R2I
N 5
R3I
N 6
R4I
N 7
R5I
N 8
SH
DN
22IC19
MA
X32
41
[ CH
1 ]
/TX
D1
VC
C
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S1
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R1
C15
80.
1uF
C15
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1uF
C15
70.
47uF
C1+
28
V+
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2 6
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24
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2+ 1
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2
T1I
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4
T2I
N 1
3
T3I
N 1
2
R1O
UT
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1
R2O
UT
B 2
0
R1O
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E T
YP
E D
ES
IGN
R69 (0
)
G3'
G2'
G1'
/S7
/S6
/S5
9 8
1 0
IC3C
74LS
125
12 1
1
1 3
IC3D
74LS
125
2 3
1
IC4A
74LS
125
*IC
4*I
C3 VC
CV
CC
C40
0.1u
FC
410.
1uF
G[1
'..10
']
/X4
/X5
/X6
FB
3
BLM
21
FB
4
BLM
21
/X1
/X2
/X3
FB
5
BLM
21
FB
6
BLM
21
FB
7
BLM
21A
'
/S4
/S3
/S2
VC
C
R33
4.7K
5 6
4
IC4B
74LS
125
9 8
1 0
IC4C
74LS
125
G'
F'
E'
D'
C'
B'
R70 0
DP
'
*IC
2 : 6
5083
G7'
G8'
G9'
PD
S'
G10
'
FIS
CA
L : P
DS
NO
RM
AL
: G7'
G7'
G7'
G7'
1
G8'
2
G9'
3
G10
' 4
PD
S'
5
CN
9
(PO
P C
N.5
2807
-051
0)
SG
DP
10P
in--
NU
1 2
7
IC2G
: 9P
in--
GN
D
1 1
8
IC2H
KID
6508
3AP
C21
SA
SB
SC
SD
SE
SF
1 8
1
IC2A
1 7
2
IC2B
1 6
3
IC2C
1 5
4
IC2D
1 4
5
IC2E
1 3
6
IC2F
C22
C23
C24
C25
C26
C27
/CF
SR
/CF
SR
D2
1SS
353
12 1
1
1 3
IC4D
74LS
125
C28 10
00pF
*8/X
0
* IC
3,IC
4 : 7
Pin
--G
ND
14P
in--
VC
C
FB
8
BLM
21
87
65
43
21
ABCD
12
34
56
78
D C B A
3/3
3) K
EY
BO
AR
D
KE
Y14
4
16 1
6
17 1
7
18 1
8
KE
Y_C
N_1
8P(5
229-
18C
PB
)
VC
C
/MO
DR
/MO
DR
VC
C
ST
0S
T1
ST
2S
T3
/S0
/S1
/S2
/S3
/S4
/S5
R35
47K
C34
0.1u
F
CK
DC
RC
KD
CR
A 1
B 2
C 3
G1
6
G2A
4
G2B
5
Y0
15
Y1
14
Y2
13
Y3
12
Y4
11
Y5
10
Y6
9Y
7 7
VC
C16
GN
D 8
IC5
74LS
138
VC
C
/S6
/S7
/S8
/S9
/S10
/S11
/S12
/S13
/S14
/S15 V
CC
KE
X0
KE
X1
C35
0.1u
F
A 1
B 2
C 3
G1
6
G2A
4
G2B
5
Y0
15
Y1
14
Y2
13
Y3
12
Y4
11
Y5
10
Y6
9Y
7 7
VC
C16
GN
D 8
IC6
74LS
138
VC
C
/S13
/S14
/S15
D28
1SS
353
D29
1SS
353
/ K R 0 A
/ K R 1 A
/ K R 2 A
/ K R 3 A
/ K R 0 B
/ K R 1 B
/ K R 2 B
/ K R 3 B
/ K R 0 C
R48
R49
R50
R51
R52
R53
R54
R55
R56
47K
*11
VC
C
/ K R 1 C
R46
R47
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
1 0
1 0
1 1
1 1
CN
6
KE
T_C
N_1
1P(5
229-
11C
PB
)
VC
C
/KR
3B/K
R3A
1G 1
B 2
1C3
3
1C0
6
1C2
4
1C1
5
2G15
A14
2C3
13
2C2
12
2C1
11
2C0
10
2Y 9
1Y 7
VC
C16
GN
D 8
IC8
74H
C15
3
C37
0.1u
F
R42
47K
R43
47K
R44
47K
R45
47K
VC
C
/KR
0
/KR
1
/KR
0A
/KR
0C/K
R0B
/KR
1C/K
R1B
/KR
1A
/KR
2B/K
R2A
/KR
2
/KR
3
1G 1
B 2
1C3
3
1C0
6
1C2
4
1C1
5
2G15
A14
2C3
13
2C2
12
2C1
11
2C0
10
2Y 9
1Y 7
VC
C16
GN
D 8
IC7
74H
C15
3
C36
0.1u
F
R36
47K
R38
47K
R37
47K
R41
47K
R39
47K
R40
47K
VC
C
CK
DC
R/S
1/S
2/S
3/M
OD
R/S
4/S
5/S
6/S
7/S
8
1 2 3 4 5 6 7 8 9 10 11
CN
7
MO
DE
SW
.CN
.520
11-1
110
D27
/RS
0
/C0
/C1
/S10
/S11
/S0
/S1
/S2
/S3
D12
1SS
353
D13
1SS
353
D14
1SS
353
D15
1SS
353
D16
1SS
353
D17
1SS
353
KE
YB
OA
RD
SW
1
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 1
0
11 1
1
12 1
2
13 1
3
14 1
4
15 1
5
CN
5
VC
C
C38
10uF
/16V
D4
1SS
353
D5
1SS
353
D6
1SS
353
/S12
/S2
/S3
/CF
SR
D3
1SS
353
D7
1SS
353
D8
1SS
353
D9
1SS
353
D10
1SS
353
D11
1SS
353
D3:
FLA
T K
/B N
OT
US
E
FLA
T K
/B N
OT
US
E
/S13
/S4
/S5
/S6
/S7
/S8
/C2
/C3
/C4
/C5
/C6
/CF
SR
/S4
/S5
/S6
/S7
/S8
/S9
/S10
/S11
/S12
D18
1SS
353
D19
1SS
353
D20
1SS
353
D21
1SS
353
D22
1SS
353
D23
1SS
353
D24
1SS
353
D25
1SS
353
D26
1SS
353
1SS
353
NO
T U
SE
87
65
43
21
ABCD
12
34
56
78
D C B A
1/1
3. IP
L R
OM
PW
B
VC
C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
CN
303
Opt
ion
RA
M S
TA
CK
CN
.357
73-4
020
3 1
2
SW
302
IPL
SW
SLI
DE
SS
S81
2-B
-2B
3 1
2
SW
301
IPL
SW
SLI
DE
SS
S81
2-B
-2B
VC
C/O
PB
S
/IPLO
N1
A21
A20
A19
A18
VC
C
/IPLO
N0
/HW
R
IPL-
RO
M R
ELA
Y P
WB
]
123456789101112131415161718192021222324252627282930313233343536373839404142434445
CN
301
IPL
RO
M F
PC
CN
.XF
2H-4
515-
1
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
/RD
D15
D14
D13
D12
D11
D10
D9
D8
/RA
SP
N2
VC
KD
C
TO
MA
IN
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D8
D9
A19
1
A16
2
A15
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
D8
13
D9
14
VC
C32
A18
31
A17
30
A14
29
A13
28
A8
27
A11
25
OE
24
A10
23
D15
21
D14
20
D13
19
D12
18
D11
17D
10 1
5
GN
D 1
6
CE
22
A9
26
IC30
2
8M R
OM
1
VC
C
D13
D14
D15
A18
A17
A14
A13
A8
A9
A11
A10
/RD
/EP
RO
M1
C30
30.
1uF
C30
4(1
00pF
)
VC
C
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
/RD
D15
/HW
R
D14
D13
D12
D11
D10
D9
D8
/RA
SP
N2
VC
KD
CG
ND
GN
D
TO
RA
M P
WB
D11
D12
VC
C
A18
A17
A14
A13
A8
A9
A11
A10
/RD
C30
50.
1uF
D10
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
VC
CC
308
10uF
/16V
A19
1
A16
2
A15
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
D8
13
D9
14
VC
C32
A18
31
A17
30
A14
29
A13
28
A8
27
A11
25
OE
24
A10
23
D15
21
D14
20
D13
19
D12
18
D11
17D
10 1
5
GN
D 1
6
CE
22
A9
26
IC30
3
8M R
OM
2
GN
D
/EP
RO
M2
VC
KD
C
GN
DG
ND
/EP
RO
M1
/OP
BS
I
A1
A0
D8
D9
D10
VC
CC
9
10uF
/16V
D11
D12
D13
D14
D15
/EP
RO
M2
C30
6(1
00pF
)
87
65
43
21
ABCD
12
34
56
78
D C B A
1/1
4. L
CD
I/F
PW
B
LCD
320X
240
LF10
036K
GT
(0,0
)
V0L
121
V1L
122
V4L
123
V5L
124
VS
S12
5
SH
L12
9
DIO
212
6
CK
132
DIS
PO
FF
#12
8F
R12
7
DIO
113
3
VD
D13
4
V5R
135
V4R
136
V1R
137
V0R
138
O12
012
0
O1
1
MO
DE
130
DM
IN13
1
V0L
121
V0R
138
IC1
LH15
30
V0L
121
V1L
122
V4L
123
V5L
124
VS
S12
5
SH
L12
9
DIO
212
6
CK
132
DIS
PO
FF
#12
8F
R12
7
DIO
113
3
VD
D13
4
V5R
135
V4R
136
V1R
137
V0R
138
O12
012
0
O1
1
MO
DE
130
DM
IN13
1
V0L
121
V0R
138
IC2
LH15
30
V0
V1
V4
GN
D
M LCD
EN
B+
5V
LPFLM
12
34
56
78
91 0
VR
PW
B
VR
201
5k
1 2 3
CN
201
VR
CN
.532
61-0
390
V 0V 1
V 4L P
L C D E N B
M+ 5 V
G N D
R1
18
F L M
12
34
56
78
91 0
CN
4
FP
C 1
0PIN
CA
BLE
C11
0.1u
FV 0 L
V 2 L
V 3 L
V 5 L
V D DM D
S H L
E I O 2
D I 0
D I 1
D I 2
D I 3
D I 4
D I 5
D I 6
D I 7
X C KL P
D I S P O F F #F R
E I O 1
V S S
V 5 R
V 3 R
V 2 R
V 0 R
Y 1 6 0
1 6 0
Y 1
1
V 0 L
V 0 R
1 6 1
1 6 2
1 6 3
1 6 4
1 6 5
1 6 6
1 6 7
1 6 8
1 6 9
1 7 0
1 7 1
1 7 2
1 7 3
1 7 4
1 7 5
1 7 6
1 7 7
1 7 8
1 7 9
1 8 0
1 8 1
1 8 2
1 8 3
1 8 4
1 8 5
1 8 6
1 6 1
1 8 6
IC3
LH15
40
L D 1
L D 0
L D 2
L D 3
(320
X24
0)
V 0 L
V 2 L
V 3 L
V 5 L
V D DM D
S H L
E I O 2
D I 0
D I 1
D I 2
D I 3
D I 4
D I 5
D I 6
D I 7
X C KL P
D I S P O F F #F R
E I O 1
V S S
V 5 R
V 3 R
V 2 R
V 0 R
Y 1 6 0
1 6 0
Y 1
1
V 0 L
V 0 R
IC4
LH15
40
L D 0
L D 1
L D 2
L D 3
C3
0.1u
F
V2
V3
V0
GN
D+
5V
LD[0
..3]
CP
LP LCD
EN
BM
C2
0.1u
F
+5V
LD0
LD1
LD2
LD3
GN
D
GN
D
LPMFLM
CP
LCD
EN
B
R2
18
R3
18
R4
18
R5
18
C4
C5
C6
C7
C8
1uF
*5
LD[0
..3]
VO
C1
1uF
VO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CN
1
LCD
CN
(15P
)ELC
O 0
0-62
00-1
57-0
32-8
00
VB
LED
C9
4.7u
F/5
0V
NC
1
VIN
3 2
V3
3
RX
4 4
RX
3 5
RX
2 6
V4
7
NC
8
VE
E 9
NC
10
NC
11V
RE
F12
ST
R13
V1
14R
X1
15V
IN2
16V
217
NC
18V
CC
19N
C20
IC5
LA53
12V
R6
OP
EN
R7
0 R8
0 R9
OP
EN
R10
0
VO
2,3
6,7
12 4
IC6
LM31
7L
R11
240
C10
1uF
/50V
5,8P
in:N
U
R12 3k
R13
2.2k
1 2CN
2
LED
CN
.532
61-0
290
1 2 3
CN
3
VR
CN
.532
61-0
390
1 6 1
1 6 2
1 6 3
1 6 4
1 6 5
1 6 6
1 6 7
1 6 8
1 6 9
1 7 0
1 7 1
1 7 2
1 7 3
1 7 4
1 7 5
1 7 6
1 7 7
1 7 8
1 7 9
1 8 0
1 8 1
1 8 2
1 8 3
1 8 4
1 8 5
1 8 6
1 6 1
1 8 6
87
65
43
21
ABCD
12
34
56
78
D C B A
1/1
5. P
OP
UP
DIS
PLA
Y P
WB
1 31 4
41 7
1 81
23
1 51 6
97
1 25
68
1 01 1
FN
D4
DIG
5'D
IG6'
DIG
7'
1 31 4
41 7
1 81
23
1 51 6
97
1 25
68
1 01 1
FN
D2
1 31 4
41 7
1 81
23
1 51 6
97
1 25
68
1 01 1
FN
D3
DIG
1'D
IG2'
DIG
3'D
IG4'
1 31 4
41 7
1 81
23
1 51 6
97
1 25
68
1 01 1
FN
D1
1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
CN
1
PO
P U
P C
N.C
AB
LE(1
5P)
A'
B'
C'
D'
E'
F'
G'
DP
'
R20
R22
R24
R14
R16
R18
R10
R12
2727
2727
2727
2727
87
65
43
21
ABCD
12
34
56
78
D C B A
6. T
CP
/IP IN
LIN
E I/
F P
WB
1) C
PU
VC
C
LD0
LD1
LD2
LD3
LD4
LD5
LD6
18
27
36
45
BR
110
k*4
18
27
36
45
BR
210
k*4
LD[0
:7]
HD
0H
D1
HD
2H
D3
HD
4H
D5
HD
6H
D7
VC
C
HD
[0:7
]
2 1
C41
470p
F
PLL
VC
C
2 1
C43
0.1u
F
PLL
VS
S
1 8
2 7
3 6
4 5
BR
3
33*4
1 8
2 7
3 6
4 5
BR
4
33*4
2 1
(C3)
18pF
2 1
(C4)
18pF
VC
C
R70 3k
R71
200
R4
10k
R3
10k
R2
10k
2 1
C42
0.1u
F
R75
10k
X1
5MH
zC
ST
CR R
7
680
R76
10k
(R5)
10k
(R6)
10k
SH
7014
/LR
ES
H D 0
H D 1
/RT
S1
/DT
R1
/DC
D1
/CI1
/DS
R1
VC
C
/CT
S1
R13
910
k
R13
810
k
PLL
VS
S
R1
10k
PE
0/T
I0C
0A/D
RE
Q0
85
PE
1/T
IOC
0B/D
RA
K0
86
D12
56
P E 1 4 / D A C K 0 / ~ A H
1
R E S8 4 P E 1 5 / D A C K 1
2V S S
3A 0
4A 1
5A 2
6A 3
7A 4
8A 5
9A 6
1 0A 7
1 1A 8
1 2A 9
1 3A 1 0
1 4A 1 1
1 5A 1 2
1 6A 1 3
1 7A 1 4
1 8A 1 5
1 9A 1 6
2 0V C C
2 1A 1 7
2 2V S S
2 3P B 2 / ~ I R Q 0 / ~ R A S
2 4P B 3 / ~ I R Q 1 / ~ C A S L
2 5P B 4 / ~ I R Q 2 / ~ C A S H
2 6V S S
2 7P B 5 / ~ I R Q 3 / R D W R
2 8
PE
2/T
IOC
0C/D
RE
Q1
87
PE
3/T
IOC
0D/D
RA
K1
88
PE
4/T
IOC
1A 8
9
VS
S 9
0
PF
0/A
N0
91
PF
1/A
N1
92
PF
2/A
N2
93
PF
3/A
N3
94
PF
4/A
N4
95
PF
5/A
N5
96
AV
SS
97
PF
6/A
N6
98
PF
7/A
N7
99
AV
CC
100
VS
S10
1
PE
5/T
IOC
1B10
2
VC
C10
3
PE
6/T
IOC
2A10
4
PE
7/T
IOC
2B10
5
PE
810
6
PE
910
7
PE
1010
8
VS
S10
9
PE
1111
0
PE
1211
1
PE
1311
2
P A 1 5 / C K
8 3
PB
6/A
1829
PB
7/A
1930
PB
8/IR
Q6/
A20
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IT31
P L L V S S
8 2 P L L C A P
8 1 P L L V C C
8 0 M D 07 9 M D 17 8 V C C
7 7 N M I7 6 M D 27 5 E X T A L
7 4 M D 37 3 X T A L7 2 V S S
7 1 D 0
7 0 D 1
6 9 D 2
6 8 D 3
6 7 D 4
6 6 V C C
6 5 D 5
6 4 D 6
6 3 D 7
6 2 V S S
6 1 D 8
6 0 D 9
5 9 D 1 0
5 8 D 1 1
5 7
VS
S55
D13
54
D14
53
D15
52
PA
0/R
XD
051
PA
1/T
XD
050
PA
2/S
CK
0/D
RE
Q0/
IRQ
049
PA
3/R
XD
148
PA
4/T
XD
147
PA
5/S
CK
1/D
RE
Q1/
IRQ
146
PA
6/T
CLK
A/C
S2
45
PA
7/T
CLK
B/C
S3
44
PA
8/T
CLK
C/IR
Q2
43
PA
9/T
CLK
D/IR
Q3
42
CS
041
CS
140
VS
S39
WR
L38
VC
C37
WR
H36
WD
TO
VF
35
RD
34
VS
S33
PB
9/IR
Q7/
A21
32
IC1
CP
U_S
H70
14
CP
U
R73
10k R74
10k
1 8
2 7
3 6
4 5
BR
1310
k*4
1 8
2 7
3 6
4 5
BR
1110
k*4
1 8
2 7
3 6
4 5
BR
1210
k*4
H D 2
H D 3
H D 4
H D 5
H D 7
H D 6
H D 8
H D 9
H D 1 0
H D 1 1
HD
12
HD
13H
D14
HD
15
/MW
E
/CS
1/C
S0
/CS
3
VC
C
RX
D1
TX
D1
/CS
DP
RA
M
1 8
2 7
3 6
4 5
BR
5
10k*
4
1 8
2 7
3 6
4 5
BR
6
10k*
4
1 8
2 7
3 6
4 5
BR
1810
k*4
1 8
2 7
3 6
4 5
BR
1710
k*4
LD7
VC
C
R13
210
kR
133
10k
21C5
21C6
21C7
21C8
21C9
21C10
21C11
21C12
100p
F*8
18
27
36
45
BR
8
18
27
36
45
BR
9
18
27
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BR
10
18
27
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45
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10k*
410
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10k*
4
VC
C
LA[0
:17]
LA0
LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LA10
LA11
LA12
LA13
LA0
LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA10
LA11
LA12
LA13
LA9
VC
C
/INT
HW
/INT
HR
/INT
LAN
LA[0
:17]
L A 1 3
L A 1 4
L A 1 5
L A 1 6
L A 1 7
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HR
DY
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R15
10k
LA19
LA18
R13
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10k
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C
R13
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10k
LA19
R13
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10k
R8
10k
21C
4010
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LA18
21C
3910
0pF
21C
10.
1uF
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TD
RV
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AC
K
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Q
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Q
L A 0
L A 1
L A 2
L A 3
L A 4
L A 5
L A 6
L A 7
L A 8
L A 9
L A 1 0
L A 1 1
L A 1 2
VC
C
R12
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10k
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D4
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1 8
2 7
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4 5
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1410
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R72
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R14
147
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LAN
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12
R69 10
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13
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6
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1
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C10
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LA[0
:17]
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RO
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SH
R12
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LA14
LA15
LA16
LA17
21C21
21C22
21C23
21C24
21C25
21C26
21C27
21C28
21C29
21C30
21C31
21C32
21C33
21C34
21C35
21C36
21C37
21C38
100p
F*1
8C
21~
38
LA14
LA15
LA16
LA17
1/4
87
65
43
21
ABCD
12
34
56
78
D C B A
2) L
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CO
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RO
LLE
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(R10
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(R10
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(R10
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R91
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(R92
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93)
(R94
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95)
(R96
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VC
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(R99
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(R10
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102)
(R83
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82)
(R85
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84)
BD
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B D 4 ( I R Q S 2 )
8 0 B D 5 ( I R Q S 1 ) ( E E S K )
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I N T 1 ( I R Q 3 ) 3
I N T 0 ( I R Q 2 / 9 ) 4S A 0
5V D D
6S A 1
7S A 2
8S A 3
9S A 4
1 0S A 5
1 1S A 6
1 2S A 7
1 3G N D
1 4S A 8
1 5S A 9
1 6V D D
1 7S A 1 0
1 8S A 1 1
1 9S A 1 2
2 0S A 1 3
2 1S A 1 4
2 2S A 1 5
2 3S A 1 6
2 4S A 1 7
2 5S A 1 8
2 6S A 1 9
2 7G N D
2 8
I O R B
2 9
I O W B
3 0
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EM
RB
31S
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MW
B32
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RV
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34IO
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RD
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036
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137
SD
238
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339
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440
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541
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642
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743
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5 3
C D +
5 4
R X -
5 5
R X +
5 6
V D D
5 7
T P I N -5 8
T P I N +
5 9
L E D B N C
6 0
L E D 0 ( L E D C O L ) ( L E D L I N K )
6 1
L E D 1 ( L E D R X ) ( L E D C R S )
6 2
L E D 2 ( L E D T X )6 3
A U I6 4
J P
6 5
B A 2 1 ( P N P )6 6
B A 2 0 ( B S 0 )
6 7
B A 1 9 ( B S 1 )
6 8
B A 1 8 ( B S 2 )
6 9
V D D
7 0
B A 1 7 ( B S 3 )
7 1
B A 1 6 ( B S 4 )
7 2
B A 1 5
7 3
B A 1 4 ( P L 0 )
7 4
B C S B
7 5
E E C S
7 6
B D 7 ( P L 1 ) ( E E D O )
7 7
B D 6 ( I R Q S 0 ) ( E E D I )
7 8
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BD
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7(IR
Q15
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6(IR
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5(IR
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Q10
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R90
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R14
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R14
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LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
L A 0
L A 1
L A 2
L A 3
L A 4
L A 5
L A 6
L A 7
L A 8
L A 9
L A 1 0
L A 1 1
L A 1 2
L A 1 3
L A 1 4
L A 1 5
L A 1 6
L A 1 7
L A 1 8
L A 1 9
LA[0
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R86
10k
R87
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LA[0
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R88
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IOC
HR
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LAN
CO
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(R12
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(R12
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R12
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LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15
VC
C
VC
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1 8
2 7
3 6
4 5
BR
1510
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(R12
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127)
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R81
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LD[0
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LD[0
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2/4
87
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D C B A
3) M
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LA[0
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L A 1 1
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A 1 0 L
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A1L
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A2L
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A3L
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A4L
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A5L
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A6L
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I/O0L
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I/O1L
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LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LD0
LD1
LD2
LD3
L D 4
L D 5
L D 6
L D 7
S D 0
S D 1
S D 2
S D 3
S D 4
S D 5
S D 6
S D 7
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LD0
LD3
LD4
LD5
LD6
LD7
LA10
LA11
LA9
LA8
LA13
LA15
LA16
LA14
LA12
LA7
LA6
LA5
LA4
LA3
LA2
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A9
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A11
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I/O7
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I/O6
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I/O5
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LA15
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D39
NC
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A10
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DQ
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DQ
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DQ
533
DQ
432
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C30
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LD1
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LA13
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LA9
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A13
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A8
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1 3 5 7 9 11 13 15 17 19
21 23 25 27 29 31 33 35 37 39
4 6 8 10 12 14 16 18 20
22 24 26 28 30 32 34 36 38 40
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>>>>> USE FONT <<<<<
Helvetica/ Helvetica-Condensed/ Century-Schoolbook/ Symbol & OriginalFonts: (RingWorld2/RingFont2/Pa
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8. POP UP DISPLY
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6. TCP/IP RELAY PWB 7. VR PWB
10. TCP/IP I/F PWB
B side
A side
COPYRIGHT 2001 BY SHARP CORPORATION
All rights reserved.Printed in Japan.
No part of this publication may be reproduced,stored in a retrieval system, or transmitted.
In any form or by any means,
electronic, mechanical, photocopying, recording, or otherwise,without prior written permission of the publisher.
SHARP CORPORATIONDigital Document Systems GroupQuality & Reliability Control CenterYamatokoriyama, Nara 639-1186, Japan
2001 July Printed in Japan
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Helvetica/ Helvetica-Condensed/ Century-Schoolbook/ Symbol & OriginalFonts: (RingWorld2/RingFont2/Pa
Symbol/PartsCod)
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