FOREWORD

Selamat Datang… Welcome... The organizing committee warmly welcomes you to the 33rd International Electronics Manufacturing Technology Conference IEMT 2008. IEMT 2008 is held here for the second time in Malaysia at The Parkroyal Hotel, Penang on the 4th-6th November 2008. This premier international conference is jointly sponsored by the IEEE Components, Packaging and Manufacturing Technology (CPMT) Society Malaysia Chapter with co-sponsorship from CPMT Santa Clara Chapter. The organizing committee comprises of representatives from local and international companies and worked together to make this conference a successful one. The IEMT 2008 features a wide variety of discussion topics related to electronic packaging such as Emerging Technology, Advanced Packaging, Manufacturing Technology, Chip Scale Packaging, Flip Chip, Materials, Simulation & Modeling, Reliability and many more. This year, we received an overwhelming response to our Call-For-Paper from all over the world. With the help from a number of technical experts form various industry in electronics packaging, we have selected and finalized 112 high-quality papers to be presented at the conference in total 27 oral presentation sessions. We have also selected 30 poster papers to be posted for poster presentation. These papers represent the technical works by authors from various companies, research and academic institutions from nearly 20 countries. That makes this conference a truly a global event. In addition to the paper and poster presentation, IEMT 2008 will also feature 6 keynote talks by distinguished speakers in the field. We will have Dr. William Chen give his opening address on “Engineering In The Era Of Consumer Driven Market”. This will be followed by other keynote talks from Dr. Raj Master from AMD, Dr. Mervi Poulasto from Infineon Technologies, Dr. Rolf Aschenbrenner from IZM, Dr. Karl Johnson from Freescale Semiconductor and Mr. YK Sow from Intel Technologies. We are also privileged to have four Professional Development Courses (PDC) short courses delivered by four distinguished experts, Prof. Dr. Kankanhalli Seetharamu from PES Institute, Prof. Dr. Ricky Lee from HKUST, Mr. Shimamoto Haruo from Renesas and Mr. Luu Nguyen from National Semiconductor. A 2-day table top exhibition, which features suppliers and service providers of the microelectronics and electronic industry, will also be held. We take this opportunity to thank the organizing companies, sponsors, exhibitors, authors, keynote speakers, PCD instructors, session chairs, invited guests, representatives from Santa Clara Sister Chapter and all volunteers for their support and hard works. We also would like to thank all participants and conference attendees. Together, we make IEMT 2008 a successful and great event. To our foreign as well as local delegates, please enjoy the Malaysian food delicacies and cultural shows. We believe that that you will have a memorable and joyful conference at IEMT 2008. Azhar Aripin Dr. Chee Chong Kooi Prof. Dr. Ibrahim Ahmad General Chair Program Chair Technical Chair ON Semiconductor Intel Universiti Tenaga Nasional

ORGANIZING COMMITTEE

General Chair Azhar Aripin, ON Semiconductor Sdn. Bhd. Past General Chair Chew Chee Hiong, ON Semiconductor Sdn. Bhd. Program Chair Dr. Chee Chong Kooi, INTEL Technology Sdn. Bhd. Program Vice Chair Annette Teng, Corwil, USA Technical Chair Prof. Dr. Ibrahim Ahmad, Universiti Tenaga Nasional Technical Vice Chair Lily Khor, Carsem (M) Sdn. Bhd. Exhibitions Chair Jonas Sjöberg, Flextronics Short Course Chair LC Tan, Freescale Chew Chee Hiong, ON Semiconductor Sdn. Bhd. Sponsorship Chair SH Khor, STATSchipPAC Fuaida Haron, Infineon Technologies Social & Tour Chair Jariyah Hashim, Advanced Micro Devices Facility & Logistic Chair Michael Raja, Advanced Micro Devices Poster Paper Chair Shahrul Kamaruddin, Universiti Sains Malaysia Publication Chair Dr. Ishak Abdul Azid, Universiti Sains Malaysia Administration Chair Paul Wesling, IEEE, USA Finance Chair Lim Wee Teck, ON Semiconductor Sdn. Bhd. Secretariat Ir. Dr. Cheong Kuan Yew, Universiti Sains Malaysia Wong Shaw Fong, INTEL Technology Sdn. Bhd.

INTERNATIONAL ADVISORY BOARD

Dr. William Chen, ASE, USA Dr. TS Yeoh, Intel Technologies, MALAYSIA Dr. Thorsten Teutsch, PacTech, USA Kyung-Wook Paik, KAIST, KOREA Prof. Dr. Ricky Lee, HKUST, HONG KONG Raj Master, Advanced Micro Devices, USA Rolf Aschenbrenner, Fraunhofer IZM, GERMANY Kiyokazu Yasuda, Osaka University, JAPAN Wayne Johnson, Auburn University, USA Yi-Shao Lai, ASE, TAIWAN Jan Vardaman, Techsearch International, USA Saat Shukri Embong, Freescale, MALAYSIA Dr. John Lau, Institute of Microelectronics, SINGAPORE Prof. Kankanhalli Seetharamu, PES Institute, INDIA Kouchi Zhang, Philips, NETHERLAND Prof. Rao Tummala, Georgia Tech, USA Eric Beyne, IMEC, BELGIUM Bernie Siegal, TEA, USA Dr. Robert Hagen, Infineon Technologies, GERMANY Luu Nguyen, National Semiconductor Corp., USA Chris Bailey, University of Greenwich, UK Charles Vath, ASM, SINGAPORE

CONFERENCE INFORMATION

Conference Kit All registrants will receive a conference kit upon registration at the registration desk. The items inside the kit include final program booklet, thumb drive containing all accepted papers and souvenirs. Name Badge All registrants are required to put on their badges during the entire conference events. Message Board All messages for participants received by the Conference Secretariat are to be posted on the Message Board. It is located at the lobby in front of Grand Ballroom. Please check the board regularly. Lunch Lunch is provided to all registrants during lunch hour at the hotel lunch area which is located near to the swimming pool. Coffee Break Coffee with local delicacies will be provided to all participants during the coffee break. Dinner and Cultural Show A BBQ dinner and cultural show will be held on Wednesday evening (19:30PM – 23:00PM) at the hotel lawn near the beachside. This will provide participants with an opportunity to socialize in a relaxed atmosphere while enjoying the entertainment of fascinating cultural show. Tourist Attractions There are a number of tourist attractions around Penang. Please consult the hotel management for the destination. There are also many bargain souvenirs being sold at the close proximity of the hotel especially during the night. Conference Secretariat The room for conference secretariat is located on the first floor. Please feel free to drop by if you have any problem or comment. Wireless Internet Access Free wireless internet access will be provided at the conference area. Please get the access password from the secretariat.

KEYNOTE SPEAKERS

Dr. William Chen Raj N. Master Dr. Mervi Paulasto-Kröckel President IEEE/CPMT Society Advanced Micro Devices Infineon

Rolf Aschenbrenner Dr. Karl Johnson Sow, Yeek Kooi IZM Freescale Intel

SHORT COURSE INSTRUCTORS

Prof. Dr. Kankanhalli Seetharamu Prof. Dr. Ricky Lee PES Institute, INDIA HKUST, HONG KONG

Shimamoto Haruo Luu Nguyen Renesas Technology, JAPAN National Semiconductor Corp., USA

CONFERENCE OPENING ADDRESS 5 NOVEMBER, 2008, WEDNESDAY

08:45 AM – 09:15 AM

“Engineering in the Era of Consumer Driven Markets”

Dr. William Chen

Senior Technical Advisor, ASE (U.S.) Inc. President IEEE/CPMT Society

Abstract The last decade has seen major changes in our industry. The rise of the fabless-foundry-SAT and IDM-fablite-SAT models has spawn many novel inventions and innovations with new brand names for electronic products that contributes to the USD 1.4 trillion global electronic industry. The evolutions in the technology and product supply chains have led to changes in how products are developed and engineering is done. We have seen a bifurcation of Moore law technology driving forces to More Moore and More than Moore. During the same period of time Electronic Packaging has seen a proliferation of new technology families in menu offering PBGAs, QFNs, flip chip, WLCSPs and more recently Stacked Dies, SiPs, MEMs, Sensors, Embedded Actives and Passives, TSVs, 3D Packaging, with many more to come. This changing landscape is dominated by consumer driven markets, whether they are for laptops, cell phones, smart phone/PDAs, MP3 devices, automotives, biomedical and health products. How has the practice of engineering changed? How does the packaging professional get the job done and get the newest electronic products conceptualized, designed, developed and manufactured to go out of the factory door into the hands of the masses? Biography William Chen (Bill) holds the position of Senior Technical Advisor at ASE (U.S.) Inc. Prior to joining the ASE Group, he was the Director of the Institute of Materials Research & Engineering (IMRE), located in the National University of Singapore. Previously, Bill worked for over thirty three years in various R&D and management positions at IBM Corporation, where he was elected to the IBM Academy of Technology. He is the co-chair of the International Technology Roadmap for Semiconductors (ITRS) Assembly and Packaging International Technical Working Group He holds the position of President of the IEEE Components Packaging and Manufacturing Technology Society (CPMT), and has been elected a Fellow of IEEE and a Fellow of ASME. . Bill has been an associate editor of the IEEE/CPMT transactions, and ASME Journal of Electronic Packaging, and has published extensively in the fields of microelectronics packaging and mechanics of materials. Bill held adjunct faculty appointments at Cornell University, Binghamton University, University of Washington, and a visiting faculty appointment at Hong Kong University of Science of Technology. He received his B.Sc. at University of London, M Sc at Brown University and PhD at Cornell University.

KEYNOTE ADDRESS 5 NOVEMBER, 2008, WEDNESDAY

09:15 AM – 10:00 AM

“Interdependency of Packaging, Reliability and Failure Analysis in Solving Future Packaging Challenges”

Raj N. Master Corporate Fellow

Chief Technologist Advanced Micro Devices, USA

Abstract As the demand for computing performance and density increases, the demand for packaging microprocessors is getting more complex. Computing speed and increased functionalities are achieved by reducing lithography features and increasing no. of transistors and no. metal layers. The performance is further enhanced by incorporating low K dielectric films in the die. While the semiconductor makes leaps, it creates technological challenges and in some areas approach technology barriers. In addition these evolving technical challenges are increasingly dependent on physical failure analysis to understand. This talk would summarize the challenges of bumping at reduced pitch, packaging thermo mechanical issues in packaging fragile low k films in a TCE mismatched system. Discussions on assembly challenges that result from assembling large die in laminate packages will also be described. In summary, talks would discuss the inter dependency between Silicon Technology, packaging Technology and Reliability. In addition these evolving technical solutions are increasingly dependent on physical failure analysis to understand the root cause and failure mechanisms. The talk will describe some typical failures and the solutions that could be developed by the use of physical failure analysis. Biography Raj joined AMD in 1996. At AMD, Raj is a Corporate Fellow and Chief Technologist. Corporate Fellow is the highest technical position at AMD. Raj is responsible to develop AMD strategy for C4, packaging, assembly and Thermal solutions. He was responsible to successfully transfer the IBM C4/BGA technologies to AMD and set up high volume manufacturing in Penang which has to date produced more then 300 million flip chip assemblies. He led the Organic packaging development and manufacturing which is now in high volume production. As a part of that development he was responsible to select and develop package, component and material suppliers in USA to support high volume production. He is also responsible to qualify and provide technical direction to AMD bumping and probing operations in Dresden, Germany. He led the selection and qualification of Unitive and bumping foundry and Amkor and ASE as assembly and test foundries. He provides technical guidance for equipment and processes for C4 /BGA manufacturing lines in Suzhou, Penang and Singapore. He also provides technical expertise and guidance to product lines, Failure analysis, and reliability and quality organizations within AMD. He manages advanced packaging group involved in developing strategic enabling technologies. He is also manager of the Lead Free program of AMD. Raj joined AMD after spending 21 years at IBM. He was Senior Technical Staff member at IBM prior to joining AMD. He was responsible for packaging development and manufacturing as related to C4, Ball Grid Array, Column Grid Array, Board Level Reliability and Multi Layer Ceramic Substrate. Raj has 39 U.S. patents issued to him and has published over 70 technical papers.

KEYNOTE ADDRESS 5 NOVEMBER, 2008, WEDNESDAY

10:00AM – 10:45AM

“Future Trends in Reliability Technology in Electronics”

Dr. Mervi Paulasto-Kröckel Director Package Development

Infineon Technologies AG, Munich, GERMANY

Abstract Continuous increase of functionality of electronic devices drives microelectronics assembly industry and development into major changes. Examples can be taken equally from wireless products with increasing number of supporting peripheral functions as well as automotive products such as individual safety and comfort concepts for all passengers. At the same time, cost reduction pressure and technology advances push the technology miniaturization at all levels of the supply chain. These parallel developments, integration and miniaturization, accompanied with increasing expectations on faultless operation from the end-user, set high requirements for the product reliability. This presentation deals with the most important product trends in the electronics industry and their impact on the assembly reliability. Different challenges and their implications to product functionality are shown. The necessity for enhancements in the development methods towards fundamental understanding of materials and their interactions will be discussed. The way to an effective anticipation of potential failure modes is described. Biography Dr. Paulasto-Kröckel is Director Package Development with Infineon Technologies AG in Munich, Germany. In this role she has the responsibility for the package strategy and development execution for Infineon Automotive Power products. She drives roadmapping, innovation and definition of future packages, as well as creation of strategies in package differentiation and company external cooperation. Prior to joining Infineon Technologies Dr. Paulasto-Kröckel was a Staff Principal Engineer at Motorola Semiconductor Products Sector in Munich. She has over 12 years of experience in microelectronics packaging development specifically for automotive electronics market. She holds a PhD in materials science and engineering from the Helsinki University of Technology in Finland.

KEYNOTE ADDRESS 5 NOVEMBER, 2008, WEDNESDAY

13:40 PM – 14:25 PM

“Technology Trends for Heterogeneous Integration”

Rolf Aschenbrenner Fraunhofer Institute for Reliability and Microintegration

Gustav-Meyer-Allee 25,13355 Berlin GERMANY

Abstract Advanced silicon technologies offer the possibility of integrating hundreds of millions of transistors into a single electronic component such as a microprocessor. Experts predict that the increase of components per chip will follow the well known “Moore’s law” in the next decade, too. “Microelectronics” will become “Nanoelectronics”. This trend can be characterized by “More Moore”. If electronic signal and data processing systems are focussed, nanoelectronic components will be very cost efficient due to larger wafer sizes and a high degree of miniaturization (System-on-Chip). But future multifunctional systems require not only more signal and data processing power but also interfaces to the human sensory organs and altogether functions for an interaction with the environment. Besides these, antennas, components for optical signals and data transmission as well as functions for energy conversion and storage are also needed. However, for these future multifunctional technologies in most cases the cost efficient nanoelectronic standard technologies cannot be applied. Non-electronic and often radiofrequency functions require alternative materials and special processes. This additional process steps often reduce the yield or require special process developments which result in a tremendous cost increase. Therefore pure “System on Chip (SoC)” solutions will be supplemented by “More than Moore” solutions. “More than Moore” uses standard technologies for the realization of multifunctional system technologies. Both “More Moore” as well as “More Than Moore” solutions are aiming at single component solutions. As far as technical and economical feasible these “System on Chip” or “More than Moore” solutions will be chosen. But more and more applications are asking for specific application and specific integration technologies or the flexible integration of highly complex systems containing digital and non-electronic functions. Therefore the future of Nanoelectronics will see a combination of ‘More Moore’ and ‘More than Moore’ components, combined in one package (‘System-in-Package’ or SiP). With such a SiP solution, the application benefits from a comparable level of miniaturization to that achievable with a “System on Chip” (More Moore) solution, from the enhanced functionality of “More than More” solutions and it also benefits from having each part of the system fabricated in an optimum process technology. One of the reasons “Heterogeneous Integration” concepts are gaining importance is the lower cost and risk assessment compared (in this row) to “System on Chip” (SoC) and “More than Moore” solutions. Further advantages include their shorter time to market cycle and a high degree of flexibility. This high flexibility of “Heterogeneous Integration” certainly offers the possibility to integrate “System on Chip” as well as “More than Moore” solutions, for example for subsystems.

The quota of “System on Chip” and “More than Moore” solutions in a Hetero System depends strongly on cost issues. The present status of system integration is still dominated by single-chip packaging, with the few stacked-die SiP solutions being implemented mainly using wire bonding. The most advanced substrate boards are High Density Interconnect (HDI) multi-layer boards. Unlike the integrated circuit industry, where electrical, thermal and mechanical characterization is allocated to the complete design, the chips, package and board in SiP solutions are still designed separately. This approach will not be sufficient to meet the future integration requirements of advanced SiP solutions. The very high level of miniaturization and extreme reliability required in future SiPs will mean that issues such as thermal and mechanical stress management will need to take into account everything between the point at which heat is generated and the outside of the package. It will be further complicated by integration of special functions into the package, such as sensors, actuators, RF interfaces or power supply components, which may be especially sensitive to heat, stress etc. In addition the application environment in which the SiP will ultimately be used will also need to be taken into account. To meet these challenges, new architectures will have to be developed. To reach the required level of miniaturization, it will also be necessary to develop advanced assembly and handling technologies for thin wafers and chips. The integration of nano-ICs, sensor chips, actuator components, passives and displays into 3-D architectures will require the development of new design methodologies as well as reliable ultra-thin metallic interconnect technologies. New low-cost solutions for heat dissipation and thermal and RF shielding will have to be investigated and improved thermal interfaces are required to provide adequate thermal management. In addition, improvements in design and simulation methodologies, test strategies and reliability modelling are required. This research work has to be accomplished through the common effort of technology users and technology and equipment providers, as well as the appropriate European research institutes. Biography Rolf Aschenbrenner received the B.S. degree in mechanical engineering from the University for Applied Science, Gießen, Germany, in 1986 and the M.S. degree in physics from the University of Gießen, Germany, in 1991. In 1993, he joined the Research Center for Microperipheric Technologies at the Technical University of Berlin, working in the area of electroless metal deposition. Since March 1994 he has been employed at the Fraunhofer Institute for Reliability and Microintegration Berlin (IZM) where he is presently head of the department System Integration and Interconnection Technologies. From 2000 until 2006 he was Deputy Director of the Fraunhofer Institute IZM. Rolf Aschenbrenner has served as conference and program chair in several international conferences and workshops and has worked in various advisory committees. He has authored and co-authored more than 100 articles in journals or proceedings and holds more than 14 patents in the field of microelectronic packaging. As a member of the IEEE CPMT Society Board of Governors Rolf Aschenbrenner has worked as a European representative on the Conference Advisory Board Committee, and has played an active role in the globalization of IEEE CPMT in terms of membership and chapter development. He was Technical Vice President and has recently become a Senior Member of IEEE. He currently serves as Vice President Conferences.

KEYNOTE ADDRESS 6 NOVEMBER, 2008, THURSDAY

08:30 AM – 09:15 AM

“A Vision of the Future of Packaging & Assembly Technologies”

Dr. Karl Johnson

Freescale Semiconductor USA

Abstract As the semiconductor industry continues in its pursuit for greater performance and functionality, the challenges for packaging and assembly technologies are becoming significant. Packaging and assembly technologies are being required to provide competitive capabilities that deliver the promised enhanced performance while maintaining the curve of reduced cost per function. In order to meet these expectations, packaging can not longer be thought of as a back end process largely independent of the silicon and product definition. Assembly and packaging technologies have become an integral component in the overall performance, figures of merit and cost competitiveness of these new generations of products. Further, market trends and customer expectations are moving rapidly into higher levels of system integration and system solutions with shorter times to market. This trend is moving products toward greater levels of integration, diversification and flexibility beyond the scaling of Moore’s Law. Rapid market growth in areas beyond the traditional drivers for the semiconductor industry, computer and industrial applications, into consumer applications and the commoditization of products such as cellular handsets are changing the very nature of the semiconductor industry. These consumer markets demand fast cycles of learning and time to market. The products require continuous reduction of cost, greater flexibility, reuse of subsystems and periodic refresh cycles. This presentation will discuss these new challenges. The developments and innovations in packaging and assembly to address these challenges, including system-on-chip, 3D integration, system-in-package as well as wafer level fan-in and fan-out assembly, will be addressed. Biography Dr. Johnson is a senior technical leader within the Freescale Semiconductor’s Technology Solutions Organization. His responsibilities include supporting the development and implementation of a broad spectrum of packaging advances in support of the Freescale businesses and strategy. These innovations are in areas which include analog power, RF and sensor modules, automotive applications and advanced wire bond, flip chip and “wafer level” packages. Prior to his 25 year career at Freescale, Dr. Johnson pursued an academic and research career in High Energy Experimental Physics at Lawrence Berkeley Laboratory – University of California Berkeley, University of Arizona and University of Notre Dame. Dr. Johnson’s previous Freescale (Motorola) positions included managing research and development in III-V, silicon and enabling technologies for RF, microwave and millimeter applications, as well as advanced packaging solutions.

KEYNOTE ADDRESS 6 NOVEMBER, 2008, THURSDAY

14:00 PM – 14:45 PM

“Opportunities in Microelectronic Packaging, Challenges & the Need For

Innovation”

Sow Yeek Kooi Assembly Technology Development

INTEL MALAYSIA

Abstract While you were surfing the Internet, playing your games or working on your project, did you ever wonder what kind of microprocessors are being used? How are the microchips in your computers developed and manufactured? What are the materials used to obtain a robust package? How can the materials affect the performance of devices? Wonder no more! This paper answers these questions and explains the assembly packaging of advanced microchip. The challenges and trends of high density interconnection (HDI) assembly packaging of the semiconductor industry evolved based on Moore’s Law. It also considers the challenging trends of increasing transistor numbers, I/O counts, electrical power and thermal generations. In general, the impacts of Moore’s Law are the reduction in package dimensions, enhancement in microchip features and increment of package complexity. In an attempt to provide an insight on how assembly packaging affects the performance electronic packages, this paper discusses on topics such as fine line spacing for high density, robust interconnection solder and efficient thermal interface materials for heat management. It also entails the emerging need of the system-in-package technology used for the hand-held & mobile internet devices. This exciting technology trend that drives the need for lower cost, higher performance and smaller form factor will require significant research and development effort leveraging the fundamentals of chemistry, thermal mechanic and materials science. University should continue to strengthen the basics of education and fundamentals of science to ensure students are able to adapt to this fast changing environment and capable of generating innovative solutions to meet challenges of this exciting industry. Biography Sow, Yeek Kooi is currently the Director of Intel Assembly Technology Development in Malaysia. His organization is responsible for the materials and process path-finding and the development of Intel Chipset & Ultra Mobile PC packaging technologies. Sow started his career at Intel 18 years ago as a quality & failure analysis engineer with a degree in Materials Engineering from University Science Malaysia. Over his career, he has progressed through a variety of technical and managerial roles including two international assignments in United State of America. His wide range of knowledge in high volume manufacturing industry, quality system and packaging technology provides an excellent foundation for him to lead his technology organization in meeting the dynamic changes in the semiconductor industry.

SHORT COURSES 4 NOVEMBER, 2008, TUESDAY

8:15 AM – 12:15 PM & 1:30 PM – 5:30 PM

SHORT COURSE AI & PI

“Thermal Management Of IC Packaging” (Part I and II)

Prof. Dr. Kankanhalli Seetharamu

Chair Professor, PES Institute Of Technology

INDIA

Abstract In this one day short course, you will learn about the latest developments in analysis, modeling and design at the component, board and system levels. A discussion of the current status of thermal management with special emphasis on the cooling requirements of today’s and tomorrow’s components and systems. A review of the fundamental concepts of heat transfer and the state of art in analytical and numerical approaches (like finite element method) will be given. You will learn to use these tools in solving your own electronic cooling problems. Who Should Attend Product design engineers(in telecom, consumer, power, medical, automotive and military electronics) involved with the design of electronic components, PCB’s and systems, manufacturing personnel, quality engineers packaging, electronics and design engineers reliability engineers, research and development specialists, laboratory managers, mechanical engineers, project managers, quality control managers and consultants, and also research scientists in high institution. Course Outline ? Introduction, Thermal management trends, Levels of Thermal Analysis ? Fundamentals of Heat Transfer: Conduction, Convection, Radiation and Boiling ? Package level Thermal Analysis: Package Thermal resistance, Influence of board

Mounting, A New method of Determining thermal ? Resistance of components mounted on PCB ? Heat Sink Technologies: Types of Heat Sinks, Passive and Active heat sinks, Heat Sink

selection, Heat sink attachment and interface material ? Introduction to Finite element method: One, two and three dimension problems,

Formulation, and Boundary conditions, Use of FEM in Thermal System Analysis ? Microchannel Heat sinks: Single phase and Two phase flows. Arrangement of flows. ? Heat generation and Transport in Micro and Submicro Scale ? Application of Genetic Algorithm in Electronic Cooling ? Case Study: Thermal management in Cellular Phones ? Fast Local Transient Solution to Thermal problems

Biography Kankanhally N. Seetharamu (SM’03) received the B.E. degree from Mysore University, Mysore, India, in 1960; the M.E. degree from the Indian Institute of Science, Bangalore, in 1962, and the Ph.D. degree from the Indian Institute of Technology (IIT), Madras, in 1973. He was a Professor of mechanical engineering at IIT, Madras, for almost three decades before joining USM, Malaysia in 1998 and left USM in 2004. Dr. Seetharamu was the President of IEEE CPMT Chapter of Malaysia and the Secretary/Treasurer of IMAPS Malaysia Chapter. He was responsible for starting both the IEEE-CPMT and IMAPS chapters in Malaysia. He is now currently at PES Institute of Technology Bangalore, India as a Chair Professor in Thermal Engineering. He has published 110 papers in international journals and 200 papers in international and national conferences. He co-authored Finite ElementMethod in Heat Transfer Analysis in 1996 and Fundamentals of Finite Element Method in Heat and Fluid Flow (New York: Wiley, 2004), authored Engineering Fluid Mechanics’ (New Delhi, India: Narosa, 2004), contributed a chapter on “Fundamentals of Thermal Management” in Fundamentals of Microsystems Packaging (New York: McGraw Hill). His research interest is in the areas of fluid flow, heat transfer, stress analysis, electronic packaging and FEM simulation. At present, he is engaged actively in the area of electronic packaging including micro electromechanical systems (MEMS). He is also engaged in the application of Artificial Neural Network and Genetic Algorithms to the engineering problems.

SHORT COURSES 4 NOVEMBER, 2008, TUESDAY

8:15 AM – 12:15 PM

SHORT COURSE AII

“Through Silicon Vias And Microvias For High Density Interconnect in Advanced Packaging”

Prof. Dr. Ricky Lee

Associate Professor of Mechanical Engineering Director of Center For Advanced Microsystems Packaging (CAMP)

Hong Kong University of Science & Technology HONG KONG

Abstract Microvias and build-up layers have been the major enabling technologies for high density interconnects in the past decade. Without them many advanced packages could not be materialized. In recent years, due to the development of 3D packaging and system-in-packages, the concept of “through vias” has been extended from the board/substrate level to the chip/wafer level. Through silicon vias (TSVs) have evolved to become one of the hottest subjects in microelectronics and have attracted substantial attention in the industry and academia. In principle, both microvias and TSVs are the enabling technologies for vertical interconnection in advanced packaging. This course will elaborate on the latest development and the most important research results of forming and plugging microvias and TSVs. Various fabrication processes will be presented and compared. The applications of these two levels of high density interconnection in advanced packaging will be introduced. Some related reliability issues will be addressed. Perspectives on further downscaling of vias will be provided. For professionals active in microelectronic packaging research and development, this is a timely summary of progress in all aspects of this fascinating field. The lecture contents are based on the instructor’s books, his recent research results, and interactions with the packaging and assembly industries. The scope of this short course covers overview of high density interconnect technologies, base materials for build-up layers, via forming and plugging processes, insulation/barrier/adhesion layers, characteristics of copper diffusion, various applications and reliability considerations, and future outlook. With the information provided in the lecture, the attendees will acquire an overall understanding in the design, materials, processes, and reliability issues of high density vertical interconnection in advanced packaging. Course Outline:

? Overview of high density interconnect technologies and emerging trends ? Organic substrates/PCB with sequential build-up layers ? Comparison of various board level microvia technologies ? Special high density interconnect technologies ? Forming of through silicon vias (TSVs) ? Deposition of interfacial multi-layers on the wall of TSVs ? Plugging of TSVs

? Applications and reliability issues ? Outlook on nanoscale vias

Who Should Attend This short course is intended for scientists in research institutions, faculty members and postgraduate students in universities, professional engineers and technical managers in the industries who are involved in the design, materials, processing, and assembly of high density advanced packages. Biography Ricky Lee received his PhD degree from Purdue University in 1992. Currently he is Associate Professor of Mechanical Engineering and Director of Center for Advanced Microsystems Packaging (CAMP) at the Hong Kong University of Science & Technology (HKUST). He is also appointed Chief Technology Officer of Nano & Advanced Materials Institute (NAMI) at HKUST. His research activities cover flip chip technologies and wafer level packaging, through silicon vias and 3D packaging, LED and optoelectronics packaging, lead-free soldering and solder joint reliability. Ricky has substantial publications in international journals and conference proceedings. He also owns one US patent and co-authored three books (two have been translated into Chinese). Ricky is a two-time recipient of JEP Best Paper Award conferred by ASME Transactions: Journal of Electronic Packaging (2000 & 2001). He also won the Best Paper Award of IEEE Electronic Components & Technology Conference (2004) and the IEEE CPMT Electronics Manufacturing Technology Award (2008). Ricky is very active in professional societies and international conferences. He is Fellow of IEEE, ASME, and Institute of Physics (UK). He is also elected IEEE CPMT Distinguished Lecturer. Furthermore, he serves as Editor-in-Chief of IEEE Transactions on Components & Packaging Technologies and Associate Editor of IEEE Transactions on Advanced Packaging. He also sits on the Editorial Advisory Board of two other international journals. Ricky was Chair of IEEE CPMT-Hong Kong Chapter, Member-at-large of Board of Governors and Vice-President of IEEE CPMT Society. He was also Chair of ASME-Hong Kong Section and Chair of ASME Electronic & Photonic Packaging Division. In addition, Ricky was General Co-Chair of 60th Chinese Association for Science & Technology Forum for Young Scientists (2001), General Chair of 8th International Conference on Electronic Materials and Packaging (2006), and General Co-Chair of ASME 2nd Integration & Commercialization of Micro & Nanosystems International Conference & Exhibition (2008).

SHORT COURSES 4 NOVEMBER, 2008, TUESDAY

1:30 PM – 5:30 PM

SHORT COURSE PII

“3D Packaging Technology And Advances”

Shimamoto Haruo Department Manager, Technology Development

Renesas Technology JAPAN

Abstract Electric System to realize Ubiquitous World demands several items, such as system diversion, function convergence, software explosion and so on. From the point of packaging, these mean the necessity of high volume of Memory Capacity, high speed data transmission, high pin counts in the minimum dimensions. 3D packaging makes an important roles in device innovation and SiP is one of the solution to realize. Roadmap of SiP is composed from major 3 trends, that is high density, high speed and advanced functionality. In high density trend, the chip-stack structure is mainly used wirebond technology but to realize the request of containing the larger scale system LSI in the minimum size, the flip-chip technology is also used for the bottom chip. On this trend, POP and COC (Chip on Chip) are expanding depend on increasing the number of die and bit width of the memory ICs. This chip-stacked SiP is continuously the mainstream, and road to further more stacked 3-Dimensional SiP using TSV(Through Si Via). To realize high speed and advanced functionality, not only passive device but also active device will be embedded in the SiP substrate which is called SiM(System in Module). From the point of signal propagation and power dissipation, 2-D structure still act the important role. Technology Trend of 3D Packaging by introducing Renesas products will be introduced in this short course lecture. Biography Shimamoto Haruo graduated from Osaka University, Department of Technology in the subject of Electrical Engineering in1978, and obtained his Masters Degree in March 1980. In April 1980, he joined Mitsubishi Electric, and worked in developing bump fabrication, MCM packaging and TCP. After temporary transferred to Kumamoto assembly and worked for mass production from 1994 to 1999, he started to develop package for System LSI. In 2003, he was transferred to Renesas Technology and engaged in developing SiP/BGA packaging and from 2005 onward, he is assigned on the present post to develop flip chip package and elemental assembly technology. His major achievements include SiP package development for mobile phone processor, FC-BGA development for high speed signal transmission usage and development of packaging technologies for advanced wafer process.

SHORT COURSES 4 NOVEMBER, 2008, TUESDAY

8:15 AM – 12:15 PM & 1:30 PM – 5:30 PM

SHORT COURSE AIII & PIII

“Wafer Level Chip Scale Packaging” (Part I and II)

Luu Nguyen

Senior Engineering Manager Packaging Research Group

National Semiconductor Corp. USA

Abstract Wafer Level-Chip Scale Packaging (WL-CSP) has gained momentum in the small chip arena, driven by needs for cost reduction, form factor shrinkage, and enhanced performance. This course will provide an overview of WL-CSP technology. The market drivers, benefits, and challenges facing industry-wide adoption will be discussed. The current WL-CSP configurations will be reviewed in terms of their construction, manufacturing process, and published electrical and thermal performance, together with package and board level reliability. Since the technology marks the convergence of fab, assembly, and test, discussion will also address some fundamental issues such as: ? Does it fit best with front end or back end processing? ? Will it be applicable and cost-effective for memory and other complex devices such as

ASICs and microprocessors? ? Are the current standards for design rules, package outlines, and reliability still applicable?

Extensions to higher pin count packages and other arenas such as RF, MEMS, and imaging sensors will be reviewed.

Course Outline ? Wafer Level-Chip Scale Packaging (WL-CSP) definition. ? Market drivers for WL-CSPs. ? Benefits of WL-CSPs. ? Barriers and challenges for WL-CSPs. ? Review of current WL-CSPs in the industry (standard, imaging, sensors, MEMS, etc.). ? Wafer level testing - status and challenges. ? Infrastructure service providers (bumping, testing, assembly). ? Case studies of WL-CSPs (structures, processing, applications, reliability). ? Extension of WL-CSP concept to other arenas (sensors, imaging, MEMS, etc.). ? Future trends: enhanced lead-free solder balls; large die sizes; wafer level underfill; thin

and ultra thin WL-CSP; stacked WL-CSP, MCM in "reconstituted" wafers, embedded components, etc.).

Who Should Attend The course will be useful to the following three groups of engineers and scientists: ? Newcomers to the field who would like to obtain a general overview of WL-CSP. ? R&D practitioners who would like to learn new methods for solving CSP problems. ? Those considering WL-CSP as an alternative for their interconnect systems.

Biography L. T. Nguyen is a Senior Engineering Manager in the Packaging Research Group at National Semiconductor Corp., working on various aspects of wafer level packaging, lead-free and halogen-free, thermal measurement and modeling, design-for-manufacturability, opto-electronics, printed electronics, and precision analog. He received his PhD in Mechanical Engineering from MIT, and has worked at IBM and Philips Research. He co-edited two books on packaging, and has close to 200 publications. He has over 60 patents and invention disclosures. He is a Fellow of IEEE and ASME, and a Fulbright Scholar (Finland 2002). He is currently an Associate Editor for the IEEE Transactions on Advanced Packaging, IEEE Transactions on Components and Packaging Technologies, and IEEE Transactions on Electronics Packaging Manufacturing. He was a Guest Editor for T-EPM for a special issue on Drop Testing, and T-AdvP for an issue on Wafer Level Packaging. He received two Best of Conference Awards (27th IEMT 2002 and InterPack 2005), and eight IMAPS and IEMT Best of Session Conference Awards. Other awards include the 2003 Mahboob Khan Outstanding Mentor Award from the Semiconductor Research Corporation in recognition of contributions to student mentoring, research collaboration, and technology transfer, and the 2004 IEEE CPMT Outstanding Sustained Technical Contributions Award. He has also been involved with an Engineering Council since 2002 to develop a comprehensive program to foster professional development, practical training, best practices sharing, mentoring, cross-training, and e-learning among more than 2,500 National Semiconductor engineers worldwide. These efforts were recognized with the IEEE Educational Activities Board Employer Professional Development Award (2005), the IEEE Region 6 Outstanding Corporate Engineering Community Service Award (2006), and the European Electronics Industry Awards Elektra "Investing in People" Award (2006).

CONFERENCE VENUE

COFERENCE VENUE

Parkroyal Penang The hotel offers a conference rate for IEMT2008 BATU FERRINGHI BEACH participants who are staying at the hotel. Please PENANG MALAYSIA 11100 ask for the IEMT2008 rate when you register. Malaysia

+60 4 881 1133 +60 4 881 2233

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VENUE FLOOR LAYOUT

CORPORATE SPONSORS

PAC TECH– Packaging Technologies GmbH Am Schlangenhorst 15-17, 14641 Nauen,

Germany Tel: +49 (0) 3321-4495-100 Fax: +49 (0)3321-4495-110 Email: sales@pactech.de

PAC TECH USA Inc

328 Martin Avenue,Santa Clara, CA 95050 Tel: +1 (408) 588-1925 • Fax: +1 (408) 588-1927

Email: sales@pactech-usa.com

PAC TECH Asia Sdn Bhd. 11900 Bayan Lepas, Penang, Malaysia

Tel: +60 (4) 644-0986; Fax:+60(4) 644-9987 Email: sales@pactech-asia.com

INFINEON TECHNOLOGIES (Malaysia)

SDN. BHD.(56645-D) Free Trade Zone, Batu Berendam,

75350 Melaka, MALAYSIA Tel No: (606) 2325266

http://www.infineon.com.my

Head quarters: Neubiberg, Germany

http://www.infineon.com

RESOTECH CORPORATION (M) SDN BHD8, Jalan

PJS 3/34, Taman Sri Manja, Off Jalan Klang Lama 46000 Petaling Jaya, Selangor DE, Malaysia.

Tel : +603-7784-6318 Email : resotech@streamyx.com

SAMSUNG TECHWIN CO., LTD. 10th FI.,KIPS Bidg., 647-9, Yeoksam-Dong

Kangnam-Gu, Seoul, Korea 135-980

Manufacturing Plants & Asia Pacific Sales Offices:

Carsem (M) Sdn. Bhd. - (M Site) Jalan Lapangan Terbang , P.O. Box 204,

30720 Ipoh, Perak, Malaysia Tel : +60 5 3123333 Fax : +60 5 3125333

Carsem (M) Sdn. Bhd. - (S Site)

Lot 52986, Taman Meru Industrial Estate, Jelapang, P.O. Box 380,

30720 Ipoh, Perak, Malaysia Tel : +60 5 5262333 Fax : +60 5 5265333

Carsem Semiconductor (Suzhou) Co. Ltd.

No. 408, Shen Hu Road,Suzhou Industrial Park, Jiangsu,P.R. China 215021 Tel : +86 512 6258 8883 Fax : +86 512 6258 8885

http://www.carsem.com/index.php

PLOT 534, Jalan Keluli 3, Pasir Gudang 81700 Johor, Malaysia

Tel:+607-2533500 Fax: +607-2533533 http://www.asmpacific.com

ASM Assembly

Equipment (M) SDN BHD. Bayan Point, Medan Kampung Relau

11900 Penang, Malaysia Phone: 60-4-644 9490 Fax: 60-4-645 1294

Email: inquire@asmpt.com

ASM Assembly Equipment (M) SDN BHD. Sungai Abong, 84000, Muar, Johor, Malaysia

Phone: 606-951 5713 Fax: 606-951 5786

Email: inquire@asmpt.com

SOUVENIR/OTHER SPONSORS

Freescale Semiconductor Malaysia 47300 Petaling Jaya, Selangor, Malaysia

Tel : 603-7874 1133 Fax : 603 – 7873 1389

Email: LCTan@freescale.com

ON Semiconductor SCG Industries Malaysia Sdn.Bhd.

Lot 122,Senawang IndustrialEstate, 70450 Seremban,Negeri Sembilan,

West Malaysia. Tel:06-671 2222 Fax:06-678 2262

Email: Azhar.aripin@onsemi.com

MK Electron Co., Ltd. Attn. Marketing Team / Sung J. Won

316-2 Kumeu ri, Pogok eup, Cheoin gu Yongin, Kyunggi do, KOREA

Tel : +82-31-330-1944 Fax : +82-18-277-3363

Email : sjwon@mke.co.kr

Advanced Micro Devices Phase 3, Free Industrial Zone,

Bayan Lepas 11900 Penang,

MALAYSIA Tel : 04-6433128 Fax : 04-6436307

Email: Jariyah.Hashim@amd.com

Intel Technology

Bayan Lepas FTZ, Phase 3, Halaman Kampung Jawa, 11900, Penang, Malaysia.

Tel: +6-04-253-2528 Fax: +6-04-253-5730

Email: choong.kooi.chee@intel.com

EXHIBITORS

PAC TECH, GERMANY

PAC TECH– Packaging Technologies GmbH Am Schlangenhorst 15-17, 14641 Nauen,

GERMANY Tel: +49 (0) 3321-4495-100 Fax: +49 (0)3321-4495-110 Email: sales@pactech.de

Momentive Performance Materials

Suite 9-06, Level 9, Centerpoint South, Lingkaran Syed Putra, 59200 Kuala Lumpur.

Tel: 603 9206 1555 Fax: 603 9206 1533

HP: 012-4159341 Email: Tat.Quah@momentive.com

TechSearch International Inc.

4801 Spicewood Springs Rd., Suite #150,

Austin, TX 78759 Phone: 512-372-8887

Fax: 512-372-8889 Email: becky@techsearchinc.com

Nihon Superior (M) Sdn. Bhd.

Lot 17, Jalan Industri 1, FIZ Jelepang 2, 30020 Ipoh,

Perak, Malaysia Tel no.: 05-5273792

Fax: 05-5273659 H/P: 016-5677535

Email : hbchan@nihonsuperior.com.my

WinTech Nano-Technology Services Pte.

Ltd. Tel: (65) 6777 7354 HP: (65) 9487 3566 Fax: (65) 6777 2462

Email: fuchao@wintech-nano.com

Crest Systems (M) Sdn. Bhd.

9, Jalan TK 2/1C, Taman Kinrara, Jalan Puchong,

47100 Puchong, Selangor. Tel: 603 8075 2268 HP: 012 3211 882

Fax: 603 8075 2292 Email: ryan.lee@crestsystems.com.my

NAMICS CORPORATION-SG RO 627a Aljunied Road,

#10-02 Biztech Centre, Singapore 389842 Tel: (65) 6747 3757 Fax: (65) 6747 0721

Email: alex@namics-asia.com

MYDATA ASIA PTE LTD

5, Pereira Road, #01-01, Asiawide Industrial Building, Singapore 368025.

Tel: +60 19 4706083 Fax: +65 6281 7667

Email: dwoon@pc.jaring.my

1110-1230 Session A1 – Advanced Packaging I Co-Chairs : Rolf Aschenbrenner, FRAUNHOFER INS. Dr. Haley Fu, iNEMI A1.1 1110 High Power Multi-Chip System Integration in

Package *Hubert Wieser1, Shim Kar Wei2, Anton

Kolbeck1 1Freescale Halbleiter DEUTSCHLAND GmbH 2Freescale Semiconductor (M) Sdn. Bhd., MALAYSIA

A1.2 1130 Process Development And Reliability

Evaluation For Inline Package On Package (POP) Assembly

*Jonas Sjoberg, David A. Geiger, and Dr. Dongkai Shangguan Flextronics, USA

A1.3 1150 Unique High Density Leadframe Development

for SOT23 *Zhang Jingyuan, Ruan Jianhua

Leshan Phoenix Semiconductor Co. Ltd., CHINA

A1.4 1210 Embedded Wafer Level Ball Grid Array

(eWLB) T. Meyer, *M. Brunnbauer, G. Ofner, R. Hagen

Infineon Technologies AG, D-93049 Regensburg, Wernerwerkstraße 2

1110-1230 Session B1 – Solder Joints Modeling Co-Chairs : Dr. Wei Keat Loh, INTEL Prof. Dr. Seetharamu, PES INSTITUTE B1.1 1110 Thermal Cycling Fatigue Model Development

for FBGA Assembly With Sn-Ag-based Lead-free Solder

*Fa-Xing Che, Jing-En Luan, Daniel Yap, Kim-Yong Goh, and Xavier Baraton, STMicroelectronics, SINGAPORE

B1.2 1130 Mechanics of Sn-4Ag-0.5Cu Solder Joints in a

Ball Grid Array Package During Reflow and Temperature Cycles

Lai Zheng Bo1, Nazri Kamsah1, Loh Wei Keat2 and *Mohd Nasir Tamin1

1Universiti Teknologi Malaysia , MALAYSIA 2Intel Technology Sdn. Bhd., MALAYSIA

B1.3 1150 Application of Artificial Neural Networks in

Thermal Analysis And Solder Joint Reliability Analysis Of Stacked Dies LBGA Packages

Law Ruen Ching, *Ishak Hj Abdul Azid Science University of MALAYSIA

B1.4 1210 A Mechanical Fatigue Assessment Methodology to Study Solder Joint Reliability

*Ian Chin, Shaw Fong Wong, Pramod Malatkar, Canham Rick Intel Technology Sdn. Bhd., MALAYSIA

1110-1230 Session C1 – Manufacturing Technology I Co-Chairs : Dr. Ivan Szendiuch, BRNO University Dr. Ilgu Yun, YONSEI UNIVERSITY

C1.1 1110 Achieving High Speed RFID Die Pick and

Place Operation Ron Koepp, Terry Allen, Jay Fassett, Impinj and

*Annette Teng CORWIL Technology, USA

C1.2 1130 Chip-free Singulation for Medical Application Annette Teng

CORWIL Technology, USA C1.3 1150 Screen and Stencil Printing Processes for

Wafer Backside Coating *Mark Whitmore and Jeff Schake

DEK Printing Machines Ltd., UK C1.4 1210 Characterization of Electro-Chemical Deflash

and High Pressure Water Jet through MPCpS *Marvin Picardal and Gavino Coronel

ON Semiconductor, PHILIPPINES

1110-1230 Session D1 – Material & Reliability I Co-Chairs : Tan Hong Mui, X-FAB Shutesh Krishnan, ON SEMICONDUCTOR

D1.1 1110 Radical Breakthrough Innovative Solution In

SHBI PM Optimization Using TRIZ *Nagappan Annamalai, Ninad K Patel,

Subramaniam Muthukarapan Intel Technology Sdn. Bhd., Penang, MALAYSIA

D1.2 1130 Process Development and Reliability study

with Anisotropic Conductive Film Bonding as a Replacement for Surface Mount Connectors and Hotbar Soldering

*Jonas Sjoberg, Jenson Lee, Manickavasagar Minor and Dr. Dongkai Shangguan FLEXTRONICS, USA

D1.3 1150 A Study of Lead-Free BGA Backward

Compatibility Through Solderability Testing at Component Level

*Eu Poh Leng1, Wong Tzu Ling1, Nowshad Amin2, Ibrahim Ahmad2

1Freescale Semiconductors (M) Sdn. Bhd., MALAYSIA 2Universiti Kebangsaan Malaysia, MALAYSIA

D1.4 1210 Implementation Of Novel Reflow Profile Of Various Clean And No Clean Fluxes To Enhance Flux Stability And Oxide Layer Removal Of The High Lead Solder Bump

*Nowshad Amin, Ang Ye Cheah and Zainudin Kornain Universiti Kebangsaan Malaysia, MALAYSIA

1430-1550 Session A2 – Advanced Packaging II Co-Chairs : Dr. Mervi Poulasto, INFINEON Dr. Haley Fu, iNEMI

A2.1 1430 Optimization of Ceramic Packages including Thermal Via-hole for Light Emitting Diodes

*Youngwoo Kim, Jaepil Kim, Jaebum Kim, MinSung Kim, Sungmo Park and Sangbin Song Korea Photonics Technology Institute, KOREA

A2.2 1450 Electrical Characterization of Through

Silicon Via (TSV) for High-Speed Memory Application

*Terry Hsu, Kevin Chiang, Jeng-Yuan Lai and Yu-Po Wang Siliconware Precision Industries Co, TAIWAN

A2.3 1510 An Introduction of QFN-SIP Package:

Process Challenges and Technical Issues Lee Chee How , Thong Kai Choh , Lim Kian

Guan & *Lily Khor Carsem (M) Sdn. Bhd., MALAYSIA

A2.4 1530 High Efficiency 850 nm Vertical-Cavity

Surface-Emitting Laser using Fan-Pad Metallization and Trench Patterning

*Mohd Sharizal Alias1, Paul O. Leisher2, Kent D. Choquette2 & Sahbuddin Shaari3

1Telekom Malaysia Research & Development (TMR&D), MALAYSIA 2University of Illinois at Urbana-Champaign (UIUC), USA 3National University of Malaysia, MALAYSIA

1430-1550 Session B2 – Thermal/Mechanical Modeling Co-Chairs : Prof. Dr. Mohd Nasir, UTM Dr. Wei Keat Loh, INTEL

B2.1 1430 Prediction Studies on Percolation Threshold

Behavior of Silver filled Epoxy Composite for Electrically Conductive Adhesives Applications

*Zulkarnain, M, M. Mariatti, I.A. Azid Universiti of Science Malaysia, MALAYSIA

B2.2 1450 Modeling and Process Development of Die

Edge Protection to Alleviate Thermo-mechanical Stresses on Silicon Dies in PBGA Packages

*CS Foong1, KW Shim1, Min Ding2 1Freescale Semiconductors (M) Sdn. Bhd., MALAYSIA 2Freescale Semiconductor Inc. Austin, USA

B2.3 1510 Warpage Simulation for Chip-in-Substrates *Jong Woon Kim, Ju Pyo Hong, Shan Gao, Seog

Moon Choi, Sung Yi Samsung Electro-Mechanics, KOREA

B2.4 1530 Approximate Optimum Warpage Value For

Stack-die QFN Packages *Izhan Abdullah, Ibrahim Ahmad, Meor Zainal

Meor Talib, Nur Nadia Bachok, Umizaimah Mokhtar & Asmawati E Said Universiti Kebangsaan Malaysia, MALAYSIA

1430-1550 Session C2 – Manufacturing Technology II Co-Chairs : Dr. Ivan Szendiuch, BRNO UNIVERSITY Dr. Ilgu Yun, YONSEI UNIVERSITY

C2.1 1430 Breakthrough of Laser Deflash System to

Improve Productivity Deng Bin, Shao Peng

Leshan Phoenix Semiconductor,CHINA C2.2 1450 High Speed Wafer Dicing With Ablation

Laser Cut *David Wong Chee Way, Lee Chai Ying,

Infineon Technologies Malaysia, MALAYSIA C2.3 1510 CCTO Thin Film Growth On A Cu Plated Si

Wafer By Pulse Laser Deposition At Low Temperatures

*Joseph Y. Lee, JungWon Lee, Yul-Kyu Chung, SeogMoon Choi, Jongin Ryu & BumSik Jang Samsung Electro-Mechanics Co. LTD., KOREA

C2.4 1530 TRIZ: Systematic Innovation Towards

Factory Operational Efficiency *Yeoh Tay Jin, Yeoh Teong San, Song Chia Li

Intel Technology Sdn. Bhd., MALAYSIA 1430-1550 Session D2 – Material & Reliability II Co-Chairs : Zulfikar Ali, AMD Tan Hong Mui, X-FAB

D2.1 1430 Process Development And Reliability

Evaluation Of Electrically Conductive Adhesives (ECA) For Low Temperature SMT Assembly

Jenson Lee1, *Jonas Sjoberg1, Dr. Daniel T. Rooney2, David A. Geiger2, and Dr. Dongkai Shangguan2 1Flextronics International, MALAYSIA 2Flextronics International, San Jose, USA

D2.2 1450 Nano Silica Dispersion in Epoxy: The

Investigation of Heat, Milling Speed and Duration Effect

Shereen Ong1, *J. Ismail1, M. Abu Bakar1, I. A. Rahman1, C. Stephen Sipaut1, Choong Kooi Chee2 1Universiti of Science Malaysia, MALAYSIA 2Intel Technology (M) Sdn. Bhd., MALAYSIA

D2.3 1510 Root Cause Study on Lid Adhesion Failure *M. C. Ong1, X. L. Zhao1, P. P. Joman1, J. M.

Chin1 & Raj N. Master2 1Advanced Micro Devices (Singapore) Pte. Ltd., SINGAPORE 2Advanced Micro Devices Pte. Ltd., USA

D2.4 1530 Solvent Effect on the Morphology of Copper

(I) Oxide: A Fundamental Study Towards Copper (I) Oxide-Epoxy Composites

K.Y Chew1, N.H.Mohd Hirmizi1, W.L.Tan1, *M.Abu Bakar1, J.Ismail1, L.C. Sim2 and Azmah1

1Universiti Sains Malaysia, MALAYSIA 2Intel Technology (M) Sdn. Bhd, MALAYSIA

1610-1730 Session A3 – Flip Chip Co-Chairs : Luu Nguyen, NS Dr. Uda Hashim, UNIMAP

A3.1 1610 WLCSP And Flip Chip Bumping Technologies

Andrew Strandjord1, Thorsten Teutsch1, Axel Scheffler1, *T.Oppert2, G. Azdasht2, E. Zakel2 1Pac Tech USA - Packaging Technologies, Inc. Santa Clara, CA USA 2Pac Tech GmbH - Packaging Technologies, Inc. Nauen, GERMANY

A3.2 1630 Nondestructive Method of TIM Bond-line

Measurement in Flip Chips Package *HC Heng, VS Ben, SH Chiam, AB Low,

Marshall Advanced Micro Devices Export Sdn. Bhd., MALAYSIA

A3.3 1650 Improvement on Coined Solder Surface on

Organic Substrate for Flip Chip Attach Yield Improvement

*DH Ding1, Azlina Nayan1, WS Ooi1, GH Tan1, Robert Newman2 & X Zhao3 1Advanced Micro Devices Export Sdn. Bhd., MALAYSIA 2Advanced Micro Devices, USA 3Advanced Micro Devices, SINGAPORE

A3.4 1710 Orientation Determination of Flip Chip Pb-

free Solder for TEM Application *Bernice Zee1, Xiaole Zhao1, Pin Pin Joman1,

J.M. Chin1 & Raj N. Master2

1Advanced Micro Devices (Singapore) Pte. Ltd., SINGAPORE 2Advanced Micro Devices Pte. Ltd., USA

1610-1730 Session B3 – Solder Material I Co-Chairs : Dr. Ahmed Sharif, BUET Dr. Mohd Nasir Tamin, UTM

B3.1 1610 Characteristic of Low Temperature of Bi-In-Sn Solder Alloy

*Zuhailawati Hussain1,Ervina Efzan Mohd Noor1,Ahmad Badri Ismail1, Nurulakmal Mohd Sharif1, Tadashi Ariga2 1Universiti Sains Malaysia, MALAYSIA 2Tokai University, JAPAN

B3.2 1630 Creep of Lead-free Sn-3.8Ag Solder Alloy as

Replacement of Sn-Pb Solder Used in Microelectronic Packaging

*R. Mahmudi1, A.R. Geranmayeh2, A. Torbati-Sarraf1 & A. Baradaran-Gourani1 1University of Tehran, IRAN 2Islamic Azad University, IRAN

B3.3 1650 A Comparison Study on SnAgNiCo and

Sn3.8Ag0.7Cu C5 Lead Free Solder System *Eu Poh Leng1, Dr Min Ding,1

Wong Tzu Ling1&2, Dr Nowshad Amin2, Prof Ibrahim Ahmad2, Mok Yong Lee3 and Prof. Dr. A.S.M.A. Haseeb 3

1Freescale Semiconductor, (M) Sdn. Bhd. 2Univer. Kebangsaan Malaysia, MALAYSIA 3 University Malaya, MALAYSIA

B3.4 1710 Effects of In Addition on Solidus and

Liquidus Temperatures, Microhardness, and Wettability of Sn-0.3Ag-0.7Cu Solder Alloy

Kannachai Kanlayasiri King Mongkut’s Institute of Technology Bangkok, THAILAND

1610-1730 Session C3 – Manufacturing Technology III Co-Chairs : Annette Teng, CORWIL Mark Whitmore, DEK PRINTING MACH.

C3.1 1610 Characterization of Copper Etching Process on Micro Leadless Land Grid Array (µLLGA) via Design of Experiments Approach.

*Fon Bih Wen, Kok Kee Yang ON Semiconductor (M) Sdn Bhd

C3.2 1630 Six Sigma Approach in Assembly Yield

Improvement for High Power And High Brightness LED Package For Automotive Application

*Law Ruen Ching1*, Li Zhang2, Beh Hock Yau1, Jeff Kmetec2, Desmond Tan1, Benno Spinger2, Chan Choon Earn1, Koay Huck Khim1, P. Linssen1

1Philips Lumileds Lighting Company Sdn. Bhd., Penang, MALAYSIA 2Philips Lumileds Lighting Company, USA

C3.3 1650 NGSHBI Throughput Optimization Through Innovative Solution

*Nagappan Annamalai, Choo Pak Kee, KS Yeoh, Wan Asmadi Wan Ismail Intel Technology Sdn. Bhd., MALAYSIA

C3.4 1710 Optimizing of the Cleaning Process by the

Cleaning Efficiency Investigation Vladimír Sítko1, Michal Šaffer1, *Ivan

Szendiuch2, Martin Buršík2 1Pbt Rožnov Ltd., CZECH REPUBLIC 2Brno University of Technology, CZECH REPUBLIC

1610-1730 Session D3 – Material & Reliability III Co-Chairs : Jürgen Barthelmes, ATOTECH Kamarul Zaman, FABTRONIC

D3.1 1610 Feasibility Study on Replacing Conventional Epoxy Dispensing with Wafer Back Coating Epoxy for QFN Packages for Discrete Product

*David Chong and LY Lim Fairchild Semiconductor (M) Sdn. Bhd., MALAYSIA

D3.2 1630 Intermetallic Growth and Failure Study for

Sn-Ag-Sb/Ni plated Cu in Power Package Subject to Thermal Aging

*Wedianti Shualdi1,2, Ibrahim Ahmad3, Ghazali Omar4, Aishah Isnin2 1Advanced Semiconductor Packaging (ASPAC) Universiti Kebangsaan Malaysia, MALAYSIA 2AMREC, SIRIM Berhad, MALAYSIA 3Universiti Tenaga Nasional (UNITEN) 4Infineon Technologies (Kulim) Sdn Bhd MALAYSIA

D3.3 1650 Modified Brown Oxide Treatment as an

Adhesion Promoter for Copper Lead Frame in Plastic Integrated-Circuit Packages.

*Lewis CHAN, Yiu Fai KWAN, Chun Ho YAU ASM Assembly Materials Ltd., SINGAPORE

D3.4 1710 Effect Of Surface Finish Metallurgy On

Intermetallic Compounds During Soldering With Tin-Silver-Copper Solders

*A. Ourdjini A. Ourdjini1, M.A. Azmah Hanim1,2, I. Siti Rabiatull Aisha1 and Y.T. Chin2 1 Universiti Teknologi Malaysia, MALAYSIA 2 Intel Technology (Malaysia), MALAYSIA

0920-1040 Session A4 – Wafer Level Packaging Co-Chairs : Thomas Oppert, PAC TECH Dr. Uda Hashim, UNIMAP

A4.1 0920 Important Qualification Process to Wafer Probing

YP Yee National Semiconductor Sdn. Bhd., MALAYSIA

A4.2 0940 The Effect of STI and Active Length on Dual Gate Oxide Reliability

Ng Hong Seng X-FAB Sarawak Sdn. Bhd., MALAYSIA

A4.3 1000 Current Capacity Evaluation of a Cantilever

Probe *Lester Thomas, P. Selvam, H.K. Kow

ON Semiconductor, MALAYSIA A4.4 1020 Wafer Level Packaging by Residual Stress

Evaluation using Piezoresistive Stress Sensors for the Enhancement of Reliability

*Seung Seoup Lee, Sung Wook Park, Jin Hyung Jun , Jong Yoon Lee, Jong Whan Baik, Jun Seok Kang, Jin Koo Kim, Jae Kwhang Lee, Young Do Kwon, Sung Yee Samsung Electro-Mechanics Co., Ltd., KOREA

0920-1040 Session B4 – Solder Material II Co-Chairs : Dr. R. Mahmudi, UNIV. OF TEHRAN Dr. Ali Ourdjini, UTM

B4.1 0920 A Study of Ag Micro-particle Reinforced Sn-Zn Matrix Composite Solder

Sazol Kumar Das & *Ahmed Sharif Bangladesh University of Engineering and Technology (BUET), BANGLADESH

B4.2 0940 Addresssing Industry Knowledge Gaps

Regarding New Pb-free Solder Alloy Alternatives

*Gregory Henshall, Robert Healey, Ranjit S. Pandher, Keith Sweatman, Keith Howell, Richard Coyle, Thilo Sack, Polina Snugovsky, Stephen Tisdale, Fay Hua, and Haley Fu Hewlett-Packard Co., USA

B4.3 1000 Low Temperature Electromigration and

Thermomigration in Lead Free Solder Alloy. *Mohd Foad Abdul Hamid1 & Cemal Basaran2

1University Technology Malaysia, MALAYSIA 2State University of New York, USA

B4.4 1020 The Superior Drop Test Performance of SAC-

Ti Solders and Its Mechanism Weiping Liu, Paul Bachorik & *Ning-Cheng Lee

Indium Corporation of America, USA

0920-1040 Session C4 – Wirebond & Adhesive Co-Chairs : Dr. Chandra Jayaram, INTEL Annette Teng, CORWIL

C4.1 0920 Cu Wire Bond Reliability Improvement Through Focused Heat Treatment After Bonding

Yow Kai Yun and *Eu Poh Leng

Freescale Semiconductor, (M) Sdn. Bhd. MALAYSIA

C4.2 0940 Solder Paste Jet Printing: A New Approach to Solder Paste Application

Goran Nasgarde MYDATA automation AB, SWEDEN

C4.3 1000 Viscoelastic Properties of Solder Pastes And

Isotropic Conductive Adhesives Used For Flip-chip Assembly

*R.Durairaj1, S. Mallik2, A.Seman2, A. Marks2 & N. N. Ekere2 1University Tunku Abdul Rahman, MALAYSIA 2University of Greenwich, UNITED KINGDOM

C4.4 1020 Solder Void Reduction on Solder Die Attach

For SIP-LGA *Ho Tuck Mun , Woo Eng Wah

Carsem (M) Sdn Bhd., MALAYSIA

0920-1040 Session D4 – Underfill & Mold Compound Co-Chairs : Loke Mun Leong, INTEL Jenson Lee, FLEXTRONICS

D4.1 0920 Characterization of Mold Compound to Improve Delamination Performance in Power Package

*Vegneswary Ramalingam, Azhar Aripin Y.S Won & Sariman Tasmin ON Semiconductor, MALAYSIA

D4.2 0940 Comparison of Encapsulant Curing with

Convection and Microwave Systems *T. Tilford1, K.I. Sinclair2, G. Goussetis2, C.

Bailey1, M.P.Y. Desmulliez2, A.K. Parrott1 & A.J. Sangster2

1University Of Greenwich, UNITED KINGDOM 2Heriot Watt University, UNITED KINGDOM

D4.3 1000 The Performance of Power MOSFET Devices

Encapsulated With Green and Non-Green Mold Compounds

Yeoh Lai Seng Fairchild Semiconductor Sdn. Bhd., MALAYSIA

D4.4 1020 An Approach on Underfill Material Selection

for the Low-k Flip Chip Plastic Ball Grid Array (FCPBGA)

Zainudin Kornain, Ang Ye Cheah, *Nowshad Amin and Azman Jalar National University of Malaysia, MALAYSIA

1110-1250 Session A5 – Emerging Process Co-Chairs : YK Sow, INTEL Thomas Oppert, PAC TECH

A5.1 1110 Highly efficient corrosion protection for plated pure tin surfaces

*Jürgen Barthelmes1, Sia-Wing Kok2, Din-Ghee Neoh2 & Olaf Kurtz1 1Atotech Germany, GERMANY 2Atotech SEA

A5.2 1130 Laser Grooving Process Development for

Low-k / Ultra Low-k Devices *Lau Teck Beng, Calvin Lo Wai Yew, Koh Wen

Shi, Siong Chin Teck Freescale Semiconductor Malaysia Sdn. Bhd., MALAYSIA

A5.3 1150 Non-contact Lead-frame Air Stabling Device

Applying to Plating Air Knife Process *Wang Yue, Zhang Jingyuan, Shao Peng

Leshan Phoenix Semiconductor Co. Ltd., CHINA

A5.4 1210 Direct Deposition of Thick Film Pastes to

Form Fine Line Patterns Jirí Hladík & *Ivan Szendiuch

Brno University of Technology, CZECH REPUBLIC

A5.5 1230 iNEMI BFR-free PCB Materials Evaluation

Project Report Stephen Tisdale, Roger Krabbenhoft, Gary Long,

Terry Fischer, Kostas Papathomas & *Haley Fu International Electronics Manufacturing Initiative, CHINA

1110-1250 Session B5 – Mechanical Analysis Co-Chairs : Dr. Ali Ourdjini, UTM Dr. TS Yeoh, INTEL

B5.1 1110 Characterization of Silicon Die Strength with Application to Die Crack Analysis

*Hu Guojun, Luan Jing-en & Xavier Baraton STMicroelectronics, SINGAPORE

B5.2 1130 The Next Generation of Quick Turn Method

for Interfacial Strength Testing: High Speed Ball Shear

*Chee Kan, Lee; Derek, Rebsom; Wei Keat, Loh; Hui Ping, Ng, Kam Wah, Lau Intel Technology (Malaysia) Sdn. Bhd, MALAYSIA

B5.3 1150 Warpage Measurements of Laminate Based

BGA Packges at Elevated Temperatures And Comparison With Real Board Assembly Behaviour

*Christian Birzer Christian Birzer, Markus Graml, Marc Dittes, Walter Mack Infineon Technologies, GERMANY

B5.4 1210 Determining The Tie Bar Break Point In LFCSP

Balgamel C. Lajom, *Rexel M. Macaraya & Joseph Edgar P. Noriel Analog Devices Philippines Inc., PHILIPPINE

B5.5 1230 Ink-jet Printing Process Modeling Using

Neural Networks Pyung Moon, Chang Eun Kim, Dongjo Kim,

Jooho Moon & *Ilgu Yun Yonsei University, KOREA

1110-1250 Session C5 – Material & Process Co-Chairs : Dr. Nowshad Amin, UKM DH Ding, AMD

C5.1 1110 Observation of Solder Fillers Coalescence in Resin for Development of Self-Organization Assembly Process

*Koushi Ohta, Masao Toya, Kiyokazu Yasuda, Michiya Matsushima, and Kozo Fujimoto Osaka University, JAPAN

C5.2 1130 Lead-Free Solder Ball Attach Improvement

on FCPBGA with SOP Pad Finishing *Eu Poh Leng1, Wong Tzu Ling1, Nowshad Amin

Ibrahim Ahmad2 1Freescale Semiconductor Malaysia Sdn. Bhd. 2National Univ. of Malaysia, MALAYSIA

C5.3 1150 Ultrasonic and Thermo-Compression Gold-

to-Gold Bonding of Narrow Frames for Hermetic Cavity Sealing and Electrical Interconnect

*T. Zoumpoulidis1, J. van Delft2, M. de Wild2, P.E.M. Kuijpers2, P. de Graaf2, R. Mauczok2, K. Biju2, M. Bartek1, M. Klee2 & R. Dekker1,2

1Delft University of Technology, NETHERLANDS 2 Philips Research, NETHERLANDS

C5.4 1210 Challenges And Solution In The Die Attach

Process for Micro Thin Die *Siew Han Looe, Soon Wei Wang

ON Semiconductor, MALAYSIA C5.5 1230 Process Development for Fast Cure Low

Stress Lid Adhesive for Microprocessors *Sean Too1, Jacquana Diep1 & Kee-Hean Keok2

1Advanced Micro Devices Inc, USA 2Advanced Micro Devices Export Sdn. Bhd., MALAYSIA

1110-1250 Session D5 – Delamination of IC Packages Co-Chairs : Naidu Apparavu, FLEXTRONICS Loke Mun Leong, INTEL

D5.1 1110 Package Autoclave Delamination Study by Substrate Design Improvement

*J.M. Liu & J.Z.Yao Freescale Semiconductor (China) Ltd., CHINA

D5.2 1130 Building a Delamination-free Electronic

Package Using Thermal Analysis Data Sheila Liza B. Dal

ON Semiconductor Inc., PHILIPPINES D5.3 1150 An Analysis on the Properties of Epoxy Based

Die Attach Material and the Effect to Delamination and Wire Bondability

*Wang H.T & Poh Y.C Infineon Technologies Sdn Bhd., MALAYSIA

D5.4 1210 Analysis and Characterization of Green

Compound Materials for High Voltage Application

*Serene Teh Seoh Hian, Azharsyah Mohd Yassin & Yun Sung Won ON Semiconductor (M) Sdn. Bhd., MALAYSIA

D5.5 1230 Influence of Die Adhesion Properties on

Delamination of Stacked Chip Interconnection Encapsulated in Plastic Package

*Shinji Takei1, Masaaki Koyama1, Tomoaki Goto1 & Kiyokazu Yasuda2 1Fuji Electric Device Technology Co., Ltd., JAPAN 2Osaka University, JAPAN

1450-1610 Session A6 – MEMS Co-Chairs : Dr. Kiyokazu Yasuda, OSAKA UNIV. YK Sow, INTEL

A6.1 1450 A Novel CMOS-compatible Fabrication Method For Development Of An Electrostatically Actuated Micropump

*Hing Wah Lee1, Mohd. Ismahadi Syono1 & Ishak Hj. Abd. Azid2 1MIMOS Berhad, MALAYSIA 2University Sains Malaysia, MALAYSIA

A6.2 1510 Nanowire Conductance Biosensor by Spacer Patterning Lithography Technique for DNA Hybridization Detection: Design and Fabrication Method

*Uda Hashim, Shahrir Salleh, Emi Azri Shohini Universiti Malaysia Perlis, MALAYSIA

A6.3 1530 A Knowledge Based Approach For MEMS

Fabrication Process Design Automation *Thilo Schmidt, Kai Hahn, Rainer Brück

University of Siegen, GERMANY

A6.4 1550 Capacitive Pressure Sensors based on MEMS Operating in Harsh Environments

*Yadollah Hezarjaribi1,2 , Mohad Nizar Hamidon1, Alireza Bahadorimehr1 1University Putra Malaysia, MALAYSIA 2Golestan University Iran, IRAN

1450-1610 Session B6 – Test & Design I Co-Chairs : Dr. TS Yeoh, INTEL Dr. Azizan Aziz, USM

B6.1 1450 A New Concept of Self-aligned Contact Implantation for Infineon Power Devices

Banu Poobalan1,2, *Kuan Yew Cheong1, Resch Roland2, Ung Boon Hoe2 1Universiti Sains Malaysia, Malaysia 2Infineon Technologies (Kulim) Sdn Bhd, MALAYSIA

B6.2 1510 High-speed Test Hardware Full Path

Measurement Using Low Loss PCB Substrate Errot In Maintenance: A Case Study In Electronic Packaging Industry

*Cheong Koon Ng, Ling Li Ong & Susan Chow Intel Technology, MALAYSIA

B6.3 1530 Quick Crosstalk Estimation Methodology for

Horizontal Traces in Structural ASIC and FPGA Packages.

*Wai Ling Lee, Hoon Ngik Low & Hong Shi Altera Corporation, MALAYSIA

B6.4 1550 Return Path Quality to Crosstalk in Wire-

bond Package *Siow Chek Tan, Yee Huan Yew and Hong Shi

Altera Corporation, MALAYSIA 1450-1610 Session C6 – Wirebond Technology I Co-Chairs : Dr. Klaus Muller, INFINEON Dr. Nowshad Amin, UKM

C6.1 1450 Ultra Low Loop Capability Development *Song HuaJun, Pang Qianhua, Ong Lin Huat

Leshan-Phoenix Semiconductor Co. Ltd., CHINA

C6.2 1510 Application Of Ultra Low Loop Gold Wire

Bonding Technique In Super Thin (Jedec Package Profile Height SubCode “X2”) Quad Flat No Lead Package (QFN)

*Tan Boo Wei, Wang Lei, Ken Niu, Carsem Semiconductor Co.,Ltd., CHINA

C6.3 1530 The Challenges in Automotive Low-K Fine

Pitch Bonding *Mohd Rusli Ibrahim, Au Yin Kheng & Yong

Cheng Choi Freescale Semiconductor Sdn. Bhd., MALAYSIA

C6.4 1550 Fine Pitch Cu Wire Bonding On Thin Pad Metallization

*Lau Seng Heng , L.J. Loh . Dennis C.Yborde Carsem (M) Sdn. Bhd., MALAYSIA

1450-1610 Session D6 – Cooling Solution Co-Chairs : Tim Tilford, UNIV. OF GREENWICH Dr. Jong Woon Kim, SAMSUNG

D6.1 1450 Air Cooling Augmentation in an Array of Heated Modules by Horizontal Semicircular Cylindrical Shells as Cross Flow Barriers

*S. G. Bhatta1,2 and T. R. Seetharam2 1Dr. M. G. R. University, INDIA 2P. E. S. Institute of Technology, INDIA

D6.2 1510 An Experimental Study on The Application of

Carbon Nanotubes (CNTs) as Thermal Interfacial Material in Processor Chip Testing

*Lee, Yuan Thing1 and D. Mutharasu2 1Intel Technology, MALAYSIA 2Universiti Sains Malaysia, MALAYSIA

D6.3 1530 Effects of Non-Uniform Base Heating in Multi

Stack Microchannel Heat Sinks used for Cooling High Heat Flux Electronic Chips and Devices

*Pradeep G. Hegde & K.N. Seetharamu P.E.S. Institute of Technology, INDIA

D6.4 1550 Characterization of Nickel Plated Copper

Heat Spreader with Different Catalytic Activation Process for Flip-Chip Ball Grid Array Package

*Victor Lim1, Ibrahim Ahmad1, Foong Chee Seng2 & Rozaidi Rasid1 1Universiti Kebangsaan Malaysia, MALAYSIA 2Freescale Semiconductor (M) Sdn. Bhd., MALAYSIA

1640-1740 Session A7 – Flip Chip Interconnect Co-Chairs : T. Zoumpoulidis, DELFT

A7.1 1640 Latest Developments in Bumping Technologies for Flip Chip and WLCSP Packaging

*Rolf Aschenbrenner1, Dionysios Manessis2, Andreas Ostmann1, and Herbert Reichl2

1Fraunhofer Institute for Reliability and Microintegration (IZM), GERMANY 2Technical University Berlin, GERMANY

A7.2 1700 Interconnection Via Technology And Wafer

Level Package For Crystal Unit Device *Tae Hoon Kim, Jong Yeol Jeon, Yun Pyo Kwak,

Tae Ho Kim, Yun Jung Lim, Jang Ho Park, Seong Moon Choi & Sung Yi Samsung Electro-Mechanics Co. Ltd., KOREA

A7.3 1720 Stress Evaluations in Micro Bump Structures of FCBGA

*Wan Yu Huang, Eason Chen, Jeng Yuan Lai and Yu Po Wang Siliconware Precision Industries Co. Ltd., TAIWAN

1640-1740 Session B7 – Test & Design II Co-Chairs : Thum Siew Beng, INTEL

B7.1 1640 Effective Electrostatic Discharge Detection in Equipment via EMI

*Chia-Li, Song & Teong-San Yeoh Intel Technology Sdn. Bhd., MALAYSIA

B7.2 1700 A Manufacturing Novel Approach to the

Push-Pull Sampling Methodology for Test Production

Chow Leng Kwang Intel Technology Sdn. Bhd., MALAYSIA

B7.3 1720 Serial Interface Logic Built In Self Test Methodology *Kean Hong Boey, Kok Sing Yap & Wai Mun

Ng Intel Microelectronics (M) Sdn. Bhd., MALAYSIA

1640-1740 Session C7 – Wirebond Technology II Co-Chairs : Dr. Klaus Muller, INFINEON

C7.1 1640 Optimized Conditions to make stable Free Air Ball (FAB) for Copper Bonding Wire

*S.H. Kim, H.W. Park, J.T. Moon MK Electron Co., Ltd., KOREA

C7.2 1700 Super Heavy 6.0 mils Cu Wire Ball Bonding *Tan Poh Chai, J. Premkumar, M. Sivakumar,

Joe Tan, James Song & Y. M. Wong ASM Technology, SINGAPORE

C7.3 1720 Using Ultrasonic Energy for Reducing ACF

Bonding Process Time *Tae-Young Jang1, Won-Su Yun2, Kyung-Soo

Kim1 & Soo-Hyun Kim1 1Korea Advance Institute Science and Technology, Korea 2Korea Polytechnic University, KOREA Polytechnic Univ., KOREA

1640-1740 Session D7 – Reliability Tests Co-Chairs : Tim Tilford, UNIV. OF GREENWICH

D7.1 1640 Achieving Full Fungibility and Quick Changeover By Turning Knobs In Tape and Reel Machine By Applying SMED Theory

Supramaniam Tharisheneprem Intel Technology (M) Sdn. Bhd., MALAYSIA

D7.2 1700 Failure Analysis For Copper Wire Bond

Process: A Case Study *Hasnida Abdul Samat, Shahrul Kamaruddin &

Ishak Abd. Azid Universiti Sains Malaysia, MALAYSIA

D7.3 1720 Wire Strength of Cu Wire on Al Metallization

Bond Pad After High Temperature Relaibility *Law C. S. & V. Krishna

Infineon Technology Sdn. Bhd., MALAYSIA

POSTER PAPERS

POSTER PAPER PRESENTATION SCHEDULE

Poster Paper Presentations will be held on the 5th of November at the Foyer outside the conference rooms. All poster papers will be put up on display together on the display boards. Authors of the papers are required to be present at their presentation posters at the time specified. There will be two sessions for the poster paper presentations.

DATE : NOVEMBER 5TH, 2008

10:45-11:10 SESSION A 1 Effects of Sb on SnAgCu Lead-free Solder Kuan Yew Cheong, Ng Mei Chan, Ahmad Badri

Ismail, Luay Bakir Hussain Universiti Sains Malaysia, MALAYSIA

2 A study of the process time effect to

Photosensitive Polyimides Karen H.L. Ang,1,2 Kuan Yew Cheong,1, Azmi

Abdul Malik, 2 Ghazali Omar2, Cheue Lih Lim,2 Danny Tan2, Michael B.C. Khoo2

1Universiti Sains Malaysia, MALAYSIA 2Infineon Technologies (Kulim) Sdn. Bhd. MALAYSIA

3 Development Of Human Reliablity Model For

Assessing Human Error In Maintenance: A Case Study In Electronic Packaging Industry

Izatul Hamimi Abdul Razak, Shahrul Kamaruddin, Ishak Abd. Azid Universiti Sains Malaysia, MALAYSIA

4 Increasing sensitivity using Half Cut Holes

Cantilevers Design S.M.Firdaus, Ishak Abd. Azid1, O. Sidek, K.

Ibrahim, Magdy Hussien

Universiti Sains Malaysia, MALAYSIA 5 Comparison of The Performances of

Micropump With Active Type Diaphragm Actuated By Several Approaches

Wong Wai Chi, and Ishak Hj Abdul Azid Universiti Sains Malaysia, MALAYSIA

6 Precise Control Of 8 Terminal Capacitor

Placement On Fully Populated PGA Singulated Substrate

Hafiz Habib , Ow Yong Soon Tatt Advanced Micro Devices Export Sdn Bhd, MALAYSIA

15:50-16:10 SESSION B 1 Optimization of Hot Carrier Resistance For

0.18µm CMOS Technology Sim Poh Ching, Yook Hyung Sun, Jenny Chu,

Evie Kho & Tee Pei Ling X-FAB Sarawak Sdn Bhd. MALAYSIA

2 Nonlinear Modeling of a Capacitive MEMS

Accelerometer Using Neural Network A. R. Bahadorimehr, M. Nizar Hamidon, T. S.

Hong, Y. Hezarjaribi University Putra Malaysia, 43300 Serdang, Selangor, Malaysia, MALAYSIA

3 Fabrication Of Nanoporous Polyimide Of

Low Dielectric Constant Mohd Bisyrul Hafi Othman, Zulkifli Ahmad and

Hazizan Md. Akil Universiti Sains Malaysia, MALAYSIA

4 An Approach for Exhaustive Self Testing of

LUTs in an FPGA New Chin Ee, T. Nandha Kumar

The University of Nottingham Malaysia Campus, MALAYSIA

5 Critical Assessment of Die Level Predictor

Models Melanie Po-Leen Ooi1, Chris Chan2, Su-Lyn

Lee1, Wai Loon Chin1, Ling Ying Goh1, Ye Chow Kuang1, and Serge Demidenko3 1Monash University Malaysia Campus, MALAYSIA 2Freescale Semiconductor, No. 2, Jalan SS 8/2, 47300, Selangor, Malaysia 3Massey University, Wallace Street, PO Box 756, Wellington, NEW ZEALAND

6 Variability Modeling of RF Characteristics

for Multi-finger MOSFET Using Statistical Methods

Hyuck Sang Yim, Jung Han Kang & Ilgu Yun Yonsei University, KOREA

0800 - 0900

Instructor(s)

1030 - 1045

1230 - 1330

1500 - 1515

0930 - 1700

0730 - 0820

0730 - 1730

0730 - 0810

0900 - 0915

Session Chairs : Rolf Aschenbrenner Session Chairs : Dr. Wei Keat Loh Session Chairs : Dr. Ivan Szendiuch Session Chairs : Tan Hong Mui

Dr. Haley Fu Prof. Dr. Seetharamu Dr. Ilgu Yun Shutesh Krishnan

1230 - 1340

Session Chairs : Dr. Mervi Poulasto Session Chairs : Prof. Dr. Mohd Nasir Session Chairs : Dr. Ivan Szendiuch Session Chairs : Zulfikar Ali

Dr. Haley Fu Dr. Wei Keat Loh Dr. Ilgu Yun Tan Hong Mui

Session Chairs : Luu Nguyen Session Chairs : Dr. Ahmed Sharif Session Chairs : Annette Teng Session Chairs : Jürgen Barthelmes

Dr. Uda Hashim Dr. Mohd Nasir Tamin Mark Whitmore Kamarul Zaman

0930 - 1700

0730 - 0830

0730 - 0830

Session Chairs : Thomas Oppert Session Chairs : Dr. R. Mahmudi Session Chairs : Dr. Chandra Jayaram Session Chairs : Loke Mun Leong

Dr. Uda Hashim Dr. Ali Ourdjini Annette Teng Jenson Lee

Session Chairs : YK Sow Session Chairs : Dr. Ali Ourdjini Session Chairs : Dr. Nowshad Amin Session Chairs : Naidu Apparavu

Thomas Oppert Dr. TS Yeoh DH Ding Loke Mun Leong

1250 - 1400

Session Chairs : Dr. Kiyokazu Yasuda Session Chairs : Dr. TS Yeoh Session Chairs : Dr. Klaus Muller Session Chairs : Tim Tilford

YK Sow Dr. Azizan Aziz Dr. Nowshad Amin Dr. Jong Woon Kim

Session Chairs : T. Zoumpoulidis Session Chairs : Thum Siew Beng Session Chairs : Dr. Klaus Muller Session Chairs : Tim Tilford

1550 - 1610(At Foyer outside function rooms)

1610 - 1640(At Foyer outside respective function rooms)

EXHIBITION - 6 NOVEMBER 2008, THURSDAY

1930 - 2300

Keynote Address IV: A Vision of the Future of Packaging & Assembly Technologies

Dr. Karl Johnson, Freescale Semiconductor, USA

1040 - 1110

1400 - 1445

Keynote Address II: Automotive Market Trend And Its Challenges on Package Reliability.

Dr. Mervi Poulasto, Infineon Technology, GERMANY

Coffee Breaks

(At Foyer outside function rooms)

Keynote Address V: Semiconductor Packaging Advances and Trend.

Delamination Of IC Packages

Extended Coffee Break

(At Foyer outside function rooms)

Keynote Address I: Interdependency of Packaging, Reliability and Failure Analysis in Solving Future Packaging Challenges

Raj Master, Advanced Micro Devices (AMD), USA

SHORT COURSES : 4 NOVEMBER 2008, TUESDAY

EXHIBITION - 5 NOVEMBER 2008, WEDNESDAY

CONFERENCE SESSIONS (DAY 1) : 5 NOVEMBER 2008, WEDNESDAY

Prof. Dr. Ricky Lee, Ph. DHong Kong University of Science

and Technology, HONG KONG

Shimamoto HaruoRenesas Technology Corporation,

JAPAN

3D Packaging Technology And Advances

Day 1 Speakers' Breakfast at Foyer

Guests and participants arrival into Grand Ballroom.

Welcome Speech by Azhar Aripin, IEMT2008 General Chair, ON Semiconductor

Opening speech by Penang Chief Minister, YAB Tuan Lim Guan Eng

Dr William Chen, President, IEEE/CPMT Society

Conference Opening Address: Engineering In The Era of Consumer Driven Markets

IEMT 2008 PROGRAM OVERVIEW : 4 - 6 NOVEMBER 2008

Coffee Breaks at Foyer outside respective function rooms.

Buffet Lunch at Foyer outside conference rooms.

Coffee Breaks at Foyer outside respective function rooms.

Registration at Secretariat Room, First Floor

0830 - 1730 (Inclusive of lunch and cofee breaks)

Opening Ceremony & Keynote Addresses at Grand Ballroom

Thermal Management of IC Packages Part I and II

Prof. Dr. Kankanhalli Seetharamu, Ph. D

PES Institute of Technology, INDIA

ROOM JINTAN (FULL DAY)Through Silicon Vias And Microvias For High Density Interconnect in

Advanced Packaging.

ROOM PALA (FULL DAY)Morning Session ROOM LAWANG Afternoon Session

Tabletop display outside of Conference Room

Wafer Level Chip Scale Packaging Part I and II

Luu NguyenNational Semiconductor

Corporation, USA

Registration at Secretariat Room, First Floor

Buffet Lunch at Foyer at Grand Ballroom.

ROOM JINTAN ROOM LAWANG ROOM PANDAN

SESSION D5

SESSION A4

ROOM PALA

SESSION C5

Buffet Lunch at Foyer at Grand Ballroom.

SESSION C7Wirebond Technology II

1640 - 1740

Coffee Break

SESSION B7

End of Conference

Emerging Process Mechanical Analysis Material And Process

Flip Chip Interconnect Test And Design II

ROOM JINTAN ROOM LAWANG ROOM PALA

SESSION A7

1450 - 1610 SESSION A6

ROOM JINTAN ROOM LAWANG

Wirebond Technology IMEMS Test And Design I

0830 - 0915

SESSION B6 SESSION C6

0920 - 1040

ROOM JINTAN ROOM LAWANG ROOM PALA

ROOM PALA

SESSION B4 SESSION C4Wafer Level Packaging Solder Material II Wirebond And Adhesive

ROOM PALA

SESSION A5

YK Sow, Intel Technology, MALAYSIA

SESSION B51110 - 1250

Coffee Break

Keynote Address III: Technology Trends for Heterogeneous Integration.

Dr. Rolf Aschenbrenner, Fraunhofer Institute, IZM, GERMANY

1430 - 1550 SESSION A2 SESSION B2 SESSION C2

ROOM JINTAN ROOM LAWANG

SESSION C1Manufacturing Technology I

ROOM JINTAN ROOM LAWANG

SESSION A1Advanced Packaging I

SESSION B1Solder Joint Modeling

1045 - 1110

0915 - 1000

1000 - 1045

1340 - 1425

1110 - 1230

ROOM PALA

Advanced Packaging II Thermal/Mechanical Modeling Manufacturing Technology II

Solder Material I Manufacturing Technology III

1610 - 1730

ROOM JINTAN ROOM LAWANG

Flip ChipSESSION A3 SESSION B3 SESSION C3

ROOM PALA

ROOM PANDAN

SESSION D1Material And Reliability I

ROOM PANDAN

SESSION D2Material And Reliability II

ROOM PANDAN

SESSION D3Material And Reliability III

ROOM PANDAN

SESSION D4Underfill And Mold Compound

Tabletop display outside of Conference Room

Day 2 Speakers' Breakfast at Foyer

Registration at Secretariat Room, First Floor

Dinner And Cultural Show

(Sponsored by Malaysian Tourism Department)

CONFERENCE SESSIONS (DAY 2) : 6 NOVEMBER 2008, THURSDAY

ROOM PANDAN

Reliability Tests

SESSION D6Cooling Solution

ROOM PANDAN

SESSION D7

Institute of Electrical and Electronics Engineers

33rd International Electronics Manufacturing Technology Conference (IEMT 2008) Parkroyal Hotel, Penang, Malaysia

4th – 6th November, 2008

IEEE Component, Packaging and Manufacturing Technology Society

CONFERENCE REGISTRATION FORM

A. Participant’s Information (use additional sheet if needed).

Name Designation Preferred Name on Badge IEEE Membership No.

1. ------------------------------------ ----------------------------- ---------------------------------- ------------------------------ 2. ------------------------------------ ----------------------------- ---------------------------------- ------------------------------

B. Contact Information

Organization : Dept : Tel : Fax : Mailing Address :

City/State : Zip : Country : Email :

R E G I S T R A T I O N F E E D E T A I L S PART I : CONFERENCE REGISTRATION (Please tick ( v ) on the appropriate box/boxes accordingly).

CONFERENCE ON 5th & 6th NOVEMBER 2008 (2 FULL DAYS). EARLY BIRD REGISTRATION FEE (BEFORE 8 SEPTEMBER 2008)

CATEGORIES CONFERENCE FEE SHORT COURSE FEE CONFERENCE + SHORT COURSE

[ ] SPEAKERS [ ] RM570 As below [ ] RM970

[ ] IEEE MEMBER [ ] RM700 [ ] RM500 [ ] RM1100

[ ] NON IEEE MEMBER [ ] RM880 [ ] RM600 [ ] RM1350

[ ] FULL TIME STUDENTS [ ] RM520 [ ] RM450 [ ] RM920

LATE FEE CHARGE – A late fee charge of RM100 will be imposed to all registrations that are submitted after 25 September 2008

Note: 1 Ringgit (MYR) is approximately US$0.31 TOTAL AMOUNT

? Conference registration fee on 5th and 6th November 2008 includes daily luncheons, 2 coffee breaks, program book and softcopy of proceedings downloaded in a flash drive.

? Short Course registration fee on 4th November 2008 includes one luncheon, 2 coffee breaks and a set of course notes.

PART II : SHORT COURSE REGISTRATION (Please tick ( v ) on the respective box accordingly) SHORT COURSE ON 4th NOVEMBER 2008 (1 FULL DAY)

MORNING SHORT COURSE (8:15 – 12:15 PM) AFTERNOON SHORT COURSE (1:30 – 5:30 PM)

[ ] SC AI : Thermal Management of IC Packages Part 1. Instructor : Prof. Dr. Kankanhalli Seetharamu PES Institute of Technology, INDIA

[ ] SC PI : Thermal Management of IC Packages Part 1I. Instructor : Prof. Dr. Kankanhalli Seetharamu PES Institute of Technology, INDIA

[ ] SC AII : Through Silicon Vias And Microvias For High Density Interconnect in Advanced Packaging. Instructor : Prof. Dr. Ricky Lee Hong Kong University of Science and Technology, HONG KONG

[ ] SC PII : 3D Packaging Technology And Advances. Instructor : Shimamoto Haruo Renesas Technology Corporation, JAPAN

[ ] SC AIII : Wafer Level Chip Scale Packaging Part I. Instructor : Luu Nguyen National Semiconductor Corporation, USA

[ ] SC PIII : Wafer Level Chip Scale Packaging Part II. Instructor : Luu Nguyen National Semiconductor Corporation, USA

PAYMENT DETAILS (IN MALAYSIAN RINGGIT) Registration is limited so please register early. To register, fill out registration form, and send along with check or bank draft payment. Please do not mail if previously faxed. All payment for the registration is to be made payable in Ringgit Malaysia to : IEEE MALAYSIA SECTION.

[ ] Cheque/Bank Draft Cheque/Bank Draft No : Bank Name : (Only cheque or bank draft drawn in Malaysian bank are acceptable)

[ ] Credit Card Payment Type of card [ ] Visa [ ] MasterCard

Card Holder’s Name (as it appears in the card) Signature : Credit Card Number : Card Expiry Date : / Card ID No. I hereby authorized IEEE IEMT 2008 to charge the amount of RM Date :

Special Meal Request (if any) : [ ] Vegetarian

Mail or fax registration form to : 33rd IEMT2008 Secretariat, (Attention : Dr. Cheong Kuan Yew) School of Materials & Mineral Resources Engineering Engineering Campus, Universiti Sains Malaysia, 14300 Nibong Tebal, Seberang Perai Selatan, Penang, MALAYSIA. Tel : +6-04-599 5259 Fax : +6-04-594 1011 Email : cheong@eng.usm.my Conference website : http://cpmt.ieeemalaysia.org

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About WinTech Nano WinTech is a young and dynamic organization that is at breadth with the latest cutting-edge technology and development for the Industry. Our technical specialists are well trained with years of experience and are committed to work confidentially with you to satisfy all requirements. We are proud to be your one-stop lab service provider. Our services are highly professional yet affordable; our analyses are first class yet have the shortest turnaround time in town.

Failure Analysis Services At WinTech Nano, we diagnose the IC failures you encounter during your product development and high volume manufacturing stages by conducting microstructure analysis at the specific failure locations. With our strong expertise in Failure Analysis and “can do” attitude, our staff are committed to deliver our highest analysis to your satisfaction. - Decapsulation - Fault Isolation - SEM (Scanning Electron Microscope) - FIB Cross-section - TEM (Transmission Electron Microscope)

IC Circuit Edit Services IC Circuit edit is an important tool for IC designers to achieve fast and reliable circuit verification result. Circuit edit services are done in the FIB (Focused Ion Beam). FIB with certain GIS (Gas Injection System) sources, ion beam etching speed against certain materials will be accelerated tens of times. WinTech Nano offers two types of Circuit Edit services: Circuit Modification & Signal Tap-out. We are able to perform circuit edit on decapsulated die or singulated die. WinTech Nano has experience over 1000 circuit edit cases with whole range of: Circuit Modification Signal Tap-out Material Analysis Services Surface analysis is applied to characterize the outer few atomic layers of a solid surface. Surface analysis is conducted to reveal properties such as morphology, crystal structure, adhesion, thickness, chemical activity, stress, wettability, distribution profiles, bio-compatibility. These techniques are commonly utilized to analyzed surface defects at sub-micron and nanometer scales. Combined with FIB’s precise locating and cross-sectioning capability, the application of surface analysis are well-extended to 3D materials analysis, serving a wide range of industries such as Semiconductor, Data Storage, Thin Film, Polymer and Nano Technology. At WinTech, our staff specialized in a variety of surface analysis techniques. We offer professional analytical services on various application. Based on the information you need, we can recommend the best analytical technique for your specific purposes. Our specialists will work with you in a completely confidential way to provide the analytical solution to your expectations. - AES - Auger Electron Spectroscopy - SIMS-Secondary Ion Mass Spectrometry - EDX- SEM; EDX-TEM - XPS- X-ray Photoelectron Spectroscopy - AFM - Atomic Force Microscopy - SRP - Spreading Resistance Profilometry - FTIR - Fourier Transform InfraRed Spectroscopy