Shrinking quantum chips using silicon · PDF file · 2017-03-03Multi-zone circuit...

An Angel Business Communications publication Volume 34 Issue 4 2012

Shrinking quantum chips using siliconA new approach to quantumcomputing

Shrinkingquantum chipsusing silicon

How IBM &GLOBALFOUNDRIESimprove computerchips

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Volume 34 Issue 4

CONNECTING THE SILICON SEMICONDUCTOR COMMUNITY

450mm Wafer Transition: a challengingdisruptive technology format thatopens up new opportunities and risks in semiconductors

THE TRANSITION to manufacturing semiconductors on larger wafers continues to be one of thehottest topics under discussion in the industry. Some chipmakers have committed to advancingthe transition. Intel announced that its D1X fab in Oregon and Fab 42 in Arizona will be 450mmcompatible. TSMC recently updated their outlook and plans to have 450mm pilot lines by 2016-2017, with volume production in 2018. IMEC has well-established programs focused on thechallenges posed by manufacturing with 450mm wafers and the University of Albany’s Collegeof Nanoscale Science and Engineering (CNSE) is expanding facilities to encompass 450mmtool development and other related R&D programs. The Global 450 Consortium (G450C), whichwas announced one year ago, provides a collaborative framework for GLOBALFOUNDRIES,IBM, Intel, Samsung and TSMC to jointly manage 450mm technology development within theCNSE infrastructure.

The 450mm wafer transition represents a significant industry inflection. While the top 3 chipmakers have deep pockets and will heavily invest into the new format, the equipment industryneeds to reinvent their business models to finance the enormous development costs associatedwith the new wafer size.

ASML, the largest equipment maker and provider of critical lithography technology, has allowedchip makers to get a stake in their company in order to co-finance the 450mm development.This is understandable as ASML also has to undertake the enormous financial burden ofdeveloping new EUV lithography tools. It would not be surprising to see similar new “deals” tomitigate the financial risk for the supply-chain.

The question remains what will be the impact on the other semiconductor device segments inthe “More than Moore” arena? How much “More Moore” is needed to remain competitivethere? Clearly, 450mm is not currently a priority for a variety of customer specific applicationssuch as in automotive, analog mixed signal, power devices, MEMS, etc. Nevertheless, somehigher volume products might also be attracted by the 450mm community sooner or later. Therefore, most within semiconductor ecosystem are necessarily paying attention to – andplanning for, the eventual wafer size transition as it will have widespread implications for thosethat make the transition as well as those that wait. For its part, SEMI is facilitating thedevelopment of industry standards and the flow of information throughout the supply chain withthe launch of 450 Central (www.semi.org/450), a web-based information service to help thesemiconductor industry efficiently transition to 450mm-ready solutions and keep the industryinformed of important news and perspectives on 450mm wafer processing.

By Heinz Kundert,President SEMI Europe

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Volume 34 Issue 4

CONNECTING THE SILICON SEMICONDUCTOR COMMUNITY contents

10 Shrinking quantum chips using siliconA research team from the University of Bristol,UK, has developed a new approach to quantum computing.

11 How IBM & GLOBALFOUNDRIES improve computer chips A refined method developed at the National Institute of Standards and Technology (NIST) for measuring nanometre-sized objects may help computer manufacturers more effectively.

14 Making ring oscillator measurementsIn the world of CMOS wafer parametric testing,the ring oscillator is one of the more important test structures because its test data helps confirm that logic gates are meeting their speed design criteria.

19 Vacuum pump selection for advanced chip packagingAdvanced semiconductor packaging techniques are employed that move beyond simple wire bonding of a single die.

22 SEMICON Europa: a marketplace for visionariesEurope’s largest and most important show for the semiconductor manufacturing industry begins this month.

28 Future trends in PCB productionWhat key trends will shape the future of PCB production?

32 Integrated photonics design flow automationBy creating generic technology platforms for development and manufacturing of Photonic Integrated Circuits, huge savings can be made.

industry & technology

news

3228

06

08 08

06

06 imec: electronics stretches like skin

06 Fujitsu shifts LSI facilities to J-Devices

08 Veeco IBD system slashes defects in EUV mask blanks

08 Samsung invests In Voltaix to advance semiconductor technology

08 Foundries boost Fab equipment spending in 2012

09 SEMI: Equipment spending plummets 13 percent

09 Creating a low-noise chip-based optical wavelength converter

09 Foundries boost 2012 spending

22

1910

Contents SIS v1.qxp 27/9/12 10:24 Page 5

imec: electronics stretches like skinRESEARCH institute imec has integratedan ultra-thin, flexible chip with bendableand stretchable interconnects into apackage that adapts dynamically tocurving and bending surfaces.

The resulting circuitry can be embedded inmedical and lifestyle applications whereuser comfort and unobtrusiveness is key,such as wearable health monitors or smartclothing.

At the 2012 ESTC conference (ElectronicsSystem Integration TechnologyConference) in Amsterdam, theresearchers will present their results andshowcase their latest demonstrations.Today, most electronic appliances are rigidand mechanically flexible. A growingnumber of applications, however, requireelectronics that dynamically adapt tocurving and bending surfaces.

For example, biomedical systems such asunobtrusive, wearable health monitors(e.g. electrocardiogram or temperaturesensors), advanced surgical tools, orconsumer electronics such as mobilephones embedded in smart textiles areneeded.

Imec’s associated lab at the University ofGhent has pioneered this technology andis inviting industrial partners to join theR&D program.

For the demonstration, the researchersthinned a commercially availablemicrocontroller down to 30µm, preservingthe electrical performance andfunctionality. This die was then embeddedin a slim polyimide package (40-50µmthick).

Next, this ultrathin chip was integrated withstretchable electrical wiring. These wererealised by patterning polyimide-supportedmeandering horseshoe-shaped wires, atechnology developed and optimised atthe lab.

Finally, the package was embedded in anelastomeric substrate, e.g.polydimethylsiloxane (PDMS). In thissubstrate, the conductors behave as twodimensional springs, enabling greaterflexibility while preserving conductivity.

“Future electronic circuitry will stretch andbend like rubber or skin while preservingits conductivity,” says Jan Vanfleteren,responsible for the research on flexibleand stretchable electronics at imec’sGhent lab.

“This breakthrough achievementdemonstrates that flexible Ultra-Thin ChipPackages (UTCP) can be integrated withstretchable wiring, paving the way towardfully flexible applications. We anticipate thefirst appliances will be used in intelligentclothing, with medical applicationsfollowing later. Once commercial productsare introduced, I expect to see clothingwith signalisation by using LEDs andsensors to track movements.”

This research is supported by the Agencyfor Innovation by Science and Technologyin Flanders (IWT) through the SBO-BrainSTAR project.

Fujitsu shifts LSI facilities to J-Devices

FUJITSU SEMICONDUCTOR LIMITED willtransfer ownership of its Large ScaleIntegration (LSI) assembly and testfacilities belonging to its fully ownedsubsidiary, Fujitsu IntegratedMicrotechnology Limited (FIM), to J-Devices Corporation.

The objective of the agreement is for thetwo companies to build a long-term,mutually beneficial strategic partnership inthe semiconductor manufacturingbusiness.

It is expected that a conclusive agreementwill be signed and the transactioncompleted by the end of this year. FujitsuSemiconductor has been striving toenhance its business foundation andimprove corporate management bypursuing a unique “fab-lite” businessmodel, as announced in 2009. As part ofthese efforts, the company has beenoptimising its manufacturing resources inaccordance with changes in the economicand business environment.

As one of Japan’s largest independentcompanies devoted to semiconductorassembly and test operations forcustomers, J-Devices believes that, tofurther expand its business, it must becost-competitive with business rivalsbased outside of Japan. To that end, J-Devices believes it is of the utmostimportance to extend the scale of itsoperations.

The ownership transfer of the assemblyand test facilities, therefore, is in line with the business objectives and views of both Fujitsu Semiconductor and J-Devices, leading to the signing of theagreement. By the end of this year,ownership of FIM’s Miyagi Plant and AizuPlant is scheduled to be transferred to J-Devices, which will then take over theoperation of these manufacturing facilities.

All employees of the two plants areexpected to be transferred to J-Devices. In addition, FIM plans a staged transfer ofequipment from its Kyushu Plant to J-

Devices facilities also located in Kyushu,and ultimately will transfer all of itsmanufacturing capability. After the transferis complete, the manufacturing currentlyconducted at FIM’s Kyushu Plant will takeplace with the same standards for qualityat J-Devices’ facilities. Employees of FIM’sKyushu Plant are scheduled to betransferred to J-Devices or reassignedwithin the Fujitsu Group.

The products that are currently beingmanufactured at the assembly and testfacilities to be transferred will be producedby J-Devices and will continue to besupplied to customers through FujitsuSemiconductor.

6 www.siliconsemiconductor.net Issue IV 2012

news � review

News SIS v1.qxp 27/9/12 10:19 Page 6

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Untitled-1 1 27/09/2012 11:14


news � review

Veeco IBD system slashes defectsSEMATECH, a global semiconductorconsortium that conducts research anddevelopment to advance chipmanufacturing, has recently achieved amajor breakthrough using Veeco’s NEXUSLow Defect Density Ion Beam Deposition(LDD IBD) System to significantly reducedefects from multi-layer deposition ofmask blanks used for extreme ultravioletlithography (EUVL).

Frank Goodwin, Manager of SEMATECH’sMask Blank Defect Reduction program,stated, “EUVL requires a low defectdensity reflective mask blank, which isconsidered to be one of the top two criticaltechnology gaps for commercialisation ofthe technology. Veeco’s world-class IBDtechnology was a major catalyst in helpingus to demonstrate low defect levels for thedeposition of critical films, and meet the 22nm defect requirements for EUV maskblanks.”

Vivek Vohra, Veeco’s Vice President andGeneral Manager, Veeco Ion BeamEquipment, added, “Veeco’s NEXUS LDDIBD System has continuouslydemonstrated the ability to provide lowdefect density deposition and precisecontrol, which are required to acceleratethe development of mask blanks used forextreme ultraviolet EUV, bringing thattechnology a step closer to high-volumemanufacturing. We congratulate theresearch team at SEMATECH for reachingthis milestone and for achieving it on ourproduction-proven system.”

Ion beam deposition tools are used in thefabrication of EUV masks. The nanometre-scale patterns on masks are projectedonto a semiconductor wafer to define achip. A single mask may be used to printover 6 million chips during its life, requiringstrict mask defect control.Advanced-technology EUV masks are

used to define chips with smallergeometries, which results in improvedpower and performance as required for anincreasing number of mobile devices.Veeco says its IBD products enable highfilm quality, featuring extremely lowparticulate deposition and precise controlof optical properties for single or multi-layer processes, two critical factors for producing advanced EUVphotomasks.

Samsung invest in Voltaix to advancesemiconductor technologyVOLTAIX, a provider of materials thatenhance the performance ofsemiconductor chips and other electronicdevices has secured growth financing from Samsung Venture InvestmentCorporation (SVIC), the global investmentarm of Samsung.

Both companies have remained tight-lipped about the amount invested.Voltaix manufactures electronic chemicalsand gases used in semiconductormanufacturing processes at majorintegrated circuit fabs worldwide.

“The financing from SVIC will enable us to continue building our worldwideinfrastructure and will further accelerateour new product pipeline developmentactivities,” says Peter Smith, CEO ofVoltaix.

“We believe our materials innovations willhelp drive new device architectures andmanufacturing technologies to highvolume manufacturing,” Smith adds.

Dong-Su Kim, SVIC Senior InvestmentDirector notes, “The increasing demandfor novel gases and materials inelectronics fabrication has attracted our

attention. Based on our analysis of thefuture demand and the players in thespace, we found Voltaix to be the leaderand are quite excited about our equityinvestment.”

The firm manufactures specialty materialsthat enhance the performance andmanufacturability of semiconductors.Voltaix produces specialty materials thatenhance the performance andmanufacturability of semiconductors.

The firm specialises in a number of areas.These include enhancing advanced DRAMcomputer memory, strained silicon for highspeed logic computer chips (CPUs) andcopper-enabling low-K dielectrics for logicand memory chips.

ADEPT TECHNOLOGY, INC. has deployedan initial batch of mobile robots to a majorsemiconductor manufacturer for theautomated transport of semiconductorpods.

“Adept is very pleased to have begunintroducing mobile technology to thesemiconductor and cleantech spacethrough this initial production deploymentwith such a large and respected client,”said Rush LaSelle, vp and generalmanager of mobile robots. The use ofautomated guided vehicles (AGVs) hasbeen explored by semiconductor fabs fordecades, but such robots have so far notbeen utilised very much. This is mainlydown to the inherent nature of traditionalAGVs which have lacked navigationalflexibility and ease of installation. Adept’sindoor navigation technology and smallplatforms function well within crowdedenvironments and allow for non-disruptiveinstallation in sensitive facilities. Adept’snewly released SPC-4200 and SPH-2200transporters are used to carry pods fromone machine tool to another (intra-bayloading) and between various processareas within the fab (inter-bay transfer).The pods are enclosed in plastic boxesthat encase a set of semiconductor wafers

Foundry selectsAdept robots



news � review

Foundries boost2012 spendSEMI’s World Fab Forecast databaseindicates that the total fab spending forequipment needed to ramp fabs,upgrade technology nodes, andexpand or change wafer size couldincrease 16.7 percent in 2013 to reacha new record high of $42.7 billion.

The estimate includes new equipment,used equipment, or in-houseequipment but excludes test assemblyand packaging equipment. The latest edition of the forecast listsover 1,150 based facilities and includes850 silicon based plants, with 76facilities starting production this yearand in the near future. Since theprevious publication in May 2012, SEMIanalysts have added 296 fabs to morethan 230 facilities, into the database.This includes 244 silicon fabs.Semiconductor manufacturingfoundries were significant drivers of fabequipment spending in 2012 with over$10 billion combined investment. Theirdominance is expected to continue withapproximately $10 billion additionalequipment spending in 2013. In 2012,the Americas dominated fabconstruction. From 2010 to 2012, over$6 billion will be spent on fabconstruction projects in this region, ledby Intel, Samsung, Globalfoundries,and Micron. Most of these constructionprojects will be completed by the endof 2012. No immediate new fab projectsin the Americas are anticipated,resulting in projected investment for2013 construction to drop below $500million from almost $3 billion in 2012. The situation is set to change In 2013,however, with most fab constructionexpected occur in Taiwan, China, andKorea. Samsung has begun anaggressive conversion of up to fourexisting Memory lines to System LargeScale Integration (LSI). A transition fromFlash to System LSI is difficult; somedrop in capacity in Memory is expected,but the company is expected tocompensate by building a new fab forMemory, in Xian, China, with awhopping investment of $7 billion. Thefab is expected to begin construction inmid-September 2012. Other increasesin fab construction investment will comefrom SMIC’s new fab in Beijing, andTSMC and UMC fab projects in Taiwan.

SEMI equipment spendingplummets 13 percentSEMI has reported that worldwidesemiconductor manufacturing equipmentbillings reached US$ 10.34 billion in thesecond quarter of 2012.

The billings figure is 4 percent lower thanthe first quarter of 2012 and 13 percentlower than the same quarter a year ago.

The data was gathered jointly with theSemiconductor Equipment Association ofJapan (SEAJ) from over 100 globalequipment companies that provide dataon a monthly basis.

Global semiconductor equipmentbookings were $9.70 billion in the secondquarter of 2012. The figure is 10 percentlower than the same quarter a year agoand 4 percent lower than the bookingsfigure for the first quarter of 2012.

The quarterly billings data by region inmillions of U.S. dollars is shown in the

graph above and shows that apart fromthe rest of the world (ROW), Taiwan wasthe only country to increase spending onsemiconductor equipment in the secondquarter this year as compared to Q1 2012.

Year-over-year, Japan and China cut theirspending from Q2 2011 to Q2 2012 by 48percent and 44 percent, respectively whileEurope slashed its spending by a massive56 percent.

Researchers from the NIST Centre forNanoscale Science and Technology havedemonstrated a low-noise device forchanging the wavelength of light usingnanofabricated waveguides created on asilicon-based platform using standardplanar fabrication technology.

Optical wavelength conversion is animportant resource for applications in bothclassical and quantum informationprocessing; it can connect physicalsystems operating at differentwavelengths, and facilitate improved lightdetection by converting light towavelengths for which highly sensitivedetectors are available.

However, for many such applications theconversion process must not introduceadditional noise.

Now researchers at NIST havedemonstrated noise-free wavelengthconversion using silicon nitride (SiN)waveguides fabricated on a siliconsubstrate. These waveguides weredesigned based on electromagnetic

Creating a low-noise chip-basedoptical wavelength converter

simulations to determine an appropriatedevice geometry for a process called four-wave-mixing Bragg scattering, where aninput signal field is converted to an outputfield whose frequency is shifted from theoriginal by an amount equal to thedifference in the frequencies of twoapplied pump fields.

Measurements show conversionefficiencies in these devices as high as afew percent, approaching the levelsneeded for some applications, and with noexcess noise added during the conversionprocess. These new noise-free frequencyconverters are dramatically smaller thanthe nonlinear crystals and optical fibresused in previous work (by several ordersof magnitude), and can be created inarrays and integrated with other on-chipdevices using scalable silicon-basedfabrication methods.

The scientists say that in the future, theywill focus on increasing the conversionefficiency levels by optimising thewaveguide geometry and incorporating the waveguides into optical resonators.



news � analysis

Shrinking quantum chipsusing siliconA research team led by scientists fromthe University Of Bristol, UK, hasdeveloped a new approach toquantum computing that they saycould lead to the mass-manufacture ofnew quantum technologies.

Scientists from University of Bristol, UK, Centre forQuantum Photonics have developed a silicon chip that

will pave the way to the mass-manufacture of tiny quantum chips.

The announcement was made at the launch of the 2012 BritishScience Festival in September. Conventional semiconductortechnology is largely based on crystalline silicon which is anindirect bandgap semiconductor. This means it is inefficient atemitting light compared to materials such as gallium arsenide andindium phosphide, which have a direct bandgap. These lattermaterials are compound semiconductors and are widely used inoptoelectronics.

Now that optoelectronics is becoming increasingly important forinformation and communication technologies, there is a need todevelop optoelectronic devices that can be integrated withstandard microelectronics. The leap from using glass-basedcircuits to silicon-based circuits is significant because fabricatingquantum circuits in silicon has the major advantage of beingcompatible with modern microelectronics. Ultimately theresearchers believe this technology could be integrated withconventional microelectronic circuits, and could one day allow thedevelopment of hybrid conventional or quantum microprocessors.

Now the research team led by the University of Bristol hasdeveloped quantum chips from silicon. However, unlikeconventional silicon chips that work by controlling electricalcurrent, these circuits manipulate single particles of light(photons) to perform calculations.

These circuits exploit strange quantum mechanical effects such assuperposition (the ability for a particle to be in two places at once)and entanglement (strong correlations between particles thatwould be nonsensical in our everyday world). The technologydeveloped uses the same manufacturing techniques asconventional microelectronics, and could be economically scaledfor mass-manufacture. These new circuits are compatible with

existing optical fibre infrastructure and are ready to be deployeddirectly with the internet.

Mark Thompson, Deputy Director of the Centre for QuantumPhotonics in the University’s Schools of Physics and Electrical &Electronic Engineering, said, “Using silicon to manipulate light, wehave made circuits over 1000 times smaller than current glass-based technologies. It will be possible to mass-produce this kindof chip using standard microelectronic techniques, and the muchsmaller size means it can be incorporated in to technology anddevices that would not previously have been compatible withglass chips. This is very much the start of a new field of quantum-engineering, where state-of-the-art micro-chip manufacturingtechniques are used to develop new quantum technologies andwill eventually realise quantum computers that will help usunderstand the most complex scientific problems,” he continued.

Along with recent demonstrations from the Bristol research groupand other groups showing on-chip generation of photonics qubitsand results from the US showing on-chip detection of singlephotons, the Bristol-lead research team now believes that all thekey components are in place to realise a fully functioningquantum processor - a powerful type of computer that usesquantum bits (qubits) rather than the conventional bits used intoday’s computers.

Quantum computers will have unprecedented computationalpower for tasks including search engines and the design of newmaterials and pharmaceuticals. This work, carried out withcollaborators including Heriot-Watt University in Scotland and DelftUniversity in the Netherlands, is an essential step towards theminiaturisations of quantum technologies.

© 2012 Angel Business Communications. Permission required.

LabFab Bristol & IBM v1.qxp 26/9/12 16:51 Page 10


news � analysis

The process, which makes use ofmultiple measuring instruments and

statistical techniques, is already drawingattention from the semiconductor industry.According to NIST scientist Richard Silver,“IBM and GLOBALFOUNDRIES havealready begun developing the techniquesince we first described it at a 2009conference, and they are improving theirmeasurements using this hybridapproach.”

The image above, showing a tiny siliconpillar measuring less than 100 nm alongany of its sides, is the sort of computer chip feature thatmanufacturers can now measure more precisely with NIST’shybrid metrology method. This information can reduce thenagging uncertainties that have long plagued industry’smeasurement efforts.

Nothing in life is certain except maybe death and taxes, but in theworld of computer chip manufacturing, uncertainty is a particularlyannoying issue, especially when measuring features smaller thana few dozen nanometres. Precision and accuracy are essential tocontrolling a complex and expensive manufacturing process toensure the final chips actually work.

But features on modern chips are so tiny that optical microscopescannot make them out directly. Metrologists have to use indirectmethods, like “scatterometry” to deduce their shape fromsampling the pattern light creates as it scatters off the features’edges. When this isn’t enough, there’s atomic force microscopy(AFM). It’s expensive and slow, but it can give distinctmeasurements of the height and width of a nanoscale object whilelight scattering occasionally has trouble distinguishing betweenthem.

Even with these measurement techniques, however, there’salways a nagging margin of error. “Maybe scatterometry tells youthe width of an object is 40 nanometres, but it’s plus or minusthree nanometres, a relatively large variance,” says NIST scientist

Richard Silver. “Making things worse,the total uncertainty usually increaseswhen measurement techniques arecombined, making our vision evenhazier.”

What the NIST team needed was amore precise yet less expensivemethod of measuring what sits on achip, and their answer has turned out tobe a combination of scanningtechniques and statistical analysis.They first created a library of simulateddata based on typical chip feature

dimensions to which they can compare their actualmeasurements, made with AFM, scatterometry and other means.

A complex statistical analysis of library values is then comparedwith actual measurements to extract valid measurement values,but this is often at a cost of high uncertainty. But NIST statisticianNien Fan Zhang found an elegant way to use a statistical methodcalled Bayesian analysis to incorporate a few key additionalmeasured values from other tools into the library model beforeperforming the comparison.

In doing so, the team was able to reduce the uncertainty in someof the measurements, lowering them by more than a factor ofthree in some cases. This approach is expected to be essentialwhen measuring complex three-dimensional transistors 16 nm insize or smaller in the near future.

The math wizardry is a little counter-intuitive. “In essence, if you’vegot a really small uncertainty in your AFM measurement but a bigone in your optical measurements, the final uncertainty will end upeven smaller than either of them,” says Silver.

The hybrid method has been described in detail in the paper,“Improving optical measurement uncertainty with combinedmultitool metrology using a Bayesian approach,” by N.F. Zhang etal, in Applied Optics, Vol. 51, No. 25. Sept. 1, 2012. DOI:http://dx.doi.org/10.1364/AO.51.006196

How IBM & GLOBALFOUNDARIESimprove computer chips

A refined method developed at the National Institute of Standards andTechnology (NIST) for measuring nanometre-sized objects may helpcomputer manufacturers more effectively size up the myriad tiny switchespacked onto chips’ surfaces.

LabFab Bristol & IBM v1.qxp 26/9/12 16:51 Page 11

Exhibition TechARENA 1 TechARENA 2 ConferencesRegister now online! Free Participation - Hall 1 Free Participation - Hall 2 MEMS, Test, Packaging

Monday 8 October

International MEMS/MST Industry ForumNew Dynamics in the MEMS Industry

Tuesday 9 October Exhibition

10:00 – 17:00

Show Floor Highlights:- Science Park- Secondary Equipment and Services Pavilion- MEMS, Test and Packaging Pavilion- PE2012 Exhibition

New Materials Session Packaging SessionExhibitor Presentations

PE 2012Exhibitor Presentations


MEMS Exhibitor Presentations

Advanced Process Control (APC) and Manufacturing

Secondary Equipmentand Technology Session

Advanced Packaging Manufacturing ConferencePackaging Solutions for the New Technologies

Wednesday 10 October Exhibition

10:00 – 17:00


Test Exhibitor Presentations

Market Briefing

Workshop on EquipmentAssessment & Equipment Performance Improvements


Metrology, Process Control, Automation and Software

IC Industry Awardsby SiS SILICON SEMICONDUCTOR

14th European Manufacturing Test Conference (EMTC)Overcoming New Test Challenges through Cooperation and Innovation

Thursday 11 October Exhibition

10:00 – 16:00


3D IC Session Lithography Session 14th European Manufacturing Test Conference (EMTC)Overcoming New Test Challenges through Cooperation and Innovation

LED / SSL Session

Programs and Events: 8-11 October 2012Exhibits: 9-11 October 2012 Messe Dresden, Germany

Event Schedule

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PV Equipment InterfacePV Wafer TraceabilityPV AutomationInternational MEMS/MST

Industry ForumNew Dynamics in the MEMS Industry

16th Fab Managers ForumNetworking Evening


16th Fab Managers ForumConference

Press Conference PV RibbonPV Silicon Materials


6th Executive Summit and Reception

SAXONY! - Get Together

Plastic Electronics Conference Plenary SessionParallel Sessions- OLED’s for Displays and Lighting- Flexible and Organic PV- Integrated Smart Systems

Photovoltaic MaterialsEquipment Automation


SPECTARIS-ForumTrends in Semiconductor Processing and Market Environment for the Photonics Industry (organized by SPECTARIS)

Third European Cluster Forum Plastic Electronics ConferencePlenary Session

Equipment AutomationSilicon WaferGases and ChemicalsEHS

Market BriefingTechARENA I


Plastic Electronics Conference Parallel Sessions- OLED’s for Displays and Lighting- Flexible and Organic PV- Integrated Smart Systems

Silicon WaferGases and ChemicalsEHS

450mm Session Progress in 450mm


450mm Session Progress in 450mm

SEMI Members and Exhibitors Breakfast

Plastic Electronics ConferenceParallel Sessions- OLED’s for Displays and Lighting- Flexible and Organic PV- Integrated Smart SystemsPlenary Session

Compound Semiconductor Silicon WaferHB-LED

Compound Semiconductor HB-LED


test � techniques

A growing number of semiconductorfabs are incorporating ring oscillators

into their overall process control monitoring teststructures. Frequency measurements on ringoscillator structures are used to determine gatepropagation delay, one of the critical parametersthat determine how quickly a digital circuit canoperate. Every logic gate has input capacitance, sono device can switch instantaneously because theinput capacitance limits the speed at which a gatecan switch. However, this gate propagation delay istoo short for most test equipment to measuredirectly, so test systems measure oscillation

frequency instead and the gate propagation delay iscalculated from this frequency measurement. In a CMOS fabrication process, a ring oscillator teststructure is typically designed and constructed withan odd number of inverter stages. Rather than celllibraries or gates, a ring oscillator test structure isusually constructed from transistors in order toensure an accurate representation of theparameters of interest.

The structure is designed to be as compact aspossible to ensure that its performance isdominated by the transistors rather than by theinterconnects. The device channel length of thetransistors is usually the minimum length that theprocess design rules will support.

Figure 1a is a high-level schematic view of a typicalring oscillator circuit; Figure 1b is a block diagramof a ring oscillator.

The ring oscillator shown in Figure 1a (like all ringoscillators) consists of an odd number of inverterstages. The input can consist of a 2-input NANDgate that can serve as an externally controlledtrigger. Once triggered, the ring oscillator will free-run at a frequency that’s dependent on thepropagation delay between the stages.

Because the ring oscillator will natively oscillate at afrequency much higher than a typical parametrictest system can measure directly, the output of thetest structure is usually isolated with a buffer (inorder to deal with the effects of test systemcapacitance) and its output signal divided using a

In the world of CMOS wafer parametric testing, the ring oscillator is one of themore important test structures because its test data helps confirm that logicgates are meeting their speed design criteria. Dave Rose, Senior Staff Engineer,Keithley Instruments, Inc discusses techniques for testing these devices usingautomated parametric testers.

Making Ring OscillatorMeasurements

Figure 1. Schematic(a) and blockdiagram (b)representation of aCMOS ring oscillator(without trigger orbuffer stage)

Keithley Silicon Semiconductor v1.qxp 26/9/12 16:14 Page 14


test � techniques

D-type flip-flop by a factor of 256 (or as high as1024 for processes 0.25_m or smaller). Themeasured frequency (after the signal is divided) istypically on the order of 1-50MHz.

Given that the oscillation frequency is what’s beingmeasured but the propagation delay is the actualparameter of interest, the next step is to calculatethe propagation delay from the frequencymeasurement using this equation:

where: n is the number of inverter stages andfosc is the measured frequency of oscillation

Measurement considerationsParametric test systems have always beenoptimized to perform accurate, low-level DCmeasurements. However, AC performance for thesesystems is also important for supporting C-Vmeasurement, pulse generation, and frequencyanalysis of ring oscillator structures.

The Model S530 Parametric Test System, forexample, has been designed to provide highaccuracy DC measurements over a broad dynamicrange and with an AC signal bandwidth of 20-30MHz. A frequency counter is often thought of asthe best instrument for measuring frequency.

However, given that frequency counters countcrossings (through zero, etc.), they can oftenproduce erroneous readings in situations where thesignal has to be extracted from a noisy ACenvironment. That’s why frequency measurementsare often best performed using a spectrum analyzeror an oscilloscope using spectrum analysistechniques.

Spectrum analyzers operate by converting a signalfrom the time domain to the frequency domainusing Fourier analysis. Each frequency in thesignal’s spectrum is plotted versus its signalamplitude (Figure 2). That means, in a noisy signalenvironment, the signal of interest is often the onewith the highest amplitude. Of course, in someinstances, even spectrum analysis fails, such aswhen the amplitude of the signal of interest is belowthe noise floor of the system.

Frequency Measurement SoftwareLike many frequency measurement solutions, the S530’s frequency

measurement option supports a variety of measurement commands:

ring_max Detects the frequency with the highest amplitude.

ring_ref Detects the frequency that is closest to the specified reference frequency.

ring_Icc Detects the 5 frequencies whose amplitudes are larger than the specified threshold.

ring_meas Determines the ring oscillator frequency and amplitude.

freq_init Initializes the oscilloscope card to its default state.

freq_setup Sets the start frequency and end frequency of the scan as well as the resolution bandwidth.

freq_measure Measures the frequency and amplitude of the strongest signal.

freq_measure_next Measures the frequency and amplitude of the next strongest signal as compared to the measurement returned by the freq_measure command.

freq_detect_peaks Returns the frequencies and amplitude of the specified number of peaks.

freq_selftest Places the oscilloscope card in self-test mode and returns the status.

Figure 2. Ring oscillatorsignal spectrumthrough the S530switch matrix


Untitled-4 1 11/09/2012 16:33


test � techniques

In applications outside the general-purposeparametric test environment, test system designersstrive to ensure that the impedances of the DUT,transmission lines, and measurement equipmentare matched and that there are no open signalpaths, thereby minimizing the major causes of ACsignal distortion: insertion loss and reflections.However, this is not always possible to accomplishin a DC parametric test environment.

This is another situation in which a spectrumanalyzer will produce more accurate readings thana frequency counter because the amplitude of thefrequency of oscillation will usually stand outdespite these distortions.

Frequency measurementhardware Some parametric testers, including the S530Parametric Test System, support characterizing ringoscillators using a frequency measurement option.For the S530, this measurement option isoscilloscope-based and connects to an instrumentport on the system’s switch matrix, just like thesystem’s source measurement units (SMUs), C-Vunit, pulse generator units, and digital multimeter(DMM.) Once connected to the switch matrix, thefrequency measurements can be switched to anyone of the matrix’s DUT pins.

The instrument driver for the frequencymeasurement option measures the frequency of aring oscillator signal by using Fourier analysis toconvert the signal from the time domain to thefrequency domain. The various software commandsreturn the measurement in the form of pairs ofresults, corresponding to the frequency andamplitude of the strongest signals. The S530’sfrequency measurement option can accuratelymeasure AC signals with signal levels above25mVp-p and frequencies up to 20MHz.

Ring oscillator measurementexampleTo illustrate the process of making a ring oscillatormeasurement, let’s begin by assuming a ringoscillator like the one shown in Figure 3. The freq _init, freq _ setup, and freq _ measure commandsdescribed previously provide one way to measurethe ring oscillator frequency and signal amplitude.For the purposes of this example, let’s assume that

For this example, the following seven-command S530 test sequence could be

used to perform this measurement:

vss _ pin = 1 Defines the DUT pins.vcc _ pin = 2vccb _ pin = 3output _ pin = 4

vcc = 5.0 Defines the voltages required to power and trigger the ring oscillator.

conpin(SMU1, vcc _ pin, Makes the connections to the DUT.vccb _ pin, 0)conpin(vss _ pin, GND, 0)conpin(SCP1A,output _ pin, 0)

forcev(SMU1, vcc) Powers the device and triggers the oscillation.

init _ status = Initializes the oscilloscope card. This commandfreq _ init() is always required to use the scope card!

setup _ status = freq _ Defines the frequency scan and resolutionsetup( 0e6, 15e6, 1e6) bandwidth. Because the oscillator frequency is

10MHz, it’s essential to make sure that it is within the scan boundaries. In this case, the start frequency is set to 0Hz, the end frequency to 15MHz, and the resolution bandwidth (or scan resolution) to 1MHz. This would give a frequency measurement that is accurate to 1MHz.

meas _ status = freq _ Performs the measurement and returns themeasure(frequency, level) frequency (in Hz) and amplitude (in Vp-p) of

the strongest signal found.

Figure 3. Generalized CMOS ring oscillator

This is another situation in which a spectrum analyzer will produce more accurate

readings than a frequency counter because the amplitude of the frequency

of oscillation will usually stand out despite these distortions



test � techniques

the ring oscillator frequency is 10MHz and that itsVss, Vcc, Vccb, and output pads are connected topins 1, 2, 3, and 4 respectively. Let’s further assumethis device requires 5V to power it and 5V to triggerthe oscillation.

This article has offered a number of techniquesuseful for performing ring oscillator measurementswith a frequency measurement tool.


The ring _ max command listed previously offers a simpler approach to

performing this same measurement:

vss _ pin = 1 Defines the DUT pins.vcc _ pin = 2vccb _ pin = 3output _ pin = 4

vcc = 5.0 Defines the voltages required to power and trigger the ring oscillator.

meas _ status = ring _ Performs the measurement and returns themax(vcc _ pin, vccb _ frequency (in Hz) and amplitude (in Vp-p) of thepin, vss _ pin, strongest signal found. The ring _ max commandoutput _ pin, vcc, simplifies things a bit. Although most of the10e6, 0.5, 25e-3, arguments are self-explanatory when compared tofrequency, level, the previous example, the 6th, 7th, and 8thmeas _ status) arguments (...10e6, 0.5, 25e-3...) require some

explanation:� 10e6 is the expected frequency of oscillation.� 0.5 is the measurement tolerance. This parameter

tells the function how to know that it hasmeasured the desired frequency. The measurement stops when the following condition is met:

� 25e-3 is the minimum acceptable signal level in Vp-p.

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of the Silicon Semiconductor industry.

If you want to highlight the important breakthroughs that you make,

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packaging � chips

Today, advanced semiconductor packaging techniques are employed that move beyond simple wire bonding of a single die. Stacked dies, flipchips, and recently, more frequent employment of redistribution layer(RDL) wiring are commonplace to convert nanometer scale dimensionsto ones more easily measured in fractions of a millimeter.Michael S. Boger, Global Market Sector Manager for Edwards, discusses.

With greater complexity inpackaging, the number of bonding

pads has, likewise, increased significantly. Furthercomplexity is added with the introduction ofinterposers to act as a virtual breadboard formultiple dies in a single package – colloquially, a2.5D device. In a few years, true 3D will be a realitywith the stacking of homogeneous orheterogeneous dies. The trend to increasingcomplexity and 3D processing can be consideredone of the “More than Moore” trends referenced inthe International Technology Roadmap forSemiconductors. This trend is shown pictorially inFigure 1.

Growing challenges due to packaging topologyselection are associated with greater use ofvacuum-based processing tools. For example, flip-

chip packaging can make use of physical vapordeposition (PVD) vacuum processing equipment todeposit the under-bump metals (UBM) used as thebonding locations for the solder bumps.

When RDL wiring, which can also be deposited viaPVD or electrochemical deposition, is added,dielectric deposition is required to insulate the metaltraces. This dielectric could be chosen from anumber of different materials. In particular,polyimide appears to find some level of popularity.

If, as forecasted, silicon interposers find more use inadvanced packaging, a full suite of interconnect–producing, vacuum-based processing equipmentwill be required to create the package-enablingthrough-silicon-vias (TSVs) and dual-Damascenewiring (depending on the number of wiring levels).

Vacuum pump selection for advanced chip packaging

Edwards v2.qxp 27/9/12 10:07 Page 19


packaging � chips

The feature sizes of the circuitry are orders ofmagnitude larger than today’s smallest transistorsizes, but the reliable manufacture of such featureswill require semiconductor processing knowledge.With full 3D packaging technology, greater skill willbe required, as well as a potential division of laborrelated to device manufacturing and packaging.

In particular, for both 2.5D and 3D technology, thequestions are: will independent device makers(IDMs) and foundries do the packaging themselves?Will out-source assembly and test (OSAT)companies stretch their technology portfolio toinclude more vacuum processing? Or, will all of thework go to an independent third party as part of anintellectual property protection strategy, especiallywhen chips from different vendors are used in a

single package? Today, no one business ortechnology model prevails. From a vacuumcompany perspective, one conclusion can bederived: more and more vacuum processingequipment will be required in the packaging factory,and the packaging factory managers are likely to beless experienced with that equipment than thosesame managers of an IDM or foundry.

To minimize operating costs in an advancedpackaging factory, it is helpful to take advantage ofthe advancements in vacuum product technology.For example, new vacuum pumps dedicated toload-lock or light duty processing are incrediblycompact with low consumption of utilities. Figure 2shows an example of such a light duty pump (theiXL120 from Edwards, which is well suited for PVDprocessing tools) and how it compares to othersimilar products in the market. The iXL120consumes only 500 Watt of input power at a 700Torr exhaust pressure. It can also evacuate a 50 litervacuum chamber in only 17 seconds, a distinctadvantage for improving processing toolthroughput.

More vacuum pumps will be required for otherprocesses likely to be introduced into packagingfactories for 2.5D and 3D processing, such aschemical vapor deposition (CVD) of dielectrics anddeep reactive ion etch (DRIE). DRIE, in particular,poses particular challenges related to thermalmanagement of the pump and all associated pipingto ensure high reliability and a long time betweenpump services. Experience with best knownmethods related to pump reliability counts if down-time is to be minimized.

As the complexity of processing increases, so willthe number of vacuum pumps in the factory. As acompany’s size increases, the number of factorieswill also increase, especially since packaging tendsto be geographically close to where the wafers arebeing manufactured. In order to maximizeoperational efficiency, it can be financiallyadvantageous to monitor vacuum pumpperformance to prevent unplanned maintenanceand scrapping of wafers.

Vacuum pumps provided by leading manufacturersgenerally have on-board data monitoring capabilityand an ability for connection to a network where adatabase server is running to monitor and capturedata. With good network design, vacuum pumpdata can be made easily available within acompany’s intranet for monitoring purposes.Especially when fault prediction algorithms areemployed, savings related to implementing acomputer monitoring system add up quickly.

Figure 2a.Performancecomparison ofsimilarly classed load-lock pumps foruse with with vacuumprocessing tools

Figure 1. Increasedcomplexity inpackaging will requiregreater user ofvacuum-basedprocessing tools


Figure 2b.iXL120 VacuumPump


packaging � chips

Consider the assumptions shown in Table 1. Usingthe assumptions given, it can be seen that routinechecks would cost a company $60,833(€47,388.91) per year. If the data is analyzed anddiscussed, it can cost $10,920 (€8,506.68) per year.The higher costs come from an unplanned eventthat results in lost production. If five unplannedevents occur per year, and it is assumed $1,000(€779.00) can be earned per wafer, the unplannedevents can add up to $1,000,000 (€779,000.00) ofloss production per year excluding the cost of anylost wafers.

Although the price per wafer that can be earnedvaries greatly by product produced, even a value of$500 (€389.50) per wafer still results in a significantsavings if computer monitoring can reduce theamount of unplanned downtime. Evidence suggeststhat making use of on-board monitoring capabilitywithin leading edge vacuum pumps can only bebeneficial. In order to realize these benefits, it isimportant to select vacuum pumps, such as turbo-molecular pumps, from a single vendor to ensureseamless connection to a dedicated monitoringsystem.

In conclusion, advances in semiconductorpackaging are happening today. Tomorrow, greatercomplexity involving semiconductor vacuum-basedprocessing will pose a challenge. Using advancedvacuum products from experienced companies willhelp reduce operational costs, especially if featuresbuilt-in to the products can be used to advantage.


Figure 3 (a) Exampleof Edwards Fabworksequipment monitoringscheme. (b) Exampleof data monitoringused for predictivefailure analysis

Item Assumption Number of pumps 100

Periodic checks

Routine pump check 5 min / pump

Service person’s wage $20 / hr (€15.58)

Cost for checks $60,833 / year (€47,388.91)

Data review and analysis

Analysis time 2 hr / week

Collation / summary 1 hr / week

Analyst wage $70 / hr (€54.53)

Cost for analysis $10,920 / year (€8,506.68)

Pump replacement analysis

Time to replace 2 hr

Tool preparation time 2 hr

Unplanned times 5 / year

Downtime per year 20 hr / year

Process tool & wafer price

Tool throughput 50 wafer / hr

Price per wafer earned $1,000 (€779.00)

Table 1. Model Assumptions



exhibition � focus

SEMICON Europa: A marketplace for visionaries

In a few weeks Europe’s largest and most important show for thesemiconductor manufacturing industry will start. It’s the marketplacethat promotes the sharing ofknowledge and ideas, brings togethermanufacturers and suppliers, createsstandards and enables all participantsto think outside the box.

SEMICON Europa 2012 and Plastics Electronics 2012 willprovide unique opportunities for companies. Now

integrated with SEMICON Europa is the 8th Plastics ElectronicsExhibition and Conference (PE2012). It will also take place from 9– 11 October at Messe Dresden.

The mission of PE2012 is to bring together experts, researchinstitutions, manufacturers, investors, suppliers and other industrystakeholders to accelerate plastic electronics from the laboratoryto the large-scale, high volume production.

More than 350 exhibitors from over 20 countries are expected atthe combined SEMICON Europa and Plastic Electronics events,which also feature over 210 industry leaders speaking on a widerange of topics.

The 16th European Fab Managers Forum, a comprehensive two-day event, covers issues and topics focused on improving

SEMICON Europa v1.qxp 27/9/12 11:49 Page 22



manufacturing productivity and extending the life of existing FABs through new technologies and markets. The topic this year: “Cost Reduction and Continuous Improvement by using ITTools”.

The International MEMS/MST Forum will focus on “New Dynamicsin the MEMS Industry”. The forum is an exceptional platform forexhibitors and visitors to explore the MEMS industry supply chain.

The 450mm Session is covering the latest state of introducing,planning and R&D for 450mm. The session includes all majorinitiatives as well as the progress which was made during the lastyears. The Advanced Packaging Conference will present “PackagingSolutions for the New Technologies”. The conference will give theopportunity to learn more about most important microelectronicsapplications developments which enable novel, advancedpackaging solutions to be the key drivers in system integration of

electronic devices. The 14th European Manufacturing TestConference (EMTC) is presenting “Overcoming New TestChallenges through Cooperation and Innovation”. The Conferencewill present an interesting mix of topics in the broad area oftesting semiconductor devices.

SEMICON Europa remains the largest industry event in Europefocusing on technologies and solutions for advancedmicroelectronics manufacturing including semiconductors, MEMS,printed and plastic electronics, power electronics, and otheremerging and related electronics markets. “SEMICON Europa isthe heart and soul of the microelectronics industry in Europe,”says Heinz Kundert, president of SEMI Europe. “It is the placewhere the entire industry gathers – suppliers, technologists,executives, and purchasing agents – to learn, network, andunderstand the developments of technology and trends thatshape and drive microelectronics innovation.”

Plastic Electronics offers new opportunities After many years of research and development efforts around theglobal, plastic electronics is reaching the momentum ofcommercialization in areas such as for displays, lighting,photovoltaics and integrated smart systems. The PlasticElectronics 2012 Conference and Exhibitions in Dresden will befocused on challenges and opportunities for manufacturing theseapplications and products for the mass consumer markets. It isthe single and sole event to focus on issues related tomanufacturing of these challenging new applications andproducts and will bring together the stakeholders for this newemerging industry in a single setting. The conference will presenta line-up of over 90 expert views for top-level professionals in thefield, whereas the exhibition will be the market place to meetabout 100 materials suppliers, tooling vendors and integrators ofPE systems and solutions.

The Plenary Session, a comprehensive three-day event, coversissues and topics focused on technologies and markets. Thekeynote-speakers are:

Barry Young, Managing Director, OLED Association is presentingthe “Market Forecast”. He addresses issues as the developmentof industry standards for OLED display and lighting, promotion ofthe technology and the resolution of industry-wide technicalissues.

Thibaud Le Seguillon, CEO of Heliatek will speak about: “FutureApplications: Roll-to-roll Vacuum Deposition of Small Molecules –The Right Choice”. Heliatek GmbH, a global leader in high-endsolar PV technology, is about to start production of its worldwideunique organic solar films. The solar films will be produced in alow temperature roll-to-roll process in which small molecules(oligomers) are vacuum deposited onto inexpensive plasticsubstrate. The presentation will inform about the progress onramping up Heliatek’s vacuum based roll-to-roll production andthe production process in general.

Luisa Torsi, Professor, Università degli Studi di Bari “Aldo Moro”.She focuses on “Technology: Ultra Sensitive Label Free Bio-electronic OFET Sensors”. She is the 2010 E. H. Merck prizewinner for Analytical Science, being the first women to beawarded with this prize. Her main research interests are in thefields of functional materials/nanostructures and electronic



and are expected to reach worldwide revenues of over 20 BillionUS-Dollar in 2015.

The world market for flexible and organic PV is currently estimatedat about 2.6 Billion US-Dollar. According to the market researchcompany Nanomarkets, the market for thin film and organicphotovoltaics will grow worldwide up to 7.5 Billion US-Dollar in2015. It is generally expected that roll-to-roll manufacturing offlexible PV, partly done by soluble printing will becomeeconomically feasible for grid-linked application once efficienciesof 10% at cell level will be passed.

Integrated Smart Systems is the new buzzword for a innovativeclass of applications and products which are expected to arise.Manufacturing, processing and tooling issues will be at the focusof attention of the event and in line with applications and productsentering the end-user markets. Attending the event will bechallenging and rewarding to anyone exploring the opportunitiesof this emerging and promising technology!

SEMICON Europa and Plastic Electronics Exhibition andConference offer a unique proposition for visitors and exhibitors.The two segments have much in common, sharing basictechnologies, equipment, materials, and services. For existingmembers and customers, many topics touch on both traditionalsemiconductors and new technologies emerging from plastic

electronics. Synergistic opportunities exist for enterprising andentrepreneurial supply chain participants.

Approximately 400 exhibitors from 20 nations are expected at the SEMICON Europa in Dresden

from 9 – 11 October. For more information ontopics, conferences, expert events and exhibitors visitwww.semiconeuropa.org and www.plastic-electronics.org

© 2012 Angel BusinessCommunications. Permission required.

devices for chemical and biological sensing. Ho Kyoon Chung,Chair Professor and Director, Samsung SMD OLED Center,Sungkyunkwan University will do the motivational speech on thethird day. His topic: “Challenges of AMOLED TV and PlasticAMOLED”. AMOLED technology has been successfullycommercialized for the high resolution mobile displays and is nowpoised to enter the new markets such as large size TV’s andplastic AMOLED. However, there are still many challenges forcommercialization, which is related to the cost of manufacturing.This talk will discuss these challenges and propose innovativeideas to overcome the cost issues.

The Plastic Electronics Conference and Exhibition will consider allmajor aspects of the industry. It is the best forum to meet withother professionals with the same interests, both from researchand industry.

SEMICON Europa has ever been a marketplace for visionaries formany years. Organic and plastic electronics are an entirely newarea of technology. “This combination fits very well”, says Ed vanden Kieboom, Chairman of the Plastic Electronics Special InterestGroup. “The two events offer visitors as well as exhibitors greatsynergies and opportunities. No other event combines the twodisciplines under one roof like the SEMICON Europa in Dresden,Germany. Topics like ‘Smart System Integrations’ touch bothtraditional semiconductors and new technologies emerging fromplastic electronics.”

Organic and Large Area Electronics (OLAE) coverfive important areas – OLED Lighting, Organic andInorganic Photovoltaic, OLED Displays, OrganicElectronics and Integrated Smart Systems –which all have a similar cutting-edgetechnology with high benefits, fast timeresponse, thin format, excellent colorreproduction and low powerconsumption. In 2012 the revenues areexpected to accelerate to over 4 BillionUS-Dollar. Larger displays for TV areexpected to boost the marketdevelopment for OLED displays


Integrated Smart Systems is the new buzzword for a innovative class of

applications and products which are expected to arise. Manufacturing,

processing and tooling issues will be at the focus of attention of the event

and in line with applications and products entering the end-user markets.

Attending the event will be challenging and rewarding to anyone exploring

the opportunities of this emerging and promising technology!


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Chaired by Keynote speakerDr Andrew Nelson, IQE President and Chief Executive Officer Conference Chair

Dr Wilman Tsai, Intel CorporationProgram Manager of Technology Manufacturing III-V CMOS for High Performance and Low Power Logic Devices

Platinum Sponsors

Featuring

Daniel Cline, Lux Research IncSenior AnalystWBG Devices Electricity Grid Opportunities

Dr Simon Fafard, Cyrium Technologies Inc Chief Technical OfficerNovel Solar Cell Technology

Bryan Bothwell, TriQuint Semiconductor Strategy and Business Development ManagerMaximizing Gallium Nitride Product Solutions and Foundry Services for Advanced RF Design Success

Asif Anwar, Strategy Analytics Director Strategic Technologies Practice What is the Future of GaAs Microelectronic Manufacturing

Dr Michael Lebby, Translucent Inc General Manager & Chief Technology Officer Challenges & Opportunities of Using Epitaxial GaN, GeSn, & Rare Earth Oxides on Large Format Silicon Wafers for Power Electronics, Solar, & Lighting

Dr Rainer Krause, Soitec Director Smart Cell Incubator UnitPV Chip Development

Dr Markus Behet, Dow Corning Corporation Global Market Segment Manager Power ElectronicsLarge Diameter SiC and GaN/Si Substrates as Cost-Effective Solutions for Power Electronic Applications

Dr Schang-jing Hon, Epistar CorporationAssociate Vice PresidentHigh-Voltage LED for General Lighting Application

Michelle Bourke, Oxford Instruments Senior Product ManagerMEMS – Entering a New Growth Cycle

Malcolm Harrower, Indium Sales Manager EuropeAn Overview of the CS Building Blocks – Indium, Gallium and Germanium

Allan Jaunzens, EvatecMarketing ManagerPresentation TBC

4th-5th March 2013 Sheraton Frankfurt, Germany

CS International DPS Alternative version v19.indd 2 27/09/2012 10:55

Bringing together leading Compound Semiconductor industry insidersGain a comprehensive overview of the entire compound semiconductor industry-the must attend event for 2013 is the 3rd CS International conference in Germany, at the Sheraton Frankfurt on 4th-5th March 2013.

Delegates will have the unique opportunity to network with leading industry professionals of the III-V chip making industry, interact with suppliers and industry experts who will deliver the latest research, business models, and insights.

Please visit www.cs-international.net for further information or register at: www.cs-international.net/registration

Gold Sponsors

All speakers and presentations are subject to change

Dr Philippe Roussel, Yole Développement Business Unit ManagerGaN vs SiC in Power Electronics - Status and Roadmap to 2020

Dr Tudor Williams, Mesuro LtdSenior Systems EngineerImproving RF Measurements

Pars Mukish, Yole DéveloppementMarket & Technology AnalystNew Trends in LED Industry: A focus on China and GaN-on-Si LEDs

Professor Tao Wang, Seren Photonics Scientific Advisor Improving LED Performance

Dr YiFeng Wu, TransphormVice President, Product Development Status of Wide Bandgap Power Electronics

Dr Vijit Sabnis, Solar Junction Vice President, TechnologyReally High Efficiency Triple-Junction Solar Cells

AJ Nadler, RF Micro Devices (RFMD)General Manager, R&D and Engineering Gallium Nitride for High Voltage Power Electronics

Dr Ertugrul Sönmez, MicroGaN Director, Business DevelopmentAddressing Emerging Power Market

Dr Frank Schulte, Aixtron Vice PresidentPresentation TBC

Dr Elisabeth Steimetz, LayTec AG Director Marketing and SalesIn-Situ Monitoring - The Key to MOCVD Production Process Control and Yield Enhancement

Noriyuki Matsubara, Panasonic Europe Dry Etching and Photolithography EngineerDry Etching Technology for III-V Devices

Dr Thomas Uhrmann, EV Group Business Development ManagerWafer-Level Packaging of Compound Semiconductor Devices

Gregg Wallace, Temescal Managing DirectorFundamental E-Beam Coating Collection Efficiency & Paths to Improvement

Erwin Ysewijn, Azzurro VP Sales & MarketingGaN on Si. Large Size High Voltage Wafers showing Superior Electrical Performance and Volume Production Track Record

Gunnar Stolze, Oclaro IncVP Global Sales Industrial and ConsumerHigh Power Lasers

CS International DPS Alternative version v19.indd 3 27/09/2012 10:56


PCB � manufacturing

Future Trends in PCB ProductionWhat key trends will shape the future of PCB production? John Cunningham, ChiefChemist, Rainbow Technology Systems Ltd hasidentified some key drivers that are universal to the electronic sector and looks to answer this broad, yet complex question.

When Rainbow Technologyembarked on a journey six years

ago to develop a new method of PCB production,the following factors were taken into account: � All manufacturers want to cut costs without

compromising quality.� All manufacturers want to improve yields and

reduce wastage and reject rates.� There is an overriding pressure to make

processes greener. This not only means the use of more environmentally friendly materials but also making every effort possible to reduce energy consumption in the manufacturing process.

� Features are becoming increasingly smaller therefore there is a greater demand for fine line circuitry than ever before.

The result was the Rainbow Processing Unit – anautomated PCB production unit incorporatingcoating, imaging and developing in one compactenclosure.

Traditional PCB productionThe process for producing PCBs has changed littlein the past 50 years. There have been incrementalimprovements in quality and efficiency but nothingrevolutionary. At present PCB manufacturingequipment requires a substantial capital investmentas it must be housed in a clean room environmentand the machinery takes up considerable amountsof space. The process starts with either laminatingthe copper boards with dry film protected withMylar™ or roller coating with a solvent-basedcoating which is then passed through a hot air orinfrared oven to remove the solvent and leave a dryfilm. Due to long drying times, often in a horizontalposition, debris can get on to the panel which canlead to occlusions later in the imaging processThese dry film or coated panels are thentransported under yellow light to the imaging unit.

Imaging is carried out with an off-contact processusing collimated light, which at present can onlyachieve imagining down to 50 microns. The imaged panel is then transported (again inyellow light) to the developing station where the 20-25 microns of film or coating spend 1-2 minutesbeing developed before storage or forwarding to

Rainbow Technology Systems v1.qxp 27/9/12 10:16 Page 28



the etching line. When it comes to fine line detail(under 50 microns) the most common methodsemployed are Laser Direct Imaging (LDI) or unitsincorporating a Digital Mirror Device (DMD). Both ofthese methods use imaging units which require thecopper panels to be coated with a dry film laminateor a wet solvent-based photoimageable resist.

Both methods require considerable space for thelaminating or coating lines and consume a lot ofpower as there require drying ovens (from 20kW to70kW), laminators (averaging 20kW) and collimatedUV light sources for the imaging process (averaging20kW).

ResistThe first area Rainbow looked at was the type ofresist commonly used. Traditionally dry film is usedhowever it has a number of drawbacks. To obtainfine detail the dry film is very thin in the order of 12-15 microns, it is difficult to handle does not conformeasily to the surface of the copper and has atendency to delaminate particularly when printingfine detail. It is also applied laminated with heatedrollers prior to imaging which can lead to stressforces building with in the copper panel.

We therefore looked to develop a special wet resistwhich could be applied wet to the panel surfaceand squeezed into all the contours of the coppersubstrate thereby greatly improving surfaceconformity and subsequent adhesion. As thecoating is 100% solids and solventfree it does not need to be pre-dried.The resist is cured using UV LEDlight and any unexposed resist issimply washed off as it remains in itsliquid state.We then addressed the efficiency ofthe process. At present Laser Direct Imaging (LDI)is used for fine line printing. This canproduce up to 80 single-sided panelsper hour. By contrast the Rainbow ProcessingUnit can process up to 200 double-sided panels per hour (total elapsedtime for producing a double-sidedpanel is only 1 minute from beginningto end).

By using standard LEDs for imagingand avoiding the need for pre-dryingthe Rainbow system has an overallpower consumption (averaging under3kW). The unit itself takes up only

12sq m of floor space and is in its own self-contained enclosure where the air quality is kept atcleanroom conditions by HEPA filters. Withproduction space at a premium this is now a veryimportant consideration.

With the dry film process a layer of protective Mylaris applied to the substrate to protect the film. ThisMylar has to be stripped off and disposed of in landfill sites. In traditional resist systems solvents usedin the base coatings release considerable amountsof CO2 into the atmosphere when removed from thesubstrate and burned off in scrubbing units beforeventing to atmosphere. As no Mylar is used in theRainbow process and the resist is solvent free theprocess is significantly greener.



Maximum yieldsAll manufacturers are striving for maximum yieldsand minimum waste. The Rainbow System hasbeen designed using optics which has a collimationof only six degree half angle. As there is only a nine-second gap between the coating and imagingstages and the panel in a vertical orientation thisoffers less opportunity for debris to attach itself tothe wet resist.

Particles which trapped in the cured resist will betransported on with the panel or if present in the wetresist will either slide off the protective layer on thephototool or again move forward with the panel andbe removed in the developer and so repeat errorsare unusual.

Given this and the fact that the whole process isalmost entirely automated it should lead to higheryields. As the panels come out ready for etchingthere is no need to transport or store them in yellow

light (to prevent premature curing from UV light inthe atmosphere). One of our aims in developing thesystem is to give a new lease of life to standardphoto tools without the costly maintenanceconnected with LDI. Very little heat is generated bythe process so the issue of heat distortion of thephoto tool is avoided.

Standard silver halide photo tools are used and a special three-micron coating is applied usingRainbow’s Panda Coater to protect the tool frommoisture and chemical attack from the resist. Photo tools take under two minutes to changeoverusing a self-locating cart system

Touchscreen productionAlthough we designed the Rainbow Processprimarily for PCB production there has been interestin applying the technology in other areas mostnotably touchscreen displays. The process can beused to print very fine conductive tracks, invisible tothe human eye, on to a clear substrate. Gridpatterns of five microns by 300-pitch offer more

conductivity than ITO or conductivepolymers and offering muchcloser track and gapconfigurations (down to 10micron spacing) designers willhave more scope toincorporate additional featuresand functionality into the touchscreen.

ConclusionTraditional methods of PCB arechanging in line withmanufacturers demands forgreater efficiency, finer linecircuitry and a greener

approach to production. Companies such as Rainbow Technology

Systems are developing new processes to meetthese demands and produce the next generation ofPCB imaging equipment.



Traditional methods of PCB are changing in line with manufacturers

demands for greater efficiency, finer line circuitry and a greener

approach to production. Companies such as Rainbow Technology Systems

are developing new processes to meet these demands and

produce the next generation of PCB imaging equipment


The Power of [Europe]

Connect to the trends, technologies and people driving the European Semiconductor Industry forward.

SEMICON Europa is the place to see the leading companies,

technologies, and people driving the future of micro- and

nanoelectronics design and manufacturing.

SEMICON Europa exhibitors are the suppliers to and partners

of Europe’s leading microelectronics companies. From silicon

to system − and everything in between and beyond − SEMICON

Europa showcases the biggest and brightest names in micro-

electronics manufacturing.

SEMICON Europa Programs:• 14th European Manufacturing Test Conference (EMTC)

• Advanced Packaging Conference

• 16th Fab Managers Forum

• International MEMS / MST Industry Forum

• 6th Executive Summit

• SEMI Market Briefing

• Metrology, Process Control, Automation and Software Session

• 3D IC Session

• Power Electronics Session

• Secondary Equipment and Technology Session

• LED / SSL Session

• Workshop on Equipment Assessment & Performance Improvements

• Standards Meetings

9–11 October Messe Dresden, Germany

www.plastic-electronics.org

Co-located with:

Plan now to be part of SEMICON Europa 2012

www.semiconeuropa.org

EUVLED/SSL450mm

More than Moore

3D ICMEMS

Fab AutomationEquipment

The Power of [x]


generic � manufacturing

Integratedphotonicsdesign flowautomationBy creating generic technology platforms fordevelopment and manufacturing of PhotonicIntegrated Circuits, huge cost reductions can beachieved. Using a small set of re-usable buildingblocks that are integrated in mature foundryprocesses, a wide variety of Photonic Integrated Circuits can be designed and fabricated using the same family of fabrication processes. Twan Korthorst andRemco Stoffer discuss.

IPDF v1.qxp 26/9/12 16:05 Page 32



Stable fabrication and integrationtechnologies decrease the cost price and

development time of photonic integratedcomponents without sustaining a loss on theperformance of the photonic component. Instead ofoptimising the fabrication technology for everysingle application, the product design is adapted tothe capabilities of available, mature, high

performance fabrication processes. To createstable processes right tools are needed, such

as software for layout, simulation andfabrication execution and methods such as

in-line and off-line quality testing. Nextstep is to collect the information fromthe fabrication processes and translate

this into standard building blocks for thephotonic integrated circuit, given a

particular fabrication process flow.

Integrated Product CreationProcess

Underpinning the whole “genericmanufacturing” concept is the information flow

between different abstraction levels and thedifferent stages of product and process

development. When system engineers, designengineers and process engineers work together to design both the product and, when required,fabrication processes, it is known as the integratedproduct creation process (iPCP figure 1). Thedesigner’s consideration of design formanufacturability, cost, reliability and maintainabilityis the starting point for an integrated productdevelopment.

The iPCP concept has been implemented bydeveloping dedicated Design Kits for variousfabrication technologies, amongst others siliconphotonics. PhoeniX Design Kits contain all relevantinformation for designers in order to create aphotonic integrated device or circuit within thecapabilities of the fabrication processes. Usersbenefit from this by having immediate access tomature and proven building blocks, ensuringfunctional devices. Furthermore, recurring costs areavoided by streamlining the discussions amongstdesigners and engineers at the foundry. Theknowledge of the product creation process will beutilised into the Design Kits through standarddesign software, which assists to avoid thatdesigners repeatedly build libraries for sametechnologies. The main content of these Design Kits

are the building blocks containing geometricalinformation, parameters, boundaries, design rules,IP-rights, simulation settings, mask information,version, etc. By reusing validated definitions formultiple applications and designs, the quality of theinformation used by the designers increasesconsiderably.

Photonics Design AutomationIn the electronics industry, the use of ‘ElectronicsDesign Automation’ (EDA) is wide-spread. A foundryoffers an extensive set of building blocks (BBs),which a designer can use to create a complexdevice. The BBs and their combination areguaranteed to work as expected if the given designrules are respected. Software supports each step inthe design process, from physical analysis to layout,and flags any design rule violation before the finaldesign is shipped to the foundry. Furthermore,simulation tools are integrated in, or link directlyinto, the EDA environment and assist the designerin his work.

In the field of integrated photonics, such advanceddesign kits have not been available until recently. A number of European companies and institutionshas worked together to set up a Photonics DesignAutomation (PDA) tool-set. Just like in EDA,photonic foundries define a number of buildingblocks, which are implemented in software toolsranging from mask layout through physical andcircuit simulators. The circuit simulator is able to call

Figure 1: IntegratedProduct CreationProcess

IPDF v1.qxp 26/9/12 16:05 Page 33



the physical simulation software, or query a buildingblock directly, in order to quickly simulate theresponse of a device. Furthermore, it can call themask layout software to export the circuit designinto a physical mask layout.

Since building blocks of one foundry can be similarto those of other foundries, many designs will betransferable from one foundry to another with onlyminor changes to the layout (due to differences inBB sizes and port locations), however withsignificant changes to the mask layers (due todifferences in technologies and process flows).

Design flowA designer of a PIC (Photonic Integrated Circuit),who wants to have his design realized by a foundry,typically starts his design by modelling it in a circuitsimulator [1]. In the circuit simulator, one designsan optical circuit by placing building blocks from thefoundry library with their properties into the circuitlayout. The designer does not focus on how exactlya building block is implemented; the foundry ratherspecifies the input / output ports and, possibly inconjunction with physical layer simulators [2, 3], thewavelength dependent scattering matrix (S-matrix)of the block. By clicking together a circuit andspecifying its input and outputs, the designer canvery quickly calculate the spectral response of the

complete device. He can then optimize it for betterfunctionality or for better robustness with respect tofabrication technology tolerances.

Once a satisfactory design has been created in thecircuit design tool, it can be transferred, via the PDAframework, to the mask layout software [4]. Theuser specifies a chip type available in the foundryand (if packaging options are available) a package.Such a combination of chip type and packagedefines the locations of the optical and electricalinput and output ports.

In the mask layout software the designer can adjustthe exact layout of his design to optimize for spaceconstraints and to make sure all connections (bothoptical and RF or DC electrical connections) arecorrect.

In the layout environment, the designer might onlybe allowed to see the outline of the foundry-definedbuilding blocks. A foundry can protect its IP by justexposing a bounding box and the locations anddimensions of access waveguides and connectionsfor electrical signals, as shown by the privatebuilding blocks in Figure 3.

When the designer is satisfied with his mask layout,he exports it to a mask file. This process involvesautomatic post processing on the mask layers thatare defined by the foundry; for example, awaveguide on the final mask might have to be alittle wider than designed to correct for under etch,or a final mask layer might have to be a localinversion of the designed waveguide.

During this foundry specific automatic mask exportprocess, the software performs design rule checks(DRC) on both the logical and mask layer levels. Anexample of a logical check is the radius of curvatureof a waveguide, while an example of a mask layercheck is whether a metallization layer and awaveguide layer overlap – or are closer than a givendistance to each other.

Since the designer has no knowledge of the innerworkings of a private building block, the mask filesthat are produced will be incomplete as the IP-protected building blocks are left open. The exportprocess also generates a list of the used buildingblocks and their exact locations in the layout.

When the foundry receives designs created with thedeveloped design environment, for example for aMulti Project Wafer run, it assembles all the maskfiles from the users into one reticle or mask set.

Furthermore, it uses the building block informationsupplied by the users to fill in the private buildingblocks in all designs with its own proprietary mask

Figure 2: PhotonicsDesign Automation ascentral pivot point inthe supply chain

Figure 3: Mask design with boundingboxes for IP licensedbuilding blocks

IPDF v1.qxp 27/9/12 12:39 Page 34

ALL THE APPLICATIONS, ALL THE TECHNOLOGIESUSA’s leading event on printed, organicand � exible electronics

Giving you the full picture of end-use application requirements, manufacturing processes and materials for displays, photovoltaics, energy storage, sensors, logic, memory and lighting that are printed, flexible or based on the new organic or inorganic electronic materials. See new products and learn how these new devices can be adopted in your business. Printed and potentially printed electronics is of vital interest to industries as diverse as chemicals, consumer goods, healthcare, military, electronics, advertising, transportation, infrastructure and publishing.

Exhibitors include:

Visit www.PrintedElectronicsUSA.com for full list of exhibitors and excellent speakers.

Printed Electronics USA 2012 December 5–6 | Santa Clara, CA, USA

Visit www.PrintedElectronicsUSA.com

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TechTechPrinted Electronics

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Speakers include:

Exhibitors include:

Printed Electronics Asia 2012 October 2-3 | Tokyo, Japan

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data. After this final mask assembly, the reticles ormasks can be created.

Multi Project Wafer runsBy sharing the costs for the fabrication, the reticlesor masks and the set-up and use of the designenvironment in Multi Project Wafer (MPW) runs, theaccess barrier to photonic integration technologycan be brought down.

The amount of offered MPW runs has increasedconsiderably over the last period of time and theseresults in a steep increase in the amount ofresearch and development activities in the field ofintegrated photonics. Moreover, the increase of thenumber of fabricated wafers with a same processflow creates more stable manufacturing processesto further drive down the costs by an increasedyield.

The design flow as described in this paper hasbeen applied successfully within a number of MPW runs [5, 6, 7]. During the past six months,runs in Indium Phosphide [9, 10, 11], TriPleX [7]and silicon photonics [12, 13] have been executedon the developed design platform and more than 50 different designs have been successfullyimplemented for six different foundries and twopackaging providers [14, 15].

Future outlookA set of re-usable building blocks that is available in stable and mature (commercial) foundryprocesses leads to huge cost reductions. Thisopens up the application of photonics integrationtechnologies to a much larger public. Instead ofoptimizing the fabrication technology for everyspecific application, the product design will beadapted to the capabilities of available, mature, high performance fabrication processes. Thepresented PDA environment plays a central role(see Figure 1) in the whole product and value chainfrom concept application to material, throughdesign to manufacturing.

Further, this developed framework can be used byboth companies and institutes to promote internalcollaboration and information exchange betweendesigners and with process engineers. Thedeveloped PDA framework is open to other partiescreating their own plug-ins and building blocks. For example, two different Arrayed Waveguide Gratingplug-ins, for designing wavelength filters, have beencreated by third parties [11, 16] and are actively usedin the mentioned MPW runs designs.


References[1] Aspic: photonic circuit design and simulation tool[2] FieldDesigner: advanced modesolver, including T/O, E/O, 3D Ring

Resonator and Active Material modules[3] OptoDesigner: propagation simulator, includes BPM, FDTD,

BEP/EME, Zone and FAST technology[4] MaskEngineer: object oriented and parametric layout solution[5] InP MPW brokering organisation: JePPIX - http://www.jeppix.eu[6] SOI MPW brokering organisation: ePIXfab - http://www.epixfab.eu[7] TriPleX foundry partner: LioniX (Netherlands) -

http://www.lionixbv.com[8] European project EuroPIC - http://europic.jeppix.eu[9] InP foundry partner: Oclaro (UK) - http://www.oclaro.com[10] InP foundry partner: FhG-HHI (Germany) - www.hhi.fraunhofer.de[11] InP foundry partner: Technical University Eindhoven (Netherlands) -

http://w3/ele.tue.nl/oed[12] Silicon photonics foundry partner: CEA-Leti (France) - www.leti.fr[13] Silicon photonics foundry partner: IMEC (Belgium) - www.imec.be[14] Packaging partner: CIP (UK) - http://www.ciphotonics.com[15] Packaging partner: Linkra (Italy) - http://www.linkra.it[16] Design house: Bright Photonics (Netherlands) -

www.brightphotonics.eu

Figure 4: From DesignKit to manufactureddie [8]

IPDF v1.qxp 27/9/12 12:39 Page 37


corporate partners � directory

Equipment

Gas Handling & MFC

Gas (High Purity) Process Control

Chemical Pumps Fan Filter Units

Furnaces

Furnaces

Automation & Wafer Handling Connection Solutions Furnaces

Cleanrooms

Furnaces

Corporate Partners Final DR.qxp 26/9/12 16:22 Page 38


corporate partners � directory

Wafer Level Packaging

Wet BenchesWet Benches

Material Processing

To promote your Products and Services cost effectively to

all our buyers and specifiers, take advantage of the new

Corporate Partners section.

A Corporate Partners entry is effective, and an easy way of

promoting your products and services for the full year.

Additionally your entry will be seen at major exhibitions and

events throughout the year.

For further information, please contact: Shehzad Munshi

T: +44 (0)1923 690 215 E: [email protected]

Entries in Corporate Partners @ £1,500 per heading per year.

Liquid Nitrogen Piping

RF-/DC-/MF-Power Supplies

Semiconductor Equipment

Solder Rework

Vacuum Equipment

Equipment

Corporate Partners Final DR.qxp 26/9/12 16:22 Page 39

Multiple Adhesive Suppliers

High Throughput Production Systems

Integrated Metrology for Advanced Process Control

U.S. Patents 6,792,991 and 7,910,454 Further Patents Pending

Temporary Wafer Bonding / Debonding Solutions

www.EVGroup.com

LowTemp™ DebondingZoneBOND® Open Platform

LowTemp™DebondingEVG Technology

ZoneBOND®

EVG®850TB/DB XT FRAMEIntroducing the next-generation

temporary bonding and debonding platform for high-volume 3D IC manufacturing

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