SI Guidelines

8/3/2019 SI Guidelines

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Best PWBA Design

Practices for OptimalEMC, SI, and PI

Jim Herrmann, Principal Engineer

AppliedLogix, LLC. Fairport, NY

[email protected]


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Presentation Outline

Background and history The high speed design challenge

Digital signaling fundamentals

PWB stack-up and construction key details

Power distribution network (PDN) design approach

HyperLynx LineSim & BoardSim: ad hoc intro following talk ifany interest

1 hour time limit - topic coverage is very brief /snapshots, references provided for further

investigation

**Lets keep the discussion informal - questions arewelcomed and encouraged at any time**


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Brief Bio

25 years of digital electronics design engineering always a hands-on practitioner On-site Field Service Engineer, Kodak (1981 1983) Design Engineer (JrSrTeam Leader) Kodak (1984-1995) Hardware Design Manager, Xerox Corp. (1995-1998)

Engineering VP, InSciTek Microsystems / Allworx (1998 2006) Founder / Managing Partner, AppliedLogix LLC, (2006 present)

Career-long pursuit of a lean yet robust digitalelectronics design methodology still evolving today maximizing the products performance versus price ratio Zero defects mindset: quantitative design approach Cannot overlook or outsource DFM and DFT Methodology yields predictable / repeatable results and dev schedules


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The High Speed Design Challenge

Nicely summarized by Dr. Howard JohnsonSignal Integrity is not just a nice to know subject. It isessential to the

proper operation of every high-speed digital product. Without dueconsideration of the basic signal integrity issues typical high-speedproductswill fail to operate on the bench and, worse yet, becomeflaky or unreliable in the fieldMaintain a healthy interest inproperly balancing your signal integrity, EMC, and manufacturingcost objectives. Get some formal training, constantly keep on thelookout for new tools, and tear apart lots of other people's productsto see what the competition is doing. The payoff is easy to

understand: better system-level performance, a more reliableproduct, and an overall reduction is cost.


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PWBA Design 2010

Moores Law has delivered very high performance ICs with sub-nanosecond switching times Power delivery lower DC voltages w/ higher transient currents Output buffers faster slew rates, lower output impedance

The PWB physical interconnects are not transparent to the digital

signaling Modern PWBA design methodology careful analysis and

specification of the PWBA physical interconnects combined with SIaware component selection and circuit design PWB stack-up, construction, and trace routing Power Distribution Network (PDN)

Off-board IO Connectors Optimal EMC achieved when signal and power integrity addressed

in a comprehensive manner


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My Early Wake Up Call

1984 Very first electrical design role on the Kodak 12 MByte floppydisk drive w/ embedded SCSI controller (huh?) SMT was a brand new technology, enabling higher parts density Challenging mixed-signal design with significant digital processing and

analog circuits (2) Z80 microprocessors, (4) gate arrays High gain analog read channel; track-following servo control

A split ground plane was implemented for analog / digital isolation

First prototype K12 PWBA Passed smoke-test and bench-top POST When PWBA mounted onto the disk drive: R/W Channel FAILURE

Severe coupling of board emissions into the read/write head Weeks to determine SRAM signal traces routed over the split GND plane

were the source of the interference


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No Free Lunch Design complexity continues to ramp up

SOCs and DSPs are larger and faster FPGA performance and gate counts have reached ASIC proportions Virtually all modern IC devices produce signaling that has surpassed the high

speed effects threshold Hign speed digital design has acquired the complexity of analog and more

Growing number of low complexity embedded designs failing EMC Must plan for sufficient development time, budget, and engineering

resources to adequately address and manage high speed issues

Architecture Detailed Design PWB Layout Prototype

Verification

Architecture Detailed Design PWB

Layout

Prototype

Verif.

High

Speed

Timeline

Low Speed

Timeline


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Defining High Speed

Digital Signal Edge Ratesare the determining factor

Higher clock frequencies mandate faster edge rates, thereby

inferring high speed signaling issues

Simply operating high speed ICs at a lower clock frequency does

not eliminate the high speed signal integrity issues

Think signal bandwidth not clock frequency

Digital Signal Bandwidth the relationship between signal rise

time (10% to 90% in nsec), and its bandwidth (in GHz)

Empirical approximation: BW ~ 0.35 / rise time

Example: rise time = 0.35nsec, then signal bandwidth ~1 GHz.


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No Safe Haven

Recent peer review ofvery simple low speedboard schematic.Example net: Single SN74LVC1G14

D-flip-flop driving 4 oftrace and a single load.

Zout = 12 ohms Output rise = 500ps

BW = 700 MHz

DesignFile:6-layerstackup.ffs

HyperLynxLineSimV8.0

U7.1

LVC1G14_DBVY

TL2

52.8 ohms686.222 ps4.000 inStackup

U2.1

LVC1G14_DBVA

OSCILLOSCOPEDesign file: 6-LAYER STACKUP.FFS Designer: Jim Herrmann

HyperLynx V8.0

Comment: Fast / Strong Corner

Date: Monday Mar. 29, 2010 Time: 19:59:33

Cursor 1, Voltage = 5.507V, Time = 2.923ns

Cursor 2, Voltage = 1.783V, Time = 4.575ns

Delta Voltage = 3.725V, Delta Time = 1.652nsShow Latest Waveform = YES, Show Previous Waveform = YES

-3.000

-2.000

-1.000

0.00

1.000

2.000

3.000

4.000

5.000

6.000

0.00 4.000 8.000 12.000 16.000

Time (ns)

V

ol

t

ag

e-V

-

V [U7.1 (at pin)]V [U2.1 (at pin)]V [U7.1 (at pin)]V [U2.1 (at pin)]


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Digital Signaling Fundamentals CMOS output structure - the die I/O pad buffer

Modeled as a voltage source (Vs ) and series resistance (Zs) Series terminator (Zst) (optional) acts to increase the source impedance Incident wave amplitude: voltage divider across the lumped source impedance

and the line characteristic impedance (Z0)

Vi = Vs (Z0/ (Z0 + Zs+Zst)

Any impedance discontinuity along the line generates a reflection Load Impedance Special Cases Open circuit: Rc = 1

Short circuit: Rc = -1

Load = Line: Rc = 0

Reflection Coefficient Rc = (ZL - Z0) / (ZL + Z0)

Vi Vr = Vi(Rc)

Z0 ZLZs + ZST

VS


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Digital Signaling Fundamentals PWB Trace characteristic impedance (Z

0)

A function of dielectric constant, trace width, trace thickness, andtrace height above the return plane(s)

PWB Trace - propagation velocity

a function of dielectric constant (Er)

v= c / (Er)1/2

Microstrip (surface) layers: prop delay ~150 psec/inch Magnetic field propagating thru: FR4 below, solder mask, then air above

Internal stripline layers: prop delay ~165 psec/inch Magnetic field propagating thru: FR4 above and below


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High frequency signal return paths

Kirchhoffs Current Law: Sum of the currents entering and leaving a

node is zero Low frequency (sine wave < 10 MHz) return: path of least resistance

High frequency return: path of least inductance The smallest physical loop area always provides lowest inductance

Return current density in ref plane falls off with the square of the distance

The approx current density at D is proportional to 1 / (1 + (D / H)2)


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Signal Return Path Signal Layer Change

Three general cases:1. The (2) trace layers straddle

the same reference plane

2. The (2) trace layersreference different planes,both planes at same

potential, e.g. GND3. The (2) trace layers

reference different planes,planes at different DCpotential

Implications to PWB stack upand trace routing rules Case 2- apply a GND

shorting via grid acrossentire (x,y) PWB surface


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Signal Return Path Signal Layer ChangeCase 3.) The (2) trace layers reference different planes each at a different DC

potential. The return current encounters the plane capacitance impedance

thereby inducing a voltage drop across this impedance. This impedance dropsover time as the current spreads out and traverses a larger capacitive area.This return path impedance (Z) can be estimated as:Z ~ 5 ohm x [plane separation (inches) / time (nsec)]Simple stack-up shown not suitable for commuting very fast edge rate signaling (


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Return Path Common Design Issue

Signal trace routing directly over a split (or other discontinuity) in its

reference plane Closely spaced adjacent Vias anti-pad induced slots Often creates mutual inductive crosstalk (noise margin)

Case when many adjacent bus lines cross together

Can increase radiated EMI and lower radiated immunity threshold Degrades rising and falling edge rates (timing margin)


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Return Path Another Common Mistake

Signal return often overlooked / compromised in home-brew board-to-board IO connector pin assignment.

Low speed designs - Limit the ratio of signal pins to shared

return pins - Mutual inductance coupling crosstalk!

High speed designs controlled impedance connector withcontinuous GND reference recommended.

Best practice ensure that the signal trace reference plane is thesame on both boards.


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Pre-layout Phase SI Analysis

HyperLynx LineSim can be used for: Stack-up definition

Evaluate IO drive strengths and slew rates IBIS Models I/V characteristics over PVT Component family selections

Termination requirements Determine Bus Topologies, e.g., pt to pt, star, daisy-chain,

Clock Distribution Common Clock topology clock tree skew management Ensure monotonic clock edges

AC Timing guesstimate trace lengths and develop initial time-

of-flight estimates based on LineSim results Develop max and min trace length budgets to meet setup and hold

time requirements


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Clock Distribution Topology Issue Example of a simple, yet prevalent signaling problem: clock edge monotonicity.

Customer experiencing design reliability problems issue easily caught with

Hyperlynx simulation (show BoardSim tool in operation) Root cause: very poor clock routing topology, output drive strength, and termination choice

With some SI experience, would never consider such a topology (with or w/o simulation tool)

Design File: PPC_CLK_original.ffsHyperLynx L ineSim V8.0

U6.F2

MT48H32M16LFCJCLK

TL1

69.9ohms34.856ps0.211inPPC_CLK

U8.F2

MT48H32M16LFCJCLK

U7.F2

MT48H32M16LFCJCLK

U9.F2

MT48H32M16LFCJCLK

1P8V1.8VR25

220.0ohms

R24

220.0ohms

TL2


TL3


TL4


TL5


TL6

69.9ohms63.401ps0.384 inPPC_CLK

TL7


TL8


TL9

69.9ohms476.016ps2.882in

PPC_CLK

U5.U4

EP2C20F484C7_p...ppc_clk

TL10

69.9ohms363.405ps2.200in

PPC_CLK

TL11


U1.A10

Apollo7pmSYSCLK


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Controlled ImpedancePWB Stack-up

Specify dielectric thicknesses andtrace widths to achieve the samecharacteristic impedance on all signallayers (50 to 60 ohms is typical targetrange).

All signal layers ~54 ohms here 5 mil trace width on external layers

4 mil trace width on internal layers

Each signal layer has an adjacentplane return layer.

Spacing between signal layers (8 mils)is much larger than signal layer to itsreference (reduce sig-sig coupling)

Always Tradeoffs Here PWR//GNDpairs in middle giving up some PDNperformance (more inductance), butgain routing flexibility all signalsreference only GND and no splits tocontend with.


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Improper Controlled Impedance Stack-up Example from a peer design review provided for a company building

relatively high performance embedded systems Their stack-up has several issues They had adopted rather elaborate standard practice routing rules (trace to

trace separation, including layer-to-layer) to manage crosstalk problems inprevious designs (undoubtedly with this same stack-up)


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PDN Design

Significant PDN characterization and design optimization workpublished by Sun Microsystems staff since the 1990s Larry Smith (now with Altera), Ray Anderson (now with Xilinx) Istvan Novak (still at Sun) http://www.electrical-integrity.com/

Other notable research and papers (try DesignCon archives) IBM - Bruce Archambeault

Teraspeed Consulting Group Steve Weir, Scott Mc

Morrow Step-by-step PDN cookbook process very well defined by Eric

Bogatin See the second addition of his book Signal Integrity Simplified,

or visit his website www.bethesignal.com Alteras FPGA PDN design spreadsheet tool follows Erics

methodology Spreadsheet tool (newest release now requires Quartus user license) Altera application note AN-574 Printed Circuit Board Power Delivery

Network Design Methodology http://www.altera.com/technology/signal/power-distribution-network/sgl-

pdn.html?GSA_pos=2&WT.oss_r=1&WT.oss=pdn%20tool


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Power Distribution Network (PDN)

Overarching Design Principle Careful attention to MINIMIZE theinductance of the interconnects thereby reducing the voltage rail collapsenoise voltage: V = Ldi/dt

Lumped equivalent circuit model of a typical PWBA PDN:


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The PDN Design Process

1. Identify the highest current devices on the PWBA2. Determine their max actual operating current

Estimate the max load step transient current for each

3. Focus on the largest transient current device first

4. Calculate the required PDN target impedance

Ztarget = (Vnominal)(%AC ripple/100) / MaxTransientCurrent5. Estimate the IC package cutoff frequency

6. Using the PDN spreadheet tools (1-D, lumped models)

experiment with the type and quantity of capacitors required toachieve the target impedance across the frequency range

Adjust the location (within stackup), dielectric thickness, and numberof PWR // GND plane pairs to meet Ztarget over frequency range

7. Repeat process for next IC (now w/ planes locked down)


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PDN - Decoupling Capacitor Array

Decoupling Capacitors Selection and Mounting

MLCC package size and mounting inductance are the dominant factors.Recommend 0402 package with side-attach vias with minimum traceattach as the baseline high frequency decoupling capacitor footprint

Minimize

distance

0.006

High freq caps

0.006

Minimize distance

Bulk decoupling caps


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Via-in-Pad Process Option Enhances Cap Mounting

Via Non-conductive Fill-and-plate (via-in-pad)

Can reduce the mounting inductance of SMT components (w/ ~15% bare board cost adder)

Unique capability to mount 0402 caps directly to the non-component side vias of 1 mm BGA

0.010

Center of 0.0098 via hole to pad inner edge = 0.010 min.

Bulk Decoupling Cap

0.014

0.020

0.026

Center the 0.0098 vias within the 0402 SMT pads.

0402 MLCC


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PDN Decoupling Capacitor Selection Decoupling Capacitor Selection Strategies

Impedance versus frequency plots shown for (1) each 1.0 uF, 0.1uF, and 0.01

uF all same package Big-V single value array vs. Multi-value array Aside: avoid high-Q, NPO/COG capacitors some ESR provides dissipative

effect damps plane resonance


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Decoupling Capacitor Selection Strategies

Generic example of multi-value capacitor approach

Several different capacitor values (and package sizes) all applied in asneeded quantities, goal of carefully sculpting the impedance profile

9 different values, 23 total caps shown here


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Example: Stratix2 FBGA-1152 1.2V Core Voltage

Big-V approach deployed: required (58) 0402 1.0 uF X5R capacitors Via-in-pad utilized with the 1 mm BGA 16-layer PWB with 2-mil PWR//GND dielectric spacing Ztarget = 6.8 mohms, out to 50 MHz FPGA has both on package and on-die decoupling


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The PWB Layout Process

Do not toss responsibility over the fence to thePWB layout service bureau. The design teammust specify and manage:

Define Detailed Routing Constraints Define Component placement

Define the PWB stack-up

Define the Via Pad-stack

Work closely with the layout service bureau andthe PWB fabricator trust, but verify


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PWB Via Pad-stack Considerations

Via pad-stack definition - Know the IPC guidelines anddesign to your chosen DFM limits (i.e.,Class2 or Class 3)

Drill diameter

Aspect ratio: board thickness to drill diameter

Pad diameter

Anti-pad diameter

Careful attention to the anti-pad diameter keep as small aspossible - effects plane DC drop and spreading inductance belowBGAs. Do not let service bureau choose arbitrarily.

Consider eliminating via thermal relief (except for through-hole

components)


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IPC Pad-stack Guidelines As reported in Printed Circuit

Design & Manufacture, Sept 2007. Gil White, DDI Global


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PWB Stack-up Best Practice Attributes

Controlled impedance for all signal traces Every signal layer has an adjacent plane reference layer If (2) signal layers are adjacent (dual-stripline), then

provide additional separation between the signal layers ensure orthogonal routing is deployed

PWR // GND pairs thin dielectric spacing, move towards the surface layerwith highest transient current IC(s) if absolute minimum inductance needed

Split power planes very often required, must avoid trace crossing Tie all GND planes together with x,y via grid commuting signal return

current between GND layers

Know the PWB fabrication process (see IPC specs) and PWB fabricatorsmanufacturing capabilities. A few of the best:

DDI Global Merix Endicott Interconnect TTM Technologies


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Post Route Analysis

Perform after initial layout and before committingto board fabrication

HyperLynx Boardsim based analysis

Confirm that the signal integrity, AC timing, andcrosstalk goals have all been met.

Batch mode analysis capabilities can accelerate theverification process by assessing and reporting Signal time-of-flights

Overshoot levels and non-monotonic behavior Crosstalk levels


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Functional Problems Not Always a SI or PI Issue

1. Simple behavioral level logic/functional failure

Corner cases / boundary conditions

HW/SW interaction

Silicon device errata

2. Metastability

All asynchronous inputs to synchronous logic must be routed through1 or more synchronizing latches before that signal is utilized. Latches must eliminate any setup or hold time violations to succeeding

logic.

3. Worst Case AC Timing analysis neglected or incomplete Time of flight (TOF) ignored or incorrect

Lack of analysis over full PVT

Impact of SI effects not included


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Summary

Modern PWBA design the challenges are well documented

Significant information and resources are readily available

SI & PI Simulation Tools

Textbooks

White papers / App Notes

Consultants / Formal Training Classes

Read up, then develop and apply your own best practicesmethodology

Strive to enhance your technical understanding and design processwith each iteration

Join the SI-LIST email reflector for a daily dose of the state of the art http://www.freelists.org/webpage/si-list


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ReferencesText Books

Eric Bogatin, Signal Integrity - Simplified, ISBN: 0-13-066946-6.Howard Johnson, Martin Graham, High-Speed Signal Propagation Advanced Black Magic, ISBN: 0-13-084408-X.

Howard Johnson, Martin Graham, High-Speed Digital Design - A Handbook of Black Magic, ISBN: 0-13-395724-1.

Istvan Novak, Jason Miller, Frequency-Domain Characterization of Power Distribution Networks,ISBN: 978-1-59693-200-5.

S. Hall, G. Hall, J. McCall, High Speed System Design A Handbook of Interconnect Theory andPractices, ISBN: 0-471-36090-2.

S. Hall, H. Heck, Advanced Signal Integrity for High-Speed Digital Designs, ISBN: 0-471-36090-2.

Websiteswww.signalintegrity.comwww.bethesignal.comwww.electrical-integrity.com

www.teraspeed.comwww.ipblox.comhttp://www.altera.com/technology/signal/sgl-index.htmlwww.mentor.com/products/pcb-system-designwww.pcb.ddiglobal.com/Technology/index.cfm

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