Evaluation Board Set for Si5100 and Si5110 OC-48/STM-16 SONET/SDH TRANSCEIVERS
Description
The Si5100-EVB and Si5110-EVB motherboard/daughter card sets provide a platform for testing andcharacterizing Silicon Laboratories’ Si5100/Si5110SiPHYTM OC-48/STM-16 SONET/SDH Transceiver.The Si5100 and Si5110 transceiver devices provide full-duplex operation at serial data rates up to 2.7 Gbps.The transceiver device is mounted on the EVB daughtercard. The high-speed serial signals are accessed viaSMA connectors on the daughter card itself. The low-speed parallel data channels are routed from thedaughter card to the motherboard through the industry-standard 300-pin meg-array connector.
The included transceiver loopback motherboardprovides a hardware connection between thetransceiver low-speed parallel data outputs, RXDOUT,and the transceiver low-speed parallel data inputs,TXDIN. Test points are provided on the motherboard toallow monitoring of the parallel data channels. The clocksignals associated with the low-speed data channelsare routed to SMA connectors on the loopbackmotherboard. Static control and status signals arerouted to standard 100-mil center posts.
An optional full-duplex motherboard is also available forthe transceiver daughter card. The full-duplexmotherboard also utilizes the industry-standard 300-pinmeg-array connector to allow attachment of thedaughter card. The full-duplex motherboard routes all ofthe transceiver low-speed parallel data outputs andinputs to standard SMA connectors. The optional full-duplex motherboard is useful when connecting thetransceiver device to a parallel bit error rate tester(ParBERT), or in other applications that require fullaccess to the low-speed parallel data channels.
Features
Separate supply connections for VDD (1.8 V) and VDDIO (1.8 V or 3.3 V) allow LVTTL I/Os to be powered at either 1.8 V or 3.3 V.
Control inputs are jumper configurable.
Status outputs brought out to headers for easy access.
Potentiometers provided for controlling analog inputs.
Loopback Motherboard (included) provides hardware path between low-speed parallel data outputs RXDOUT and low-speed parallel data inputs TXDIN.
Optional full-duplex motherboard provides access to all low-speed parallel data outputs and inputs via SMA connectors.
Si5100/Si5110-EVB
2 Rev. 0.5
Motherboard/Daughter Card Set
300-Pin Meg-Array Connector
SMA Connectors for Parallel Interface Clock signals
Functional DescriptionThe Si5100-EVB and Si5110-EVB motherboard anddaughter card sets simplify characterization of the OC-48/STM-16 and FEC transceiver devices by providingconvenient access to the device I/Os. Deviceperformance can be evaluated in various modes byfollowing the “Basic Test Setup” section.
Power SupplyThe transceiver device can be powered from a single1.8 V supply or seperate 1.8 V and 3.3 V supplies.When the additional 3.3 V supply is applied, the statusoutputs are LVTTL compatible. The daughter card canbe configured for either mode of operation by setting theVDD_IO SEL jumper as shown in Figure 4.
Figure 4. VDD_IO Selection Jumpers
Control InputsThe device control inputs are located on themotherboard and daughter card. Signals with equivalentmodule functions are routed to the motherboard header,JP1. Signals specific to the transceiver are routed onthe daughter card to jumpers JP1 and JP2. In bothcases, the signal is routed to the center pin of a threepin group where the adjacent pins are power andground. The device inputs are pulled high or low so thatleaving a signal unconnected will not harm the device.
Status OutputsThe device status outputs are located on themotherboard and daughter card. Signals with equivalentmodule functions are routed to the motherboard header,JP2. Signals specific to the transceiver are routed onthe daughter card to headers JP3 and JP4. In bothcases, the signal is routed to a header pin adjacent to aground pin.
Data I/O SignalsThe serial 2.5 Gbps data and 2.5 GHz clock paths arerouted as coplanar differentially-coupled microstriptransmission lines on the daughter card. These threesignals (RXDIN, TXCLKOUT, and TXDOUT) are accoupled to standard SMA jacks for ease in connectionto industry standard test equipment. Take care whenconnecting cables to these jacks. Use a standard SMAtorque wrench to minimize reflections at the cable-to-jack interface. Finally, match all differential connectionsin length to minimize phase differences between thepositive and negative terminals.
Differential Parallel Data and Clock I/O SignalsThe differential parallel data lines are routed through the300-pin meg-array connector to the motherboard. Thestandard loopback motherboard directly couples theRXDOUT bus to the TXDIN bus. The optional full-duplex motherboard directly couples the RXDOUT andTXDIN buses to standard SMA jacks for connection toindustry standard test equipment.
Slice Level, Loss-of-Signal Level, and Phase AdjustVoltages present at the Slice Level (SLICELVL), Loss-of-Signal Level (LOSLVL) and Phase Adjust(PHASEADJ) pins can be used to adjust the data slicinglevel, the loss-of-signal alarm level, and the samplingphase position, respectively. Because these inputs arehigh impedance, simple turn-based potentiometers areused to apply the control voltage. The Si5100-EVBprovides 50 k potentiometers for each of these inputs:potentiometer R16 sets the voltage applied to theSLICELVL pin; R14 sets the voltage applied to theLOSLVL pin, and R15 sets the voltage applied to thePHASEADJ pin. The Si5110-EVB also provides 50 kpotentiometers for each of these inputs. PotentiometerR5 sets the voltage applied to the SLICELVL pin; R3sets the voltage applied to the LOSLVL pin, and R4 setsthe voltage applied to the PHASEADJ pin. Thepotentiometers are connected so the voltage appliedvaries from GND to VREF. Refer to the device datasheet for details on the operation of these inputs.
Basic Test SetupThe configurations listed in Tables 1 and 3 allow easysetup of the transceiver evaluation system for operationin the line loopback, full duplex, or diagnostic loopbackmodes. Other configurations are supported; however,operation should first be verified in one of these modesin order to minimize the number of unknown variables.
For 1.8 V operation only
VDD_IOSEL
For 3.3 V/1.8 V operation
VDD_IOSEL
1.8 V
3.3 V
1.8 V
3.3 V
Si5100/Si5110-EVB
6 Rev. 0.5
Line Loopback
When configured in line-loopback mode, the devicepasses the received/recovered data and timing to thetransmitter. The transmitter buffers the data through theFIFO and filters the jitter using the loop-bandwidthselected by BWSEL[1:0]. Operation in line loopbackmode is depicted in Figure 5. Jumper settings for lineloopback mode are given in Tables 1, 3 (Si5100), and 4(Si5110). This mode of operation is attainable with bothversions of the motherboard.
Full-Duplex
This mode is identical to normal operation of the devicein a system. TX and RX can be asynchronous (up to±300 ppm) so all timing is independent. TXCLK16IN ischosen as the transmitter CMU reference clock via theREFSEL pin. Operation in full-duplex mode is depictedin Figure 6. Jumper settings for full-duplex mode aregiven in Tables 1, 3 (Si5100), and 4 (Si5110). If theloopback motherboard is used, the full-duplex modeeffectively becomes an external loopback mode, andRXCLK1 should be connected to TXCLK16IN/TXCLK4IN to clock in the data.
Diagnostic Loopback (Parallel Side Loopback)
This mode passes the data present on the transmitparallel inputs (TXDIN[15:0] for Si5100; TXDIN[3:0] forSi5110) to the receive parallel data outputs(RXDOUT[15:0] for Si5100; RXDOUT[3:0] for Si5110).TXCLK16IN/TXCLK4IN is chosen as the transmitterCMU reference clock via the REFSEL pin. Operation indiagnostic loopback mode is depicted in Figure 7.Jumper settings for diagnostic loopback mode are givenin Tables 2, 3 (Si5100), and 4 (Si5110). The full-duplexmotherboard is required for this mode.
Figure 5. Line Loopback
Figure 6. Full Duplex
Figure 7. Diagnostic Loopback
RXDIN
TXDOUT
TXCLK
RXCLK1
RXDOUT
TXDIN
TXCLK16IN/TXCLK4IN
Si5100/Si5110
Receiver
Transmitter
TXREFCLK
RXDIN
TXDOUT
TXCLK
RXCLK1
RXDOUT
Si5100/Si5110
Receiver
Transmitter
TXDIN
TXCLK16IN/TXCLK4IN
TXREFCLK
RXDIN
TXDOUT
TXCLK
RXCLK1
RXDOUT
Si5100/Si5110
Receiver
Transmitter
TXDIN
TXCLK16IN/TXCLK4IN
TXREFCLK
Si5100/Si5110-EVB
Rev. 0.5 7
Both the motherboard and daughter card are placed in line loopback mode before shipment to customers.
Table 1. Loopback Motherboard Setup
Header—Pin Signal Name Line Loopback Asynchronous TX/RX
JP10—2 Voltage Select 3.3 V 3.3 V
JP1—14 RXCLK1DSBL_N high high
JP1—11 LTR_N high high
JP1—8 RXSQLCH_N low high
JP1—5 RXCLK2DIV_N don’t care don’t care
JP1—2 RXCLK2DSBL_N don’t care don’t care
JP2—5 TXREFRATE high high
JP2—2 TXRESET_N high high
JP3—8 DLBK_N high high
JP3—5 LLBK_N low (enables line loopback) high
JP3—2 LPTM_N high high
JP7—5 RXREFRATE open open
JP7—2 RXRESET_N high high
JP6—4 FIFORST_N tie to FIFOERR tie to FIFOERR
Table 2. Full-Duplex Motherboard Setup
Header—Pin Signal Name Line Loopback Asynchronous TX/RX Diagnostic Loopback
JP8—2 Voltage Select 3.3 V 3.3 V 3.3 V
JP1—14 RXCLK1DSBL_N high high high
JP1—11 LTR_N high high high
JP1—8 RXSQLCH_N low high high
JP1—5 RXCLK2DIV_N don’t care don’t care don’t care
JP1—2 RXCLK2DSBL_N don’t care don’t care don’t care
JP2—5 REFRATE high high high
JP2—2 RESET_N high high high
JP3—8 DLBK_N high high low
JP3—5 LLBK_N low (enables line loopback) high high
JP3—2 LPTM_N high high high
JP7—5 Si5530 REFRATE open open open
JP7—2 Si5530 RESET_N high high high
JP6—4 FIFORST_N tie to FIFOERR tie to FIFOERR tie to FIFOERR
Table 3. Si5100 Daughter Card Setup
Header—Pin Signal Name Line Loopback Asynchronous TX/RX Diagnostic Loopback
JP1—20 BWSEL0BWSEL1
11(for widest CMU loop
bandwidth)
11(for widest CMU loop
bandwidth)
11(for widest CMU loop
bandwidth)JP1—23
JP1—17 REFSEL high high high
JP1—14 MODE16 high high high
JP1—11 TXCLKDSBL low low low
JP1—8 TXMSBSEL low low low
JP1—5 TXSQLCH_N high high high
JP1—2 RXMSBSEL low low low
Note: Jump the VDD_IO selection jumper toward the 3.3 V side.
Si5100/Si5110-EVB
8 Rev. 0.5
Table 4. Si5110 Daughter Card Setup
Header—Pin Signal Name Line Loopback Asynchronous TX/RX Diagnostic Loopback
JP1—20 BWSEL0BWSEL1
11(for widest CMU loop
bandwidth)
11(for widest CMU loop
bandwidth)
11(for widest CMU loop
bandwidth)JP1—23
JP1—17 REFSEL high high high
JP1—14 TXCLKDSBL low low low
JP1—11 TXMSBSEL low low low
JP1—8 TXSQLCH_N high high high
JP1—5 SLICEMODE low low low
JP1—2 RXMSBSEL low low low
Note: Jump the VDD_IO selection jumper toward the 3.3 V side.
JP2 CONN,HEADER,4X3 2380-6121TN or 2340-6111TN 3MJP3, JP10 CONN,HEADER,2X1 2380-6121TN or 2340-6111TN 3MJP11 CONN,HEADER,1X3 2380-6121TN or 2340-6111TN 3M
Si5100/Si5110-EVB
Rev. 0.5 17
Layout N
ote
: A
ll lo
opback d
ata
pairs h
ave testp
oin
ts to facili
tate
pro
bin
g a
ccess.
MO
TH
ER
BO
AR
D
OU
TP
UT
SIG
NA
L
VO
LT
AG
E S
ELE
CT
3.3
V/1
.8V
-5.2
V/5
V
DATA8+DATA8-
DATA11-
DATA13+
DATA12+
DATA15+
DATA12-
DATA13-
DATA14-
DATA15-
DATA14+
DATA10-
DATA9+
DATA10+DATA9-
DATA11+
RX
RE
FC
LK
+
RX
RE
FC
LK
-
TX
CLK
16IN
-
TX
CLK
16IN
+
TX
RE
FC
LK
-
TX
RE
FC
LK
+
RX
CL
K2+
TX
CLK
16O
UT
+
TX
CLK
16O
UT
-
RX
CL
K2
-
RX
CL
K1
-
RX
CL
K1+
TX
CLK
16IN
+T
XC
LK
16IN
-
TX
CLK
16O
UT
+T
XC
LK
16O
UT
-
RX
CL
K1+
RX
CL
K1
-
1.8
V3
.3V
5V
-5.2
V1
.8V
VM
BO
3.3
V
R1
4
06
03
, 0
oh
m
J1
E
Me
g-A
rra
y 3
00
E1
E2
E3
E4
E5
E6
E7
E8
E9
E1
0E
11
E1
2E
13
E1
4E
15
E1
6E
17
E1
8E
19
E2
0E
21
E2
2E
23
E2
4E
25
E2
6E
27
E2
8E
29
E3
0
J4
SM
A
J1
5
MK
DS
N 2
,5/3
-5,0
8
1 2 3
PO
S1
PO
S2
PO
S3
JP
10
R1
0
06
03
, 0
oh
m
R9
06
03
, 0
oh
m
R7
06
03
, 0
oh
m
R1
1
06
03
, 0
oh
m
R6
06
03
, 0
oh
m
R1
2
06
03
, 0
oh
m
R8
06
03
, 0
oh
m
J6
SM
A
J1
G
Me
g-A
rra
y 3
00
G1
G2
G3
G4
G5
G6
G7
G8
G9
G1
0G
11
G1
2G
13
G1
4G
15
G1
6G
17
G1
8G
19
G2
0G
21
G2
2G
23
G2
4G
25
G2
6G
27
G2
8G
29
G3
0
J2
SM
A
J8
SM
A
TP
17
1In
J3
SM
A
R1
6
06
03
, 0
oh
m
TP
19
1In
J5
SM
A
TP
21
1In
TP
18
1In
J7
SM
A
TP
23
1In
TP
20
1In
J9
SM
A
R5
06
03
, 0
oh
m
TP
25
1In
TP
22
1In
TP
27
1In
TP
24
1In
TP
29
1In
TP
26
1In
J1
1
SM
A
TP
31
1In
TP
28
1In
J1
3
SM
A
TP
30
1In
J1
4
MK
DS
N 2
,5/3
-5,0
8
1 2 3
PO
S1
PO
S2
PO
S3T
P32
1In
J1
0
SM
A
R1
3
06
03
, 0
oh
m
R1
5
06
03
, 0
oh
m
J1
2
SM
A
Fig
ure
14.
Lo
op
bac
k M
oth
erb
oar
d S
chem
atic
(p
age
1 o
f 2)
Si5100/Si5110-EVB
18 Rev. 0.5
Pla
ced togeth
er
to
allow
jum
pering o
f
FIF
OE
RR
_N
to
FIF
OR
ST
74244 D
ecoupling C
aps
LE
D E
NA
BL
E/
DIS
AB
LE
DATA4-
DATA5-DATA5+
DATA4+
DATA6+DATA6-DATA7+DATA7-
DATA2-DATA3+
DATA0-DATA0+
DATA1+
DATA3-
DATA2+DATA1-
TX
RE
FR
AT
E
DL
BK
_N
LL
BK
_N
LP
TM
_N
RX
CL
K2
DS
BL
_N
FIF
OR
ST
_N
TX
RE
SE
T_N
TX
LO
L_N
LO
S_
N
FIF
OE
RR
_N
RX
CL
K1
DS
BL
_N
TX
RE
SE
T_N
DL
BK
_N
LL
BK
_N
TX
RE
FR
AT
E
LP
TM
_N
LO
S_
N
FIF
OR
ST
_N
RX
RE
SE
T_N
RX
RE
FR
AT
E
RX
CL
K1
DS
BL
_N
RX
CL
K2
DS
BL
_N
RX
CL
K2
DIV
_N
RX
SQ
LC
H_
N
LT
R_
N
RX
CL
K2+
RX
CL
K2
-
LO
S_
N
TX
LO
L_N
RX
LO
L_N
FIF
OE
RR
_N
LT
R_
N
RX
LO
L_N
RX
LO
L_N
RX
SQ
LC
H_
N
TX
LO
L_N
RX
CL
K2
DIV
_N
TX
RE
FC
LK
-T
XR
EF
CLK
+
RX
RE
FC
LK
+R
XR
EF
CL
K-
FIF
OE
RR
_N
RX
RE
SE
T_
N
RX
RE
FR
AT
E
1.8
V
VM
BO
3.3
V-5
.2V
5V
3.3
V
3.3
V
3.3
V
TP
12
1In
C2
04
02
10
0p
F
TP
14
1In
TP
16
1In
J1
F
Me
g-A
rra
y 3
00
F1
F2
F3
F4
F5
F6
F7
F8
F9
F1
0F
11
F1
2F
13
F1
4F
15
F1
6F
17
F1
8F
19
F2
0F
21
F2
2F
23
F2
4F
25
F2
6F
27
F2
8F
29
F3
0
JP
1
HE
AD
ER
5X
3
21 3 4
56 7
89 1
01
11
21
31
41
5
D3
D4
TP
71
In
TP
91
In
J1
D
Me
g-A
rra
y 3
00
D1
D2
D3
D4
D5
D6
D7
D8
D9
D1
0D
11
D1
2D
13
D1
4D
15
D1
6D
17
D1
8D
19
D2
0D
21
D2
2D
23
D2
4D
25
D2
6D
27
D2
8D
29
D3
0
TP
11
1In
J1
J
Me
g-A
rra
y 3
00
K1
K2
K3
K4
K5
K6
K7
K8
K9
K1
0K
11
K1
2K
13
K1
4K
15
K1
6K
17
K1
8K
19
K2
0K
21
K2
2K
23
K2
4K
25
K2
6K
27
K2
8K
29
K3
0
TP
13
1In
J1
I
Me
g-A
rra
y 3
00
J1
J2
J3
J4
J5
J6
J7
J8
J9
J1
0J1
1J1
2J1
3J1
4J1
5J1
6J1
7J1
8J1
9J2
0J2
1J2
2J2
3J2
4J2
5J2
6J2
7J2
8J2
9J3
0
TP
15
1In
R1
36
5r
06
03
TP
21
In
JP
8
HE
AD
ER
3X
2
1 3 5
2 4 6
R4
36
5r
06
03
R2
36
5r
06
03
JP
7
HE
AD
ER
2X
3
21 3 4
56
JP
31
x3
HE
AD
ER
12
31
23
J1
H
Me
g-A
rra
y 3
00
H1
H2
H3
H4
H5
H6
H7
H8
H9
H1
0H
11
H1
2H
13
H1
4H
15
H1
6H
17
H1
8H
19
H2
0H
21
H2
2H
23
H2
4H
25
H2
6H
27
H2
8H
29
H3
0
R3
36
5r
06
03
JP
5
HE
AD
ER
1X
2
12
TP
11
InJ1
A
Me
g-A
rra
y 3
00
A1
A2
A3
A4
A5
A6
A7
A8
A9
A1
0A
11
A1
2A
13
A1
4A
15
A1
6A
17
A1
8A
19
A2
0A
21
A2
2A
23
A2
4A
25
A2
6A
27
A2
8A
29
A3
0
TP
31
In
J1
B
Me
g-A
rra
y 3
00
B1
B2
B3
B4
B5
B6
B7
B8
B9
B1
0B
11
B1
2B
13
B1
4B
15
B1
6B
17
B1
8B
19
B2
0B
21
B2
2B
23
B2
4B
25
B2
6B
27
B2
8B
29
B3
0
D1
JP
6
HE
AD
ER
1X
3
21 3
TP
51
In
D2
JP
4
HE
AD
ER
3X
3
21 3 4
56 7
89
J1
C
Me
g-A
rra
y 3
00
C1
C2
C3
C4
C5
C6
C7
C8
C9
C1
0C
11
C1
2C
13
C1
4C
15
C1
6C
17
C1
8C
19
C2
0C
21
C2
2C
23
C2
4C
25
C2
6C
27
C2
8C
29
C3
0
C1
04
02
0.1
uF
TP
41
In
JP
2
HE
AD
ER
2X
3
21 3 4
56
TP
61
In
TP
81
In
U1
74
LC
X2
44
T,
20T
SS
OP
1
2 4 6 8
11
13
15
17
19
18
16
14
12
9 7 5 3
20
10
1O
E
1A
11
A2
1A
31
A4
2A
12
A2
2A
32
A4
2O
E
1Y
11
Y2
1Y
31
Y4
2Y
12
Y2
2Y
32
Y4
VC
C
GN
D
TP
10
1In
Fig
ure
15.
Lo
op
bac
k M
oth
erb
oar
d S
chem
atic
(p
age
2 o
f 2)
Si5100/Si5110-EVB
Rev. 0.5 19
Bill of Materials: Loopback Motherboard Assembly Revision A-01
Si5100 Loopback Motherboard Assy Rev A-01
Reference Part Desc Part Number Manufacturer
C1 CAP,SM,0.1UF,16V,10%,X7R,0402 C0402X7R160-104KNE VENKELC2 CAP,SM,100PF,50V,5%,C0G,0402 C0402C0G500-101JNE VENKELD1,D2,D3,D4 LED,SM,RED LN1271RAL-TR PANASONICJP1 CONN,HEADER,5X3 2380-6121TN or 2340-6111TN 3MJP2,JP7 CONN,HEADER,2X3 2380-6121TN or 2340-6111TN 3MJP3,JP6 CONN,HEADER,1X3 2380-6121TN or 2340-6111TN 3MJP4 CONN,HEADER,3X3 2380-6121TN or 2340-6111TN 3MJP5 CONN,HEADER,1X2 2380-6121TN or 2340-6111TN 3MJP8 CONN,HEADER,3X2 2380-6121TN or 2340-6111TN 3MJP10 CONN,HEADER,3X1 2380-6121TN or 2340-6111TN 3MJ1 CONNECTOR,SM,300 POS,BGA 84500-02 BERGJ2,J3,J4,J5,J6,J7,J8,J9, CONNECTOR,SMA,SURFACE MOUNT 142-0711-201 JOHNSON COMPONENTSJ10,J11,J12,J13J15,J14 CONNECTOR,POWER,3 POSITION 1729021 PHOENIX CONTACTR1,R2,R3,R4 RESISTOR, SM, 365 OHM, 1%, 0603 CR0603-16W-121JT VENKELR5,R6,R7,R8,R9,R10,R11, RES,SM,0,0402 CR0402-16W-000T VENKELR12,R13,R14,R15,R16TP1,TP2,TP3,TP4,TP5,TP6, TEST POINTS ON PCB N/A N/ATP7,TP8,TP9,TP10,TP11,TP12,TP13,TP14,TP15,TP16,TP17,TP18,TP19,TP20,TP21,TP22,TP23,TP24,TP25,TP26,TP27,TP28,TP29,TP30,TP31,TP32U1 IC,SM,74LCX244,20TSSOP 74LCX244MTC FAIRCHILDPCB Printed Circuit Board Si5100-EVB Loopback Motherboard PCB Rev A SILICON LABORATORIES
Si5100/Si5110-EVB
20 Rev. 0.5
RX
DO
UT
11-
RX
DO
UT
11+
RX
DO
UT
10-
RX
DO
UT
10+
RX
DO
UT
9-
RX
DO
UT
9+
RX
DO
UT
8-
RX
DO
UT
8+
RX
DO
UT
7-
RX
DO
UT
7+
RX
DO
UT
6-
RX
DO
UT
6+
RX
DO
UT
12+
RX
DO
UT
12-
RX
DO
UT
13+
RX
DO
UT
13-
RX
DO
UT
14+
RX
DO
UT
14-
RX
DO
UT
15+
RX
DO
UT
15-
RX
CL
K2+
RX
CL
K2
-
RX
CL
K1+
TX
CLK
16O
UT
-
RX
CL
K1
-
RX
DO
UT
3+
RX
DO
UT
0+
RX
DO
UT
1-
RX
DO
UT
4-
RX
DO
UT
1+
RX
DO
UT
2-
RX
DO
UT
5-
RX
DO
UT
2+
RX
DO
UT
3-
RX
DO
UT
0-
RX
DO
UT
5+
RX
DO
UT
4+
TX
CLK
16O
UT
+
TX
DIN
0+
TX
DIN
0-
TX
DIN
1+
TX
DIN
1-
TX
DIN
2+
TX
DIN
2-
TX
DIN
3+
TX
DIN
3-
TX
DIN
4+
TX
DIN
4-
TX
DIN
5+
TX
DIN
5-
TX
DIN
6+
TX
DIN
6-
TX
DIN
7+
TX
DIN
7-
TX
DIN
13
-
TX
DIN
13+
TX
DIN
12
-
TX
DIN
12+
TX
DIN
11
-
TX
DIN
11+
TX
DIN
10
-
TX
DIN
10+
TX
DIN
9-
TX
DIN
9+
TX
DIN
8-
TX
DIN
8+
TX
DIN
14+
TX
DIN
14
-
TX
DIN
15+
TX
DIN
15
-
RX
RE
FC
LK
+
RX
RE
FC
LK
-
Si5
53
0_
RE
FC
LK
+
Si5
53
0_
RE
FC
LK
-
TX
CLK
16IN
+
TX
CLK
16IN
-
R5
3
06
03
, 0
oh
m
J2
6
R3
6
06
03
, 0
oh
m
R2
2
06
03
, 0
oh
m
J2
7
R4
7
06
03
, 0
oh
m
R1
1
06
03
, 0
oh
m
J2
8
R1
06
03
, 0
oh
m
J2
9
R7
3
06
03
, 0
oh
m
J3
0R
54
06
03
, 0
oh
m
J3
1
R2
3
06
03
, 0
oh
m
J3
2
R4
8
06
03
, 0
oh
m
R2
7
06
03
, 0
oh
m
R1
2
06
03
, 0
oh
m
R6
9
06
03
, 0
oh
m
R3
7
06
03
, 0
oh
m
J3
3
R6
5
06
03
, 0
oh
m
J3
4
J3
7
J3
5
R6
6
06
03
, 0
oh
m
J3
8
R5
5
06
03
, 0
oh
m
J3
6
J3
9
R2
4
06
03
, 0
oh
m
R6
7
06
03
, 0
oh
m
R2
8
06
03
, 0
oh
m
J4
0
R7
0
06
03
, 0
oh
m
R3
9
06
03
, 0
oh
m
J4
1
R6
8
06
03
, 0
oh
m
J6
5
SM
A
J4
2
R3
06
03
, 0
oh
m
J6
6
SM
A
J4
3
R5
6
06
03
, 0
oh
m
J6
7
SM
A
J4
4
R7
4
06
03
, 0
oh
m
R2
9
06
03
, 0
oh
m
R1
5
06
03
, 0
oh
m
J6
8
SM
A
J4
5
R7
1
06
03
, 0
oh
m
R4
0
06
03
, 0
oh
m
J6
9
SM
A
J4
6J7
0 SM
A
J4
7
R4
06
03
, 0
oh
m
J7
1
SM
A
J4
8
R5
7
06
03
, 0
oh
m
J7
2
SM
A
J4
9
R3
0
06
03
, 0
oh
m
R1
6
06
03
, 0
oh
m
J7
3
SM
A
J5
0
R7
2
06
03
, 0
oh
m
R4
1
06
03
, 0
oh
m
R6
1
06
03
, 0
oh
m
J7
4
SM
A
J5
1J7
5
SM
A
J5
2
R5
06
03
, 0
oh
m
J7
6
SM
A
J5
3
R5
8
06
03
, 0
oh
m
R2
5
06
03
, 0
oh
m
J1
J5
4
R3
1
06
03
, 0
oh
m
R1
7
06
03
, 0
oh
m
J2
J5
5
R4
2
06
03
, 0
oh
m
R6
06
03
, 0
oh
m
R2
06
03
, 0
oh
m
R6
3
06
03
, 0
oh
m
R1
3
06
03
, 0
oh
m
J3
J5
6
R6
2
06
03
, 0
oh
m
R5
0
06
03
, 0
oh
m
J4
J5
7
J5
J5
8
R5
9
06
03
, 0
oh
m
R3
8
06
03
, 0
oh
m
J6
J5
9
R3
2
06
03
, 0
oh
m
R1
8
06
03
, 0
oh
m
J7
J6
0
R4
3
06
03
, 0
oh
m
R1
4
06
03
, 0
oh
m
R7
06
03
, 0
oh
m
R6
4
06
03
, 0
oh
m
J8
J6
1
J9
J6
2
J1
0
J6
3
R6
0
06
03
, 0
oh
m
R4
9
06
03
, 0
oh
m
J1
1
J6
4
R3
3
06
03
, 0
oh
m
R1
9
06
03
, 0
oh
m
J1
2
R4
4
06
03
, 0
oh
m
R8
06
03
, 0
oh
m
J1
3
R2
6
06
03
, 0
oh
m
J1
4
J1
5R
51
06
03
, 0
oh
m
J1
6
R3
4
06
03
, 0
oh
m
R2
0
06
03
, 0
oh
m
J1
7
R4
5
06
03
, 0
oh
m
R9
06
03
, 0
oh
m
J1
8
R7
5
06
03
, 0
oh
m
J1
9
J2
0
R5
2
06
03
, 0
oh
m
J2
1
R3
5
06
03
, 0
oh
m
R2
1
06
03
, 0
oh
m
J2
2R
46
06
03
, 0
oh
m
R1
0
06
03
, 0
oh
m
J2
3
R7
6
06
03
, 0
oh
m
J2
4
J2
5
Fig
ure
16.
Fu
ll-D
up
lex
Mo
ther
bo
ard
Sch
emat
ic (
pag
e 1
of
2)
Si5100/Si5110-EVB
Rev. 0.5 21
Pla
ced togeth
er
to
allo
w ju
mpering o
f
FIF
OE
RR
to
FIF
OR
ST
TX
LO
L_N
RX
RE
FC
LK
+R
XR
EF
CLK
-
TX
DIN
0+
TX
DIN
0-
TX
DIN
1+
TX
DIN
1-
TX
DIN
2+
TX
DIN
2-
TX
DIN
3+
TX
DIN
3-
Si5
530_R
EF
CLK
+S
i5530_R
EF
CLK
-
TX
DIN
5+
TX
DIN
6+
TX
DIN
6-
TX
DIN
4-
TX
DIN
5-
TX
DIN
7+
TX
DIN
7-
TX
DIN
4+
TX
DIN
11
-
TX
DIN
8-
TX
DIN
9-
TX
DIN
10+
TX
DIN
9+
TX
DIN
11+
TX
DIN
8+
TX
DIN
10
-
TX
DIN
13-
TX
CLK
16IN
+T
XC
LK
16IN
-
TX
DIN
12-
TX
DIN
14-
TX
DIN
15-
TX
DIN
14+
TX
DIN
12+
TX
DIN
13+
TX
DIN
15+
RX
SQ
LC
H_N
LT
R_N
RX
CLK
2D
IV_N
RE
FR
AT
E
DLB
K_N
LLB
K_N
LP
TM
_N
RX
CLK
2D
SB
L_N
FIF
OR
ST
_N
RE
SE
T_N
RX
DO
UT
0+
RX
DO
UT
0-
RX
DO
UT
1-
RX
DO
UT
1+
RX
DO
UT
2-
RX
DO
UT
2+
RX
DO
UT
3-
RX
DO
UT
3+
RX
DO
UT
4+
RX
DO
UT
4-
RX
DO
UT
5+
RX
DO
UT
5-
RX
DO
UT
6+
RX
DO
UT
6-
RX
DO
UT
7+
RX
DO
UT
7-
RX
CL
K2+
RX
CL
K2
-
RX
DO
UT
8+
RX
DO
UT
8-
RX
DO
UT
9+
RX
DO
UT
9-
RX
DO
UT
10+
RX
DO
UT
10-
RX
DO
UT
11+
RX
DO
UT
11-
RX
CL
K1+
RX
CL
K1
-
TX
CLK
16O
UT
+T
XC
LK
16O
UT
-
RX
DO
UT
12-
RX
DO
UT
12+
RX
DO
UT
13-
RX
DO
UT
13+
RX
DO
UT
14-
RX
DO
UT
14+
RX
DO
UT
15-
RX
DO
UT
15+
RX
LO
L_N
TX
LO
L_N
LO
S_N
FIF
OE
RR
_N
RX
CLK
1D
SB
L_N
Si5
530_R
EF
RA
TE
Si5
530_R
ES
ET
_N
RE
SE
T_N
DLB
K_N
LLB
K_N
RE
FR
AT
E
LP
TM
FIF
OE
RR
_N
LO
S_N
RX
LO
L_N
FIF
OR
ST
_N
Si5
530_R
ES
ET
_N
Si5
530_R
EF
RA
TE
RX
CLK
1D
SB
L_N
RX
CLK
2D
SB
L_N
RX
CLK
2D
IV_N
RX
SQ
LC
H_N
LT
R_N
1.8
V
3.3
V
3.3
V
3.3
V1.8
V
3.3
VJ77F
Meg-A
rray 3
00
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
JP
1
HE
AD
ER
5X
3
21 3 4
56 7
89 10
11
12
13
14
15
J77E
Meg-A
rray 3
00
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
J77D
Meg-A
rray 3
00
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
J77J
Meg-A
rray 3
00
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
J77I
Meg-A
rray 3
00
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
JP
4
HE
AD
ER
3X
2
1 3 5
2 4 6
J77G
Meg-A
rray 3
00
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
JP
7
HE
AD
ER
2X
3
21 3 4
56
J77H
Meg-A
rray 3
00
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
JP
5
HE
AD
ER
3X
2
12
J78
MK
DS
N 2
,5/3
-5,0
8
1 2 3
PO
S1
PO
S2
PO
S3
J77A
Meg-A
rray 3
00
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
J77B
Meg-A
rray 3
00
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
JP
6
HE
AD
ER
2X
3
21 3
JP
3
HE
AD
ER
3X
3
21 3 4
56 7
89
J77C
Meg-A
rray 3
00
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
JP
2
HE
AD
ER
2X
3
21 3 4
56
Fig
ure
17.
Fu
ll-D
up
lex
Mo
ther
bo
ard
Sch
emat
ic (
pag
e 2
of
2)
Si5100/Si5110-EVB
22 Rev. 0.5
Bill of Materials: Full-Duplex Motherboard Assembly Revision C-01
Si5100 Motherboard Assy Rev C-01 BOM
Reference Part Desc Part Number ManufacturerR1,R2,R3,R4,R5,R6,R7,R8, RES,SM,0,0402 CR0402-16W-000T VENKELR9,R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,R20,R21,R22,R23,R24,R25,R26,R27,R28,R29,R30,R31,R32,R33,R34,R35,R36,R37,R38,R39,R40,R41,R42,R43,R44,R45,R46,R47,R48,R49,R50,R51,R52,R53,R54,R55,R56,R57,R58,R59,R60,R61,R62,R63,R64,R65,R66,R67,R68,R69,R70,R71,R72,R73,R74,R75,R76JP1 CONNECTOR,HEADER,5X3 2340-6111TN or 2380-6121TN 3MJP2,JP4,JP7 CONNECTOR,HEADER,3X2 2340-6111TN or 2380-6121TN 3MJP3 CONNECTOR,HEADER,3X3 2340-6111TN or 2380-6121TN 3MJP5 CONNECTOR,HEADER,2X1 2340-6111TN or 2380-6121TN 3MJP6 CONNECTOR,HEADER,3X1 2340-6111TN or 2380-6121TN 3MJ1,J2,J3,J4,J5,J6,J7,J8, CONNECTOR,SMA,SURFACE MOUNT 142-0711-201 JOHNSON COMPONENTSJ9,J10,J11,J12,J13,J14,J15,J16,J17,J18,J19,J20,J21,J22,J23,J24,J25,J26,J27,J28,J29,J30,J31,J32,J33,J34,J35,J36,J37,J38,J39,J40,J41,J42,J43,J44,J45,J46,J47,J48,J49,J50,J51,J52,J53,J54,J55,J56,J57,J58,J59,J60,J61,J62,J63,J64,J65,J66,J67,J68,J69,J70,J71,J72,J73,J74,J75,J76J77 CONNECTOR,SM,300 POS,BGA 84500-02 BERGJ78 CONNECTOR,POWER,3 POSITION 1729021 PHOENIX CONTACTPCB Printed Circuit Board Si5100-EVB Motherboard PCB Rev C SILICON LABORATORIES
Si5100/Si5110-EVB
Rev. 0.5 23
Figure 18. Si5100-EVB Component Side Assembly (Daughter Card)
Figure 19. Si5100-EVB Solder Side Assembly (Daughter Card)
Si5100/Si5110-EVB
24 Rev. 0.5
Figure 20. Si5100-EVB Layer 1—Component Side (Daughter Card)
Figure 51. Layer 6—Solder Side (Optional Full-Duplex Motherboard)
Si5100/Si5110-EVB
Rev. 0.5 47
Document Change List
Revision 0.4 to Revision 0.5
Split Table 3 into Tables 3 and 4 to reflect differences in the actual PCBs for the Si5100 and Si5110 devices.
Updated table references to reflect the changes in Table 3 and the creation of Table 4.
Evaluation Board Assembly Revision History
Si5100-EVB Daughter Card Revision History
Assembly Level PCB Si5600 Device Assembly Notes
C-01 Rev. B Rev. C Assemble per BOM rev C-01
D-01 Rev. B Rev. D Assemble per BOM rev D-01
Full-Duplex Motherboard Revision History
Assembly Level PCB Assembly Notes
A-01 Rev. A Assemble per BOM rev A-01
B-01 Rev. B Assemble per BOM rev B-01
C-01 Rev. C Assemble per BOM rev C-01
Loopback Motherboard Revision History
Assembly Level PCB Assembly Notes
A-01 Rev. A Assemble per BOM rev A-01
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