Cadence Design Systems, Inc.

Signal and Design IntegrityApril 2002

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Technical issues in Deep Sub-Micron Design Manufacturability (Chip can’t be built)

– Antenna rules– Minimum area rules for stacked vias– CMP (Chemical Mechanical Polishing) area fill rules

Signal Integrity (failure to meet Performance targets)– Crosstalk induced errors– Timing dependence on crosstalk– IR Drop on power supplies– Substrate coupled noise

Design Integrity (reliability failures in the field)– Electromigration on power supplies– Hot electron effects on devices– Wire self heat effects on clocks and signals

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Why now?

These effects have always existed, but become worse at deep sub-micron sizes because of:

– Finer geometries – Greater wire and via resistance– Higher electric fields (if supply voltage not scaled)

– More metal layers– Higher ratio of cross coupling to grounded capacitance

– Lower supply voltages– More current for a given power

– Lower device thresholds– Smaller noise margins

Good news: Same solutions that work at 150 nm and 130 nm will work for next few technology generations until << 100 nm

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Crosstalk induced errors Transition on an adjoining signal causes unintended logic

transition Symptom - chip fails (repeatably) on certain logic operations

Aggressor net

Victim net

Wire R

Drive R Grounded C

Coupling C

Input Noise Tolerance

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Timing Dependence on Crosstalk

Timing depends on behavior of adjoining signals Symptom - Timing predictions inaccurate compared to silicon.

Effect can be large: 3:1 on individual nets.

Other logic net(s)

Wire R

Grounded C Coupling C (multiplied by Miller effect)

Delay here and here depends on the behavior of other nets

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Effect of Crosstalk on Delay

-4.00E-01

-2.00E-01

0.00E+00

2.00E-01

4.00E-01

6.00E-01

8.00E-01

1.00E+00

1.20E+00

1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61

Time (ps)

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Thresholdsmin nom max

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Electromigration Power supply lines fail due to excessive current Symptom: Chip eventually fails in the field when the wire

breaks

Currents depend on currentsof other cells

PadPower supplynetwork consistsof wires of varyingsizes; they must be bigenough, but too big wastes area

Currents depend on driver type,loads, and how often cell isswitched

Current limit depends on wire size

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IR Drop Voltage drop in supply lines from currents drawn by cells Symptom: chip malfunctions on certain vectors Biggest problem - what’s the worst case vector?

Voltages depend on currentsof other cells

PadPower supplynetwork consistsof wires of varyingsizes; they must be bigenough, but too big wastes area

Currents depend on driver type,loads, and how often cell isswitched

Allowablevoltagedrop at pin

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Hot Electron Effects May also be called short channel effect Caused by extremely high electric fields in the channel

– Occurs when voltages are not scaled as fast as dimensions Effect becomes worse as devices are turned on harder Symptom: Thresholds shift over time until chip fails

N+ diffusion

Gate

Oxide and/or interfaceis damaged here

Electrons pick up speed in channel;‘hot’ electrons are the fastest of astatistically fast bunch

Impact ionization occurs here

+++

+++

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Hot Electron Effect (cont)

Depends on how hard device is driven (input slew rate) And on the size of the load

Vds

Vgs

Trajectory with large C, fast Tin

Trajectory with small C, slow Tin

Contours of constanthot electron flux

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Wire Self Heat May also be called signal wire electromigration Wire heats above oxide temperature as pulses go through Symptom: Chip eventually fails when wire breaks Depends on metal composition, signal frequency, wire sizes,

slew rates, and amount of capacitance driven Requires different data/formulas from power supply EM

Oxide Metal

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Package

Substrate Noise

Currents injected by high speed switching of digital devices Supply currents injected via substrate contacts

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Analog Noise in Custom Digital ICs

CLK

Gnd2

Supply Noise

Vdd2

Gnd1

Vdd1

Supply Noise

Crosstalk

PropagatedNoise

Charge Sharing

Leakage

“0”

Overshoot(TDDB)

Undershoot(TDDB)

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What can tools do about these problems?

Accurate Analysis– Make sure real problems are caught– Avoid fixing problems that aren’t really there– For analog issues, such as substrate noise, this is about all we can

do. The user must decide how to fix the problemTools can try to prevent or avoid errorsTools can try to fix errors once they have been foundCan view two ways

– For a given problem (ie. crosstalk) what can each tool do?– For a given tool (ie. synthesis), which problems can be alleviated?– Following slides have a mixture of these analyses.

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Signal Integrity Flow- Full Chip DesignFloorPlanning

Design globalwiring

BuildBlocks

-implement wiring strategy

-Route with variable width, spacing,shielding

Place &Route

ChipAssembly

-Place blocks-Place cells with Optimization

- Re-check loads, drives, timing

All Tools

Re-verify

-Signal nets correct by construction

-Push budgets into blocks

Do globalrouting

-Re-extract routing parasitics

-Re-check loads, drives, timing

Re-verifySign-off

Verification

-Re-extract routing parasitics

- Re-check loads, drives, timing

Signal Integrity Correction and Checking:– Early and Often throughout the design flow– Fewer Signal Integrity issues at the end of the design flow

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Signal Integrity Flow- Block DesignSignal Integrity issues fixed at each step in the Design Flow:

•Post-Route Crosstalk Fixing

LogicalSimulation

FloorPlanning

Placement &Optimization

ClockTree

Routing ParasiticExtraction

TimingDelayCalc

•Signal Hot Electron

•Wire/Clk Self Heat

•Crosstalk Parasitics

•Crosstalk Delay

NewLibraryData

•Power: EM & IR Drop

•Crosstalk Prevention•Signal Self Heat •Clk

Self Heat

•Clk Hot Electron

•Power Driven

•Automatic Repeater Insertion

•Power: -PGP -EM -IR Drop

•Shielded Routing

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Controlling crosstalk

Use timing windowsUse a sensitivity-based noise check to minimize false failuresNeed fast analysis with SPICE-like distributed models

– Based on reduced order modelsAutomatically fix functional noise failures via ECOs to P&RSupport mixed flat and hierarchical analysisSpecial commands for fixing post-route crosstalk

– Needed for good flow convergence

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Timing Windows for Crosstalk Only consider signals that can change at the same

time

Data comes from static timing analysis

One clock cycle

A

B

C

D STATimingWindows

CrosstalkMagnitudes

Worst case occurs here, does not include signals A or D.

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Glitch Rejection

Calculates the sensitivity of each receiver to noise at its inputAccounts for the inherent glitch rejection of each receiverDepends on input waveform, input circuitry, and output load

IN

0UT

in

out

v

v

Noise sensitivity is dependent on input waveform shape and

output loading

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DC Noise Peak Vs Noise Immunity

7%

0.25%

12%

0.01%0.14%

1.80%

0%

2%

4%

6%

8%

10%

12%

14%

CktA (0.25u) CktB (0.18u) CktC (0.15u)

% Nets withNoise >30%Vdd

% Nets withSensitivityFailures

Using Sensitivity analysis (such as CeltIC) implies less rework!

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Crosstalk Analysis – Accuracy MeasurementCan reduced order models give accurate results?Worked through this with customers – it’s very difficultTo determine error budget, need to understand each portion

separatelyNeed to get LEF, TLF, and SPICE to exactly agree

– Need to run, and measure, SPICE simulations– Slopes, normally a second order effect, are first order for crosstalk

checkingEven SPICE analysis has ambiguities:

– Simultaneous Switching (SS) vs. Worst Case Alignment (WCA)

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Simultaneous switching is not worst delay

-4.00E-01

-2.00E-01

0.00E+00

2.00E-01

4.00E-01

6.00E-01

8.00E-01

1.00E+00

1.20E+00

1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61

Time (ps)

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Crosstalk results – lumped vs distributedGlitch Noise

– Lumped analysis was about (-10%, +70%) for noise peak.– CeltIC (distributed analysis) was (-9%, +4%) for noise peak

Since most signals fail by only a few millivolts, using distributed analysis results in many fewer reported errors.

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Glitch size with lumped modelNoise Error Rising

-20.00

0.00

20.00

40.00

60.00

80.00

0 0.2 0.4 0.6 0.8 1 1.2 1.4

XMC Noise (V)

%E

rro

r

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Celtic (distributed) Noise Errors (note scale change) Error Graph

-12.00%

-10.00%

-8.00%

-6.00%

-4.00%

-2.00%

0.00%

2.00%

4.00%

6.00%

0 0.2 0.4 0.6 0.8 1 1.2 1.4

Celtic [V]

Err

or

% Rise Error Graph

Fall Error Graph

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Better prevention helps flow convergenceCrosstalk prevention in synthesis

– Upgrade drivers of slow transition signals even if not needed for timing

– Global slew limits– Clock tree generator should include EM prevention for clocks

Crosstalk prevention in routing– Long parallel line avoidance– Longer term, track assignment does even better

– Takes advantage of ‘free’ shielding by power supply gridCrosstalk timing prevention in synthesis (forward prediction)

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Fixing errors after routing

Fixing crosstalk errors after routing requires care– Rip-up-and-reroute may change neighbors– Making victims stronger makes them better aggressors

Specific post-route heuristics are required for best convergence– Insert/change components with minimal routing changes– Change some marginal components preemptively to avoid

iterationsThese commands are also useful for other post route changes

– ECOs

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Strategy for Crosstalk Fixing From Post Route Analysis

– Create repair files for Post Route Crosstalk Fixing– Apply repair file

– Buffer insertion– Wide Space Routing– Shielded Routing

BufferInsertion

ShieldedRouting

Wide Space Routing

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Timing ConvergenceExtremely few timing problems from crosstalk glitch fixing (none

in 20-30 large examples at 0.15 and 0.13 micron) If flow is timing driven, critical path has strong drivers, short nets

and good slopes -> few crosstalk problemsConversely, nets with problems tend to be long nets with weak

drivers, and buffer insertion helps these.Wire fixes (extra spacing/shielding) increase performance if

anything

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Handling Timing Impact of CrosstalkCorrect treatment of coupling has an effect even if there is no

noise!Need accurate analysis of effect

– Lumped models have large errors– Distributed analysis is needed

– Reduced order models give good resultsWould like to avoid the need to iterate around timing windows

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Even without noise, coupling is important

in victim

Logic 0

in victim

Solid 0

Real circuit on siliconWhat existing timing verifiers see.

True timing is about 15% faster

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Crosstalk results – lumped vs distributedAnalysis of crosstalk induced delay

– Lumped analysis was about (-20%, +450%) on delay– Spice has simultaneous switching; Lumped analysis used Worst

Case Alignment– The delay measurement was interconnect delay – not stage delay

– A distributed analysis with reduced order models (CeltIC) was (-16%, +10%) for delay

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Lumped crosstalk delayEarly Rise Error

-100.00

0.00

100.00

200.00

300.00

400.00

500.00

-1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0

XMC Delay (ns)

%E

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Distributed (CeltIC) Delay ErrorsDelay Error

-20.00%

-15.00%

-10.00%

-5.00%

0.00%

5.00%

10.00%

15.00%

-1 -0.5 0 0.5 1 1.5 2 2.5 3

Celtic [ns]

Err

or

%

Late Fall Error

Late Rise Error

Early Fall Error

Early Rise Error

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Noise Aware-Timing

Internal iteration

CeltIC

STA

SDFTW

Start

End

TW SDFSDF

Noise Aware Timer

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Noise Aware Timing

Static Timing Analysis

Detailed Crosstalk DelayCalculation

Avoids iteration between tools

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Signal Integrity (SI) in SynthesisSynthesis with placement can help SI issues

– Crosstalk and EM prevention in placement/sizing– Interface to detailed crosstalk analysis– Generate timing windows, constraints, and clocks– Generate maximum frequency for reliability checks

– Wire self heat and hot electron– Post routing crosstalk correction

– Add buffers– Size drivers– Decision based on routing and cell congestion

– Includes post route timing corrections– Integrated clock tree generation supports EM prevention

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Signal Integrity Avoidance in Synthesis

Other possible prevention options– Global slew limit (can limit length as a function of driver size)– Global length limits (per layer).

– Some customers have requested this for manufacturability, but it can also be used for SI.

Better correction options– Decide bigger driver, inserted buffer, or extra spacing on a net by

net basis after routing.

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Controlling Wire Self Heat (also called Signal Line Electromigration or Joule Heating)

Need a maximum frequency for each net– Timing analysis and/or synthesis can provide this– Generated by propagating clocks forward to data signals– Maximum frequency, times load, gives maximum possible current

Clock nets are a particular concern– Highest frequency operation, long wires, big loads– Worst spot on net may not be at driver

– Vias may have tighter limits– Specialized clock drivers may only have pins on the high metal

layers, leading to a good initial clock route, but….– Router may change layers during rip-up and re-route

– Nets must be tapered (to reach pins), but only at input pins

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Buffer

All wiring segments, vias, and cell I/O pins must be checked Frequency dependent Cload and/or Slew are calculated and checked. EM current density change on a wire path are measured and checked.

4M

OK

OK

No Good

Buffer

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Signal Line Electromigration

New Placement and Routing features– Router must taper correctly (No taper at driver)– Analysis must check correctly

– Tapered (input) pins are not checked– All segments on net are checked– All vias on the net are checked.– Layers and vias that are in the routing rule, but not used, are not

checked.

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Extract Improvements Needed for SI

Accuracy for cross couplingCapacityCoupling capacitance reduction

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Extraction for Cross CouplingFully distributed coupling reflects physical reality

– Files are huge (3GB for 100K instances) -> 300GB for 10M cellsNeed a reduction that reduces network size with an acceptable

degradation of accuracy.– We believe a good compromise is possible here.

When combined with delay calculation, can potentially regain ~15% timing margin associated with assuming coupling Cs are truly grounded.

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Intelligent Network Reduction

SPICE/DSPF require even more componentsNo native element for distributed RC12 Rs, 9 Cs for T model, 6 Rs, 16Cs for Pi model

Net result: huge files

6 shapes9 inter-shape couplings

A very small example

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Network Reduction (continued)

Reduce number of componentsPreserve important properties

– Preserve moments (Elmore delay and higher order)Preserve cross-coupling properties

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Hot Electron Degradation

Most customers are designing their libraries such that the CAD tools don’t need to check this.

If needed, can be fixed by a combination of timing analysis and placement, and pre-characterization of cells

– Timing analyzer computes input slope and max frequency– Placement tool computes output load, then consults pre-

characterized table– If load is too high for specified chip lifetime, upsizes driver or

inserts isolation buffer

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Power Supply Analysis

IR drop analysis– Static (uses average current)– Dynamic (worst case stimulus)

Most users use static analysis since worst case vectors are unknown.

– This is an active research problem Important to do this early in the flow since widening the power

supplies later causes huge routing problems.

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Power Calculation Flow

Power Calc

Design -LEF, DEF

Power Spec File

Power CharacterizationSupply VoltagesRSPF parasiticsVCD file or freq +activity

Vectors

Average

PWL

Triplet

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Rail Analysis Flow

Wire Seg FileCell Seg File

SEDSM

RailAnalysis

Design: LEF, DEF

• Extract Power network

• Calculate IR Drop and EM through wire segments

• Display on physical design

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Rail Analysis

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Power supply analysis improvements Improve existing features

– Multi-Vcc -> Map to cell supply voltage– Peak IR drop – try to make easier to use

Hierarchical analysis– Top down, enter estimates for uncompleted blocks– Bottom up, analyze block and it builds a model for top analysis.

– Model has a current source per pin, and a matrix of pin interconnection Rs.

– Similar to paper of Blaauw in DAC 2000.Better run times and higher capacity

– New matrix size reduction techniques can help

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Model for Cell Power Supply Network

Model is exact for a linear system –works for transient response too

1

2

3

4

Z13

Z12

Z14

Z23

Z24

Z34

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Flow analysis/testing:There are many interactions within a place and route flowMust verify (for example) that fixing one violation does not cause

others (at least on the average)Crosstalk (for example) can be fixed in many places

– Aggressive sizing in synthesis/placement– Post track assignment analysis– Post detail routing analysis

Which of these has minimum impact on chip performance and/or time to market?

Widths and spacings affected by neighboring geometriesOPC (Optical Proximity Correction) tries to fix this, but will not succeed

completely at small process sizes.Eventually will impact manufacturability and routing, and possibly placement

User draws

Without OPC

Mask w/OPC

Silicon fabbed

What you draw is not what you Image!

90nm and Beyond – Subwavelength Effects

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90nm and Beyond – Inductance Inductance is required in some cases

– Package models, PC boards, MCMs, Flip-chip packages

For on-chip wires, it is sometimes (rarely) required– “Short” wires (compared to their rise time) are equipotential

– “Long” wires have an R that dominates their L

– In both these cases L is not needed*. Most nets meet one of these rules

A physical prototype allows our analysis to determine on a net by net basis whether L is needed. If not, we don’t extract it.– For the remaining nets the extraction and timing infrastructure must support

inductance

– Result: accurate analysis without a serious time penalty

* “Figures of Merit to Characterize the Importance of On-Chip Inductance”, by Ismail, Friedman, and Neves, IEEE Transactions on VLSI Systems, December 1999

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SummaryLots of activity in the area of Signal Integrity!

– Better analysis of all kinds of effects– SI prevention features in synthesis– Improvements to extraction– Improved SI prevention in placement and routing– Improved power supply analysis

New problems coming at 90 nm and below!Will provide job security for years to come!