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Silicon Solar Cell Damage from Electrical Overstress

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Session C Radiation Effects in Devices 1525
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Page 1: Silicon Solar Cell Damage from Electrical Overstress

Session CRadiation Effects in Devices

1525

Page 2: Silicon Solar Cell Damage from Electrical Overstress

IEEE Transactions on Nuclear Science, Vol. NS-29, No. 6, December 1982

SILICON SOLAR CELL DAMAGE FROM ELECTRICAL OVERSTRESS*

R. L. Pease and J. R. BarnumMission Research Corporation

1720 Randolph Road, S. E.Albuquerque, New Mexico 87106

W. G. Vulliet, V. A. J. van Lint, and T. F. Wrobel**Mission Research Corporation

5434 Ruffin RoadSan Diego, California 92123

ABSTRACT

A model for the prediction of electrical over-stress failure in silicon solar cells based on bulkconduction has been developed. The model has been usedto predict the threshold failure current versus pulsewidth for three types of concentrator cells and onefl atpl ate cel l. Threshold failure currents have beenmeasured in each of the cell types using a high voltagepulser that was transformer coupled to the cell impe-dance. Threshold failure currents for a 10 us exponen-tial pulse of 3-15 kiloamperes were measured for theconcentrator cells, in good agreement with model pre-dictions. However, the measured reverse failure cur-rents in the flatplate cell were 4-12 amperes for pulsewidths of 10-100 ps, compared to predicted values of200-300 amperes. The failure mechanism for the flat-plate cell was related to surface or edge currents andhence would require a different model. This study wasdirected toward pulse widths of interest for the light-ning environment but may be extended to the EMP orSGEMP environments with further analysis.

INTRODUCTIONA cloud to ground lightning stroke can pose a

threat to a photovoltaic array of silicon solar cells.The EMP field surrounding the stroke can couple tran-sient currents and voltages into the DC array cablingconnecting the array to a power conditioning unit.Depending on the proximity and peak current of thestroke and the length, orientation and impedance of thecabling the peak overstress currents coupled into thesolar cells may reach thousands of amperes.' Thesetransient overstress pulses are typically double expo-nential with a rise time of about 1 us and decay timesof 10-100 us. To the best of the author's knowledge nodata on solar cell failure due to transient electricaloverstress has been reported in the open literature norhas any model been proposed to predict failure cur-rents. Static electrical overstress tests have beenmade on solar cells2 with the general result that fail-ures occurred in the range of a few amperes to tens ofamperes for stress times of seconds to minutes. Thefailures all occurred at the periphery of the cells.2

was manufactured by TRW but was obtained from Photo-watt. Silicon solar cells consist of a very shallowheavily doped diffusion into a long lifetime sub-strate. The top surface may be smooth or textured.The metallization on the top surface consists of arelatively wide bus on the chip periphery to whichnarrow fingers (extending across the cell) areattached. The total surface area of the metallizationis usually limited to less than 10% of the cell area.The metallization consists of a thin trimetal contactonto which pure silver is electroplated to a thicknessof 5-20 tm. The bus metallization may be placed eitherdirectly on the silicon surface or on top of an oxidelayer. The top surface is usually covered with anantireflective coating. Solar cells are soldered to aceramic header on which a metallic pattern has beenlaid for back and top surface contact. Solder isflowed along bus lines to reduce resistivity and pro-vide attachment for metal straps which contact the busto the header. In the case of concentrator cells theceramic header is attached to a stud mounted copperheat sink which maintains the cell at 70-100C. InFigure 1 a top surface view of the four cells isshown. The ASEC and SNL cells have the same metalliza-tion pattern but with a different nuiber of fingers perside.

5.976 cm ,- BUS

.1

3 3 3 q

If 1

a) SOLAREX CONCENTRATOR CELL

2.35 cm-- -2.05 cm

The purpose of this study was to develop ananalytical model to predict transient overstress fail- 33ure currents in silicon solar cells and to experimen-tally measure the threshold failure currents in avariety of concentrator and flatplate cells3,4Since the primary concern was for the lightning envi- b) ASEC AND SANDIAronment, the experimental verification of the model was CELLSperformed in the rahge of 10-100 us. Figure 1. Me

CHARACTERISTICS OF THE SILICON SOLAR CELLS CEFailure current predictions and experimental

measurements of threshold failure currents were made on characteristicthree types of concentrator cells and one type of flat- transient ovrepl ate cel l . The concentrator cells were manufactured each of the paby Applied Solar Energy Corporation (ASEC), Solarex and tr referSandia National Laboratories (SNL). The flatplate cell symme r

~~~~~~~~contained in

* Work sponsored by Sandia National Laboratories symmetry meansunder contract 62-8208. and that the c

** Presently with Sandia National Laboratories.1526 0018-9499/82/1200-1526$00.75© 1982 IEEE

FlIW 112 cm

UbI 2c

A CONCENTRATOR c) PHOTOWATT FLATPLATE CELL

etallization patterns for the four solarells.

I is a list of all of the solar cells that are relevant to the prediction of?stress failure along with the values ofarameters for the four solar cells. Thers to the number of identical sectionsthe metallization pattern. Thus 1/8

s that there are 8 symmetrical sections:urrent into one section is 1/8 the total

II

A

Page 3: Silicon Solar Cell Damage from Electrical Overstress

current. The nominal values, shown in the table, wereobtained primarily from the manufacturers.5-8 Geo-metrical parameters such as cell area, bus and fingerwidth and chip thickness were verified by measurement.Base resistivities were verified both by avalanchebreakdown measurements and reverse biased junction CVmeasurements. Metallization thickness and junctiondepth were verified by angle lap measurements. A totalof 48 ASEC cells, 40 Solarex cells, 16 SNL cells and 60Photowatt cells were obtained for pulsed overstresstesting.

TABLE

CHARACTISTICS OF THE SOLAR CELL

the bus is conducted directly into the silicon. Themajority of the current however, is into the fingers,then through the silicon to the back surface aftertraversing some fraction of the finger length. Thiscurrent distribution is illustrated in Figure 2. Asshown in 2b current down the fingers also spreads outlaterally from the finger through the low resistivityn+ region. The current and voltage distributions havebeen solved in terms of the current density under thebus, JO, the lateral width of the current sheet,Wp, and the decay length down the finger, x. Theincremental finger current is

ASEC SANDIA SOLAREX PHOTOWATT

n+/p p+/n n+/p n+/p

1/8 1/8 1/2 1

72/SIDE 54/SIDE 108 24

20Gm 23um 32gm 25.4pm

5pm 10Gm 20pm 5pm

1 cm 1 cm 1 cm 1.9 cm

.15 cm .15 cm .236 cm .1 cm/.0686 cm

2.35 cm/SIDE 2.35 cm/SIDE 6 cm 1.9 cm

.4Qcm .3Qcm .4Qcm 1OQcm5.4x1l16 cm3 2.65xlG16cm 3 5.4x1U¶Bcm23 1.4x1G15cm-3

23 33 21 245

12 mil 12 mil 12 mil 8 mil

.002Qcm .002Qcm .001Qcm .00lQcm.4um .35um .4,u m .3p m

TRANSIENT OVERSTRESS FAILURE MODEL DEVELOPMENT

In deriving the transient electrical overstressfailure current model, the following assumptions weremade:

a) Maximum heating occurs for reverse bias.b) The maximmi current density in the silicon,

hence heating, occurs in the bulk ratherthan at the surface or edges for transientcurrents in the range of 10-100 is pulsewidths.

c) The threshold for failure of the siliconjunction occurs when the silicon is heatedto the resistivity turnover temperature(which is a function of the base dopingdensity).

d) The threshold for metallization failure isthe silver melt temperature, 960°C.

Assumption a) is certainly valid for heating inthe silicon junction since the voltage is much greaterfor reverse bias. The second assumption is not soobvious since, in the case of static overstress, thefailures do apparently occur at the edges. However itcan be shown for the concentrator cells that reverseleakage resistances of greater than 5-10 Q and pulsewidths less than 100 us, the expected current path isthrough the bulk.4 Assumption c) allows for a worstcase model since the resistivity turnover temperatureis the threshold for instability. In typical pulsedpower failure tests on diodes and transistors, theamount of power required to cause failure in additionto the power required to reach instability is only5-10%. Therefore assumption c) should allow the modelto provide a lower bound to the failure current.Assumption d) is obvious.

Current Distribution in the Cell. Before theheating in the cell can be calculated, the cell currentdistribution under pulsed conditions must be deter-mined. The ASEC cell will be used to illustrate themodel. The bus distributes current to the fingers.Since its cross sectional area is large, due to itswidth and the thickness of the solder, the major resis-tive voltage drop occurs in the fingers with the busbeing at uniform potential with respect to the backsurface of the cell. For the ASEC cell, the bus liesdirectly on the silicon, hence some of the current in

I(x) =J Wpx(e X/ -e-i/ )o p (1)

and the differential voltage drop down the finger is

AV(x) JP WXx (l-e-'/x) - xe-Q/ ]-m- (2)

where x is measured from the bus down the finger, Wp =f s s n+)nX s

pmWp)1/2, p is the silver resistivity (assumed to be

2 pAQ-cm), p5 and pn+ are the silicon base and n+ layer

resistivities, Ss and Sn+ are the silicon base and n+

layer thicknesses, Am is the finger cross sectionalarea, is the finger length and Wf is the fingerwidth.

- FINGER

a) CURRENT FLOW UNDER BUS AND DOWN

LENGTH OF FINGER.

I , P X. I )b) CURRENT FLOW LATERALLY FROM FINGER

THROUGH LOW RESISTIVITY n+ REGION.

Figure 2. Current distribution in the silicon.

The current density JO is determined by dividing thetotal current into the cell, IT, by the total effec-tive area of the fingers plus the bus area. The effec-tive area of a finger of length Q is

AF = W x (1 - e- )F p

(3)

Heating Effects in the Silicon. Once the cur-rent distribution under pulsed high current conditionsis established, the heating due to this current can bedetermined. The current through the cell will cause

heating in the silicon from the power dissipated across

the junction, the 12R power in the bulk silicon baseand by conduction of heat from the metallization whichlies directly on the silicon. Heating in the metalfingers occurs from the I2R power which is positiondependent due to the exponential decay of current downthe finger. Maximum heating in the finger will occur

near the bus where the current density is greatest.The threshold damage current is assumed to be theminimum current which will either heat the silverfinger to its melting point of 9600C or heat thesilicon to its resistivity turnover temperature. Forthe ASEC cell the AT required for resistivity turnoveris approximately 325°C.

Junction Heating From Reverse Bias. The mostsevere heating effects in the silicon pn junction occur

for the reverse bias case. The maximum power per unitarea occurs directly under the bus where the current

1527

CHARACTISTIC

JUNCTION TYPE

SYMMETRYNO. OF FINGERS

FINGER WIDTH

FINGER THICKNESS

MAXIMUM FINGER LENGTHBUS WIDTH

BUS LENGTH

SILICON BASE RESISTIVITY

BASE DOPING

AVALANCHE VOLTAGEFROM PLANE JUNCTIONAPPROXIMATION)

CHIP THICKNESS

TOP LAYER RESISTIVITY

TOP LAYER THICKNESS

Page 4: Silicon Solar Cell Damage from Electrical Overstress

density is greatest. This power density is equal tothe current density Jo times the junction voltage.The junction voltage, Vj, is equal to the avalancheplus space charge voltage. The temperature rise in thesilicon due to this power dissipation is ATJ3V. vYI7/Cs, where T is the current pulse width, CSthe silicon heat capacity (1.78 j/cm3°C) and D thesilicon thermal diffusivity (0.6 cm2/s). For theASEC cell at 100 ps, AT = 0.045 IT°C. Thus it wouldtake 7,220 A to raise the temperature of the junctionto its turnover temperature.

Bulk Heating of the Silicon. The heating of thesilicon base region under the bus (maximum currentdensity) due to the silicon base resistance is ATJ02PS Cs. For the ASEC at T = 100 lPs, AT = 1.60x 10- IT C. A current of 14,200 A is required toraise the silicon temperature 325°C.

Heating of Finger Metallization and SubsequentHeating of Silicon by Conduction. The most importantsource of heating in the silicon is due to conductiqnfrom the metal finger. Consequently a solution of thethermal diffusion differential equation is necessary todetermine the temperature profile in the silicon. Forthermal diffusion lengths, /'+, equal to or less thanthe finger width the solution to the thermal diffusionequation using the plane wave approximation is

AT " PT (4)

Cs Wf /

where P is the power per unit length in the finger andWf the finger width. For /_f large compared to thefinger width, the thermal wave becomes cylindrical andit is necessary to integrate the thermal conduction incylindrical geometry to obtain the heated volume. Forthis case

AT pv Qn ( 1 Wf) (5)

To find the value of P it is necessary to know the cur-rent density in the metal finger, Jm * Jm decreasesalong the length of the finger and is a maximum nearthe bus. The maximum value of Jm, which will be usedin subsequent calculations, is related to the maximumsilicon current density, Jo, by the ratio of theeffective finger area for current flow and the actualcross sectional area of the finger. The power per unitlength is P = Jm2pmAm. The silver resistivityvaries with temperature according to the relation Pm= po(1+aAT) where AT is the increase in temperatureabove room temperture, a is the temperature coefficientof resistivity for silver, .0038/1C and po is theroom temperature silver resistivity. Since the powerdissipated in the silver is proportional to Pm then P= PO(l+aAT) where PO is the power for constantresistivity. Using these relationships, along withequations (4) and (5), AT can be determined in terms ofa and PO. The variable resistivity solution from theplane wave approximation of equation (4) is

Equations (6) and (7) are not easily solved for IT.However the failure current can be determined by plot-ting AT versus IT and finding the value of IT forwhich AT = resistivity turnover temperature.

Metallization Burnout. The maximum heating inthe silver metallization occurs in the fingers near thebus. This temperature increase is given in equations(6) and (7) for the short and long pulse approxima-tions. The threshold failure currents for metalliza-tion burnout are determined by plotting AT versus ITand finding the value of IT for which AT is 935°C(melting point - room temperature).

Prediction of Threshold Failure Currents. Thesolar cell parameters necessary to calculate the cur-rent distribution in the cell and the threshold failurecurrents were given in Table I. The predictions offailure current are based on these nominal values anddo not represent either the spread in the parametersfrom cell to cell within a cell type nor do they repre-sent a worst case for a given cell type. The predict-ions do, however, represent a lower bound to the nomi-nal cell failure inasmuch as the prediction is based onheating only to the instability temperature and not thefailure temperature. Using the nominal values given inTable I, the relaxation length, width of the currentsheet and effective areas were calculated for each ofthe cell types. Using these calculated parameters, theincrease in finger temperature, AT, was determined foreach of the cell types as a function of total cell cur-rent. Figure 3 is a plot of AT versus IT for theASEC cell. Similar plots were made for the other celltypes. Equation (6) was used for 100 ns and 1 ps andequation (7) was used for 100 ps and 1 ms. These equa-tions should be valid for the concentrator cells sincethe maximum temperature increase in the silicon isprincipally due to conductive heating from the fin-gers. However in the case of the Photowatt cell, theheating from reverse bias is appreciable since theavalanche voltage is about 245 V. The heating of thesilicon under the bus, where the current density is amaximum, is AT = 93.61T/:T. The failure currents cal-culated from the reverse bias heating are thus lowerthan those predicted from equation (7) for T > 100 pS.However for the shorter pulse widths, equation (6)gives lower threshold currents.

10,000

1,000

0

100

/ND;T << 21f AT = a [e fs /-1(6)In a similar manner equation (5) can be used to derivethe variable resistivity solution for the cylindricalapproximation. The result is

/ »>> 1 Wf

aP02T<D5fC-

ATa= (42 -1] (7)

0 2 4 6 8 10 12 14

IT (KA)

Figure 3. AT versus total cell current at differentpul se widths for ASEC cell .

1528

- ~~CYLINDRICAL PAA

im M vs 100 ns

~~7 7 7 ~MELT -

~~/ / / / S~~~ILICON/// / ~TURNOVER

Page 5: Silicon Solar Cell Damage from Electrical Overstress

Figure 4 is a plot of the threshold failure cur-rents for each of the four cell types versus the pulsewidth. These failure currents were determined from theAT versus IT plots except for the long pulse resulton the Photowatt cell. Since neither of the approxima-tions are valid in the range of 10 ps the failure cur-rents at this pulse width are found by merely connect-ing the predicted results at 1 and 100 us.

100,000 TI II

- SOLAREXF- 10,000 _ -zWi ASEC

SANDIA_-

z 1,000

0ICf 100

10, ,, II,,,1 , ,11 III 1 11111 I, ,lo ns 1as 10ps 100ps 1 ms

PULSE WIDTH

Figure 4. Threshold failure current versus pulsewidth for solar cells.

Part of the reason the failure currents in theSolarex cell are high is due to the much greater crosssectional finger area, Am. Al so the reason for thelow failure currents in the Photowatt cell is the smallvalue of Am and the high base resistivity, hence highavalanche breakdown voltage. The Sandia and ASEC cellsare the same area. However the Sandia has a lowerfailure current due to the fact that the bus sits on anoxide layer thus forcing all of the current down thefingers. This difference offsets the larger value ofAm in the Sandia cell compared to the ASEC cell.

The metallization burnout threshold failure cur-rents can be determined from the AT versus IT plotsas shown in Figure 3. For the concentrator cells, allof which have a resistivity turnover AT of 325C, thefailure currents are about 37% higher than the siliconjunction failure currents. For the Photowatt cell,with AT = 175°C, the metallization burnout current isabout 73% higher at the short pulse widths. At thelonger pulse widths, T > 100 vs, the failure current isgoverned by the reverse bias heating. In this case thedifference between the silicon junction failure currentand the metallization failure current is even greater.

EXPERIMENTAL MEASUREMENTS OF PULSED CURRENTDISTRIBUTIONS

One of the critical variables in the model isthe effective area of current flow into the silicon.This effective area depends both on the lateral spreadin current from the fingers as well as the decay ofcurrent down the length of the finger. If the deriva-tion of effective area is valid then one should observethe decay in voltage down the length of a finger asgiven by equation (2). In order to verify equation (2)and to investigate the validity of the assumption thatthe bus is at an equipotential, a series of pulsed highcurrent measurements were made on the concentratorcells. The experimental technique consisted of pulsingthe solar cell at currents up to 600 A for pulse widthsup to 100 ps and measuring the differential voltage

along the bus and from the bus down the length of thefingers. The pulser used for the tests was built byMRC and consisted of a capacitive discharge system withHEXFET switches for wave shaping. Differential voltagemeasurements were made with microprobe contacts to thebus and fingers and a differential comparator with highcommon mode rejection ratio. The cell current was mon-itored with a 0.1 Q current viewing resistor. Themicroprobe and cabling configuration was designed tominimize B coupling, hence noise. Good agreement wasobtained between the predicted and measured voltagedistributions for the ASEC and Solarex cells. Theresults on the Sandia cells were erratic. This wasattributed to poor adhesion of the metallization whichhad been observed by Sandia. The two lots of Sandiacell used for the overstress tests had not met theSandia performance criteria but were all functionalcells. Measurement were made of the voltage decay downthe bus, the voltage decay down the fingers near thebus as a function of finger length, and the voltagedecay down the entire length of the longest finger.The voltage measurements on the bus confirmed the cal-culations and the assumption that the bus was at a rea-sonably uniform potential. Measurements of the slopeof the voltage decay versus finger length confirmed theprediction that the longest fingers have the greatestcurrent.

The correlation between the experimental mea-surements and the predictions from equation (2) areshown in Figure 5 for AV(x) down the longest finger ona 1/8 symetrical portion of an ASEC cell. By using asymmetrical section (which was sectioned from a wholecell by laser scribing) of the cell, the total fingercurrent is increased by a factor of 8. Thus a 200 Apulse on the section would correspond to a 1600 A pulsein a whole cell. Data is shown for both forward andreverse biased pulsing. The model was developed forthe reverse biased case. The predicted curve, fromequation (2) shows excellent agreement with themeasured results. While this data is not a directverification of the predicted effective area, it cer-tainly increases confidence in the model for currentdistribution. What the data also indicate, is that thecurrent distribution under forward bias is signifi-cantly different than for reverse bias. Since the formof the AV(x) data under forward bias is similar to thatfor reverse bias, the smaller values of AV(x) may bedue to a reduced current into the finger. This impliesthat more current is directly into the silicon underthe bus for forward bias than for reverse bias. There-fore we would expect the failure currents for forwardbias to be higher. This situation would not apply tothe Sandia cell since the bus lies on top of an oxidelayer and hence all the current is forced into thefingers.

oI-

- -3,500Ez -3,000 _

c -2,500C,Z -2,000U.z - 1,5000a -1,000 _

0a -5000

0OFi gu 0I--I0

Figure 5 .

- - CALCULATED RESPONSE FROM EQUATION (2)* ASEC #19B REVERSE BIAS* ASEC #19C REVERSE BIAS

* ASEC #19B FORWARD BIASA ASEC #19C FORWARD BIAS

.25 cm .50cmDISTANCE DOWN FINGER

1/8 section ASEC cell differential fingervoltage versus aistance down the Tinger fora 200 amp, 100 us square pulse.

1529

Page 6: Silicon Solar Cell Damage from Electrical Overstress

OVERSTRESS FAILURE TESTING

The experimental technique used to determine thethreshold failure currents in the solar cells was thestep stress method. The initial current level waschosen well below the expected failure level and thecurrent was increased on each successive pulse untilfailure was observed. Overstress testing on solarcells is a significant departure from testing othersemiconductor components such as transistors, diodesand ICs. The predicted failure currents were severalthousand amperes. No readily available pulsers, com-plete with instrumention, could be found which coulddeliver several thousand amperes into a low impedanceload for pulse widths in the range of 10-100 jis. Thesolution that was finally chosen was to build a trans-former to be used with a high voltage, 50 Q pulser.The output impedance of the transformer was designedfor 0.1 Q. The transformer was built by the Air ForceWeapons Laboratory for use with a Maxwell Labs 150 KV,50 Q custom built pulser. When complete, the transfor-mer was approximately 8 cubic feet in volume andweighed over one ton.

Coupled with the transformer, the pulser deli-vered a double exponential pulse with a 1 ls rise timeand a maximum 10 Ps decay time. The peak current intoa short circuit was about 30,000 A. This pulser wasused for all of the failure tests, both reverse andforward biased, on the four cell types. However addi-tional tests were performed on the flatplate cell underreverse bias using a square wave pulser. The output ofthe transformer was designed to provide instrumentationand function as a test fixture. The test cells weremounted to the two terminals of the transformer. Aportion of the ground terminal was milled down to forma current viewing resistor. Calibration was performedwith a precision 0.1 Q load resistor. The cell voltagewas monitored with a 100x voltage probe. With thecalibration factor and maximum oscilloscope sensiti-vity, the maximum current resolution was 225 A/div.Both the current and voltage waveforms were recordedfor each overstress pulse.

The threshold failure criteria established forthe overstress testing was one of the following, which-ever occurred first: 1) a distinct break in the cur-rent and voltage waveforms with a rapid increase incurrent and a decrease in voltage (breakpoint cri-teria), 2) an increase in the reverse current currentof greater than 10%, 3) a catastropic failure after theoverstress pul se. This would be a short circuit asobserved from the diode I-V characteristic or metalli-zation damage observed visually. Each solar cell wasinspected under magnification and I-V characteristicswere recorded on a curve tracer before and after eachoverstress pulse. The minimum failure current for oneof the above failure criteria was recorded for eachcell tested. In most cases, however, the testing con-tinued until metallization damage was observed. Cellswere tested both for reverse and forward bias over-

stress failure.

RESULTS OF FAILURE TESTS

Concentrator cells. A summary of the testresults on the three concentrator cells is given inTable II. For the reverse biased data the results are

compared with the predicted values. The predictedvalue is taken from Figure 4 at 4 ps. A 4 ps squarewave corresponds to a 10 ps exponential using anaverage power waveform conversion criterion. As statedpreviously, the model should predict a lower bound tothe failure current. Comparison of the minimum IT tothe prediction indicates that for each of the celltypes, one or more cells failed at currents below the

1530

TABLE II

SUMMARY OF FAILURE TESTS ON CONCENTRATOR CELLS

(ALL CURRENT VALUES ARE IN AMPERES)

ASEC SANDIA SOLAREX

REVSRSE BIAS

AVERAGE FAILURE CURRENT

STD. DEV.

SAMPLE SIZE

MINIMUM IF

MAXIMUM IF

PREDICTED IF

FORWARD BIAS

AVERAGE FAILURE CURRENT

STD. DEV.

SAMPLE SIZEMINIMUM IF

MAXUMUM IF

6636

1367

28

3164

9300

4700

12871

2807

8

836216300

3146

766

13

2305

4926

3400

4896

16433

3751

6780

18819

5678

25

5880

31200

15000

224062886

7

1940025990

prediction. Because of this, a much closer look at thedata was taken. Each set of data (cell type and biascondition) was plotted in histogram form to determinehow many cells failed below the predicted level andwhat was the nature of the failure was noted. In Fig-ure 6 a histogram for the reverse biased ASEC cells isshown. In each block of the histogram the cell number,failure current and the failure code is listed.

9

8

0U

0

z

_3Uui

IL

0:

z

6

4

3

2 -

1 -

0-L0

ASEC REVERSE BIASFIRST FAIL OBSERVATION

PREDICTED FAILURETHRESHOLD 4700 A

28I/V

587630 6

I/V I/V4972 5876

7 4I/V FM

4881 55148 1 20

I/V I/V I/V3164 4158 5243

1 2 3 4 5

791* 1 6HB I/VIFM6780 7910*17 2.

HB,SC I/V67B0 791019 1

I/V I/V6554 7684* 18 * 13FM FM,I/'6554 76350 * 1!

FM HB,SCi6554 7458S 26 * 2.

I/V FM,I/'S6328 7458

10 2I/V I/V

96102 745129 2

I/V FM396102 7232

6 7

FAILURE CODE6 I/V CHANGE IN I/V CHARACTERISTIC

HB - METALUZATION DAMAGE ON BUS

2 FM - METALLIZATION DAMAGE TO FINGER

SC - SHORT CIRCUIT I/V

1 EXAMPLE OF BLOCK

3 * 13 CELL ID NUMBERV I/V

v4000 CURRENT THROUGHCELL (PEAK AMPS)

FAILURE CODE* INDICATES STOPPED

V TESTING AT FIRST FAIL

2 32

I/V8 8249!4 14 5

I/V I/V2 8136 93008 9 10

CURRENT THROUGH CELL IkA)

Figure 6. Histogram of reversed bias ASEC failurecurrents.

There were two cells having failure currentsbelow the predicted value. Each of these cells failedbecause of an increase in leakage current. Prior tooverstress testing, the reverse currents are in therange of 10s to 100s of mA and are due to surface leak-age. As discussed in the modeling section, the pre-dicted current for metallization damage is only about40% greater than the current predicted for junctiondamage. Thus if the junction underwent filimentationunder a finger the current density in the finger wouldrapidly increase and a finger melt would be observed.Thus we would expect to observe metallization damage attotal cell currents very close to those required forbulk junction damage. Since no metallization damagewas observed on the cells with the low failure cur-

rents, it is reasonable to assume that the increase inreverse current is due to surface damage. The over-

stress data on units 1 and 8 were inspected further.The lowest current for which metallization damage was

observed was 7000 A for unit 1 and 4250 A for unit 8.Thus unit 8 did fail by a confirmed bulk relatedmechanism at a current below the predicted level. Asimilar analysis of the data on the other concentrator

2

_

Page 7: Silicon Solar Cell Damage from Electrical Overstress

cells revealed that two Sandia cells and one Solarexcell failed at currents below the predicted levels dueto a bulk related phenomena. The lowest bulk relatedfailure current was 80% of the predicted value.

For the forward biased tests there were nofailure currents below those predicted by the model.Thus the model is conservative in predicting a lowerbound for the forward biased failures. The higherfailure currents for forward bias are consistent withthe results on the current distribution tests. Furtherverification of the model prediction for reverse biasedfailure is shown in Figure 7. This is a schematicrepresentation of the distribution of metallizationfailures for the ASEC cells under reverse bias. Thedistribution is heavily weighted toward the longerfingers as predicted by the model.

. FINGER HEATING* FINGER MELT* FINGER MELT AND OPEN CIRCUIT* FINGER MELT, OPEN CIRCUIT, AND HOLE INTO THE JUNCTIONo HOLE THROUGH THE BUS INTO THE JUNCTION

Figure 7. Location of visual damage on ASEC cellsafter reverse bias overstress tests.

Flatplate cell. The initial reverse biasedoverstress tests on the Photowatt flatplate cell wereperformed on the Maxwell pulser. Unlike the concen-trator cells, a distinct breakpoint was observed in thecurrent and voltage waveforms. However the failurecurrents could not be accurately determined becausethey were below the resolution of the instrumentationsystem. Because the failure currents were so low, infact well below the failure current predicted by themodel, the remaining tests were performed with a squarewave pulser having a peak current capability of severalhundred amperes and variable pulse width. Tests wereperformed for 1.5, 10, 50 and 100 ps pulse widths. Theresults of failure current versus time to fail (break-point criteria) are given in Figure 8. At failuretimes below 2 lus there is a large scatter in the data.However for fail times between 5 and 100 pis, the rangeof interest for the lightning environment, the data istightly distributed between 4 and 12 A failure cur-rent. The projected failure currents from the bulkconduction model are 200-300 A, hence the failure mech-anism is clearly different in these cells. There aretwo sources of information which demonstrate that thefailure in these high resistivity flatplate cells issurface or edge related, rather than bulk related.

1,000

r

-J-J

lL

0

0

I.-

zw

:3:>

i1

0.

PHOTOWATTSQUARE PULSE TESTREVERSE BIAS

1 1.0 10TIME TO FAIL IN (us)

100

Figure 8. Failure current versus time to fail forreverse bias tests on Photowatt cells.

First the voltage across the cells at failure is wellbelow the avalanche voltage of 245 V. Second, thevisual damage sites all occurred on the periphery ofthe cells. These damage sites consisted of fingermelts at the end of the finger near the edge, holes inthe silicon on the outer edge of the bus, and tracks inthe silicon from an outermost finger to the edge of thecell. It is clear from the reverse biased data thatthe overstress failures are surface related and hencerequire a different model to predict the lower boundfailure levels.

Although additional high resistivity flatplatecell types were not included in this study, limitedtests on additional types were conducted to verify thatthe results were not totally anomalous. Reverse biasedtests on three other flatplate cells, ranging in sizefrom 2 1/4" to 4" diameter, resulted in failure cur-rents in the range of 15-20 A for 100 uis pulses. Thusthe low failure current observed for the Photowattcells is not an anomaly.

The results of threshold failure current for theforward biased tests on the Photowatt cells, were inthe range of 325 to 1220 A for the 10 ps exponentialpulse and were all bulk rel ated. The predicted thresh-old for the Photowatt cells was 340 A. Thus the modelpredictions work well in predicting a lower failurebound for- forward biased overstress in flatplate cells.

SUMMARY AND CONCLUSIONS

A model was developed to predict a lower boundto the threshold transient failure current for siliconsol ar cel l s. The model was developed for reversebiased overstress assuming bulk current conduction.This model was applied to three types of concentratorcells and one tyupe of flatplate cell. Based on themodel, the predicted failure mechanism is junctionburnout on the longest fingers near the intersection ofthe fingers and the bus. The mechanism is conductionof heat from the finger into the silicon junction,heating the silicon to the resistivity turnover temper-ature. Once the junction filiments the current densityin the finger rapidly increases and the silver melttemperature is reached resulting in metallization burn-out.

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* 1.5ps PULSE -* lOps PULSE

* * 50ps PULSE

_* 00is PULSE -

* A

I, l I ,,,,111 I,,1

Page 8: Silicon Solar Cell Damage from Electrical Overstress

The results of the reverse bias tests on theconcentrator cells verified that the model works wellin predicting a lower bound to the threshold failurecurrent for failures resulting from bulk current con-duction. Out of 66 concentrator cells tested underreverse bias only four cells had confirmed bulk relatedfailures below the predicted threshold. The lowestbulk related failure occrjrred at 909' "f the pnnd ict-?dvalue. However in several instances for all three celltypes, failures that are apparently due to surface oredge effects occurred below the predicted threshold.All of these "failures" were increases in leakage cur-rent. The effect of leakage degradation on cell per-formance was not evaluated, but it is not expected tohave a major impact. Thus the failure model seems towork very well in predicting both the nature of thefailures and a lower bound for the true threshold fail-ure current.

The results of the reverse bias transient over-stress tests on the flatplate cell demonstrated thatthe predominate failure mode was due to edge currents,hence the model did not adequately predict a lowerbound to the failure threshold. Failure currents forpulse widths greater than about 5 ps ranged from 4-12 Awhich is one to two orders of magnitude below the modelpredictions. Therefore the assumption of bulk currentconduction does not apply to transient currents in highresistivity flatplate cells and a different model basedon edge currents is required. It appears that highresistivity flatplate cells are quite vulnerable totransient overstress damage and could present a majorproblem for photovoltaic arrays in the lightning envi-ronment. Although not investigated extensively atpulse widths below 10 ps, the failure current was meas-ured in the flatplate cell for fail times as low as 100ns. Failure currents as low as 10-30 A were observedin the pulse width range of 100 ns to 1 pds. Thus evenfor pulse widths in the range of interest for EMP orSGEMP the failure currents are quite low. Additionalwork is required to better define flatplate cell fail-ure currents in the range of interest for both the EMP/SGEMP and lightning environments.

REFERENCES

1. Fowles, H., L. Scott and J. Hamm, TransientEffects from Lightning, SAND79-7051, Volumes 1 and2, Sandia National La oratories, January 1980.

2. Rauschenback, H. S. and E. E. Maiden, "BreakdownPhenomona in Reversed Biased Silicon Solar Cells,"Proceedings of the 1972 Photovoltaics SpecialistsConference.

3. Pease, R. L., et. al., "Electrical OverstressDamage in Silicon Solar Cells", EOS/ESD Symposiumproceedings, 1981, page 229.

4. Pease, R. L., et. al., Electrical Overstress Fail-ure in Silicon Solar Cells, Final Report, MissionResearch Corp., AMRC-R-358, April 1982.

5. Khemthog, S., F. F. Ho and P. A. Iles, "HighEfficiency Silicon Concentrator Cells,"Proceedings fo the 14th IEEE PhotovoltaicSpecialists Conference, 1980.

6. Wrigley, C., G. Storti and J. Wohlgemuth, SiliconConcentrator Solar Cell Manufacturing DevelopmentSAND79-7021, Sandia National Laboratories, June1979.

7. Rodriquez, J. L. and F. W. Sexton, Design, Fabri-cation and Performance of a 20 Percent EfficientSilicon Solar Cell, SAND80-2225, Sandia NationalLaboratories, October 1980.

8. PrDi Vate conversations with TRW.

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