Silicon Technologies for mmWave...

Silicon Technologies for mmWave Applications

Ned Cahoon#1, Alvin Joseph#2 , Chaojiang Li#2, Anirban Bandyopadhyay#3, BaljitChandhoke#3, Tianbing Chen#3, Abdellatif Bellaouar#4, Arul Balasubramaniyan#4, Sher Fang#4,

Kyoungwoon Kim#4, See Taur Lee#4, Mehmet Ipek#4, Chi Zhang#4, Frank Zhang#4

#1RF Business Unit, GLOBALFOUNDRIES, VT USA

#2GLOBALFOUNDRIES, Essex Junction, VT USA

#3GLOBALFOUNDRIES, Santa Clara, CA, USA

#4GLOBALFOUNDRIES, Dallas, TX, USS

#1 [email protected]

WS-01 Recent advances in SiGe BiCMOS: technologies, modelling & circuits for 5G, radar & imaging

- 2 -WS/SC/Session ID# - WS/SC/Session Title

Abstract:

Silicon Technologies for mmWave ApplicationsThe mmWave era is upon us and opens up many opportunities for differentiated silicon Integrated Circuit technologies including SiGe BiCMOS, Partially-Depleted (PD) SOI and Fully-Depleted (FD) SOI. In addition to the requisite high transistor ft/fmax needed for operation at mmWave frequencies, each of these technologies has unique attributes and strengths that have been optimized for specific application requirements and can be leveraged to provide a solution advantage. In this talk, we will discuss the application requirements and technology trade-offs for several mmWave applications of interest

1. Technology and device requirements for mmWave applications

2. PD-SOI overview; 28GHz circuit examples

3. FD-SOI overview; 28GHz and 77GHz circuit examples

4. SiGe BiCMOS overview; 28GHz circuit examples

5. Summary

- 3 -WS-01 - Recent advances in SiGe BiCMOS: technologies, modelling and circuits for 5G, radar and imaging

Phased Arrays are a key enabler for mmWave Radios

LEO satellites for broadband

communications

5G handset, small cell, Fixed wireless

Auto radar

802.11ad

• Highly focused antenna beam at mmWave• Lower Tx power per Power Amplifier and Antenna element

mmWave FEM requirements can be addressed by Silicon technologies

EIRP is proportional to the square of the number of radiating elements


Essential elements for a mmWave Silicon technology

–fT / fMAX should be at a minimum 3x and preferably > 5x application frequency

• High-performance technology

–Thick top metal(s) with increased distance from substrate– Substrate resistivity

• Low loss Back-end-of-line (metal and dielectric stack)

–mmWave model-to-hardware correlation– Good PEX & Electromagnetic simulation capability

• Well-modeled technology

• Reliability & Ruggedness

–Both at device and component/circuit block level at mmWave


Differentiated Silicon technologies for mmWave

Technology Key Features Device Cross-Section

PD-SOI (45nm)

PD-SOI = Partially Depleted Silicon-on-Insulator• High-speed w/ lower junction capacitance, isolation & stacking• FET stacking for higher voltage and power handling than CMOS• High Resistivity substrate for lower T/L losses, higher Q matching

networks and higher linearity switches• Early adoption in 5G & Satellite Communications for 45nm

PDSOI with high Ft/Fmax & optimum BEOL stack

FD-SOI (22nm)

FD-SOI = Fully Depleted Silicon-on-Insulator• Delivers FinFET-like performance and power-efficiency at 28nm

cost• Transistor body-biasing for flexible trade-off between

performance and power• High density low power logic for SOC integration• Enables applications across mobile, IoT and mmWave markets

SiGe (130nm - 90nm)

SiGe = Silicon Germanium• Based on higher performance & power tolerant HBT ( vs FET)• Technology optimized for micro and mmWave applications:

backhaul, E-band links, Sat Comm, automotive radar, A&D• Roadmap to ft/fmax >500GHz for next generation 6G and sub-

THz applications

GS D

• SiGe and SOI technologies have unique attributes to optimize mmWave radio performance and integration


• Chip partitioning / integration will depend upon application requirements and technology capability

Generic architecture for mmWave 5G Radio interface for UE

TransceiverFEM subsystemAntenna

SubsystemBaseband and

Application Processing

Digital Beamforming example

App Processor

Modem / Digital Phase

splitter / power

combiner

RF & IF up/down

conversion

LNA

PA

SPDT

LNA

PA

SPDTRF & IF

up/down conversion

ADC/DAC

ADC/DAC

PA: High Psat, efficiency

LNA: Low NF, high Gain

Switch: low IL, high Isolation & linearity

Mixer: High conversion gain, linearity

PLL: low phase noise

ADC/DAC: low power, high sampling rate

Low dynamic & leakage power, high speed and area scaling

Requirements


Key Technology Metrics for mmWave Radio

Metrics Impact Technology Requirements

Ft * Gm / ILNA , PA performance at low current

High Gm, low Gds, Cgs & Cdg

FmaxHigh peak Fmax high Pout of PA

High Gm, Low Rg, Cdg & BEOL parasitics

Back end parasitics

Low interconnect & matching network loss (PA efficiency), low LNA NF

Optimized BEOL stack, substrate resistivity/ metal shield

Breakdownvoltage

For switch & PA voltage tolerance

Higher Vbr or FET stacking & ability to isolate transistor

Flicker noise Low VCO phase noise low parasitics

In addition to above metrics, technologies with low power logic and analog are best suited for RF SoC


Key Device Parameters

• PA:• Breakdown voltage• Ft/Fmax

• LNA:• Ft/Fmax• Noise figure

• Switch:• Breakdown voltage• Ron and Coff

nmm

in

Rgg

CR

Rs

rg

2

11

3

81

2

CMOS NFmin

BJT NFmin

𝑃𝑚𝑎𝑥 ∝1

8𝐼𝑚𝑎𝑥 𝑉𝐵𝑅 − 𝑉𝑘𝑛𝑒𝑒

𝐹𝑚𝑖𝑛,𝑆𝑖𝐺𝑒 = 1 +1

𝛽+ 2𝑔𝑚𝑟𝐵 + 1

1

𝛽+

𝑓

𝑓𝑇

2


RF Silicon-On-Insulator Technologies

• Ideal technology for low-power mmWave

SOC

• Improved electrostatics with fully depleted

channel

• Software-controlled body-bias, post-silicon

trimming

• Integrated power mgmt (3.3 & 6.5v LDMOS)

in bulk region

• Excellent mmWave performance to integrate

FEM & Transceiver with AFE and Logic

Oxide Insulator

Silicon

Silicon Wafer

Ultra-thin Buried Oxide Insulator for back gate control

Fully DepletedChannel for superior FET electrostatics compared to bulk

Back Gate Bias to maximize performance / leakage

Thick Buried Oxide for substrate isolation

Partially DepletedChannel for Low Capacitance compared to bulk

High Resistivity Substrate for low coupling loss

FDSOIPDSOI

• Ideal technology for RF FEM and

beamformer (PA, Switch, LNA, phase

shifters, up/down conversion)

• Low-loss substrate allows significant

switch harmonic distortion benefits and

improved BEOL losses

• Enables FET stacking for switches and

power amplifiers.


Transistor Stacking Advantages in SOI

RF signal

Load

T1 T2 T3 T4

Vd = 4V 3V 2V 1V

In bulk CMOS, T1 would have 4V across drain-to-body junction.

In SOI, body floats to limit the junction voltage.

PA ExampleCourtesy of Professor Peter Asbeck, UCSD

• SOI FET is electrically isolated from the substrate (floating) vs. CMOS where the substrate is a common node

• Stacking overcomes low breakdown voltage of advanced node CMOS

• Power supply can be N x BVds, where N is # of stacked FETs and BVds = breakdown of a single FET

• Circuits can operate at higher voltage and power handling

• Provides significant benefit to front end circuits (PA, LNA, switch)


45nm SOI Technology Overview (Partially-Depleted)

• Ideal technology for mmWave Beamforming FEM

(Switch + LNA + PA + Phase Shifter)

• 45nm partially depleted SOI CMOS technology

• High performance 40nm NFET and PFET

• Reduced junction capacitance of SOI improves FET

performance

• NFET and PFET strain engineering enhances FET

mobility

• NFET: fT 290GHz, fMAX 330GHz (1um W) / 410GHz

(0.5um W)

• PFET: fT 245GHz, fMAX 300GHz

• FET stacking for switches and power amplifiers

• High Resistivity substrate (> 1K Ohm-cm) reduces T/L

losses, improves matching network Q and reduces switch

harmonics

• RF optimized BEOL options with raised ultra thick Cu and Al

Substrate

Buried Oxide

Silicon

BEOL IL improvement with high resistivity substrate

> 0.7 dB reduction in insertion loss

Increased ‘d’ to substrate reduces parasitics / coupling

Al

Cu

Cu

Cu

d


• 28GHz LNA / PA / Switch silicon results

45RFSOI 28GHz Benchmark Circuits Results

PA PAE at Psat Psat Gain

GF Single ended PA 41.5% 16.2 dBm 13 dB

Differential Doherty PA* 42% 22.5 dBm 21 dB

LNA Gain IIP3 NF

GF Reference 45RFSOI designs 13 dB 5 dBm 1.4 dB

SwitchInsertion

LossIsolation OIP3

GF Reference 45RFSOI designs (RonCoff = 90 fs, 1 V)

0.65 dB 26 dB 46 dBm

* Professor Hua Wang, Georgia Tech


• 3-stack single-ended cascode PA architecture

45RFSOI PA results: Psat=16dBm & PAEmax= 41.5%

160Msym/s (960Mb/s) 64-QAM modulation at 24GHz

1.5Gsym/s (9Gb/s) 64-QAM modulation at 24GHz

Source: C Li, etc, “A High-Efficiency 5G K/Ka-Band Stacked Power Amplifier in 45nm CMOS SOI Process Supporting 9Gb/s 64-QAM

Modulation with 22.4% Average PAE”, IEEE TXWMCS, 2017.

Silicon verified results


• Leverages superior performance of 45RFSOI PFET (Fmax 300GHz)

• Higher Vmax for PFET vs NFET

UCSD 45RFSOI 28GHz PFET PA

Courtesy of Professor Peter Asbeck, UCSD


45RFSOI Ka band LNA silicon data

• NF Contributors

• FET cascode core

• Gate matching inductor

• Silicon data:

• High power mode• PDC 15 mW• Gain 12.8 dB• NF 1.4 dB• IIP3 5 dBm

• Low power mode• PDC 7 mW• Gain 12 dB• NF 1.5 dB• IIP3 1.7 dBm


45RFSOI Ka Band SPDT with 0.65dB Insertion Loss

• RonCoff ~90 fS

• Triple-stack series-shunt design

• Insertion loss: ~0.65 dB IL 30 GHz

• PFET switch design has slightly lower IL than NFET

• Nonlinearity: • P1dB is 30 dBm (25 dBm 0.1 dBm compression)

• OIP3: 46 dBm (two-tone with 100 MHz space)

• Pmax 20dBm• Thin gate floating body FET

• +3dBm with thick gate Body Contact FET design


22nm Fully-Depleted SOI Overview

Low complexity 22nm planar process

• 30% fewer masks than FINFET

• High density (5.5M gates/mm2) high

performance, ultra low power logic (for

digital filtering and high speed SERDES)

Improved electrostatics with FD-SOI

• Improved Short channel effect

• Higher gm, lower gds

• Superior mismatch

• Low parasitics

Back gate for performance tuning over power, temp, and process (for digital and RF/mmWave)

22FDX® enables integration of mmWave FEM and Transceiver including ADC/DAC and SERDES

Excellent mmWave Performance

• High Ft/Fmax (350/430GHz) and Peak

Gm*Ft/Ids

• Low NFmin (0.5dB at 30GHz, 1.3dB at 70GHz)

• Low 1/f noise : 200fV2mm2/Hz @ 100Hz

• Stacked SOI FETs for high Pout/PAE PA, switch

• High breakdown voltage and very high HCI

voltage limit at low-Vgs

• mmWave BEOL stack with dual UTM


28GHz 16dBm PA with 40% PAE in 22FDX®

28-40GHz 5G TRX with Integrated FEM

Measured Results

Freq (GHz) 28 28

Stack height 2 3

IDDQ (mA) 16 16

Gain (dB) 12.4 12.8

P1dB (dBm) 17.4 15.8

Psat (dBm) 18.2 16.4

PAE max (%) 30 41

PAE 6dB BO (%) 18 21

High efficiency PA enables 22FDX to be an ideal candidate for 5G mmWave integrated FEM + Transceiver

• 2- and 3-stack 28GHz differential PA with transformer matching at input/output

• 40% peak PAE; >20% at 6 dBm backoff (where PA operates)

2-Stack PA Schematic

2-Stack PA


28GHz LNA with 1.45dB NF in 22FDX®

Layout view of 28GHz LNA

LNA1 LNA2

Freq (GHz) 19-34 23-40

Gain (dB) 12 12.6

BW3dB(GHz)

15.1 16.7

NF (dB) 1.46 1.35

IIP3 (dBm) 3 1.4

IP1dB(dBm)

-7.6 -7.9

Pdc (mW) 9.8 13

22FDX Cascode LNA has exceptional NF with low power operation:• Low Noise Figure < 1.5dB• Wide Bandwidth• Good Linearity• Low power (5mW with < 2dB NF)


28GHz Antenna Switch with 0.65dB IL in 22FDX®

Die Photo of 3-stacked SPST switch

[4] M. Thian, et al, “Ultrafast Low-Loss 40-70 GHz SPST Switch,” IEEE Microw. Wirel. Compon. Lett., vol. 21, no. 12, pp. 682–684, Dec. 2011.[5] K. Ma, et al, “A Miniaturized Millimeter-Wave Standing-Wave Filtering Switch With High P1dB,” IEEE Trans. Microw. Theory Tech. , pp. 1505–1515, Apr. 2013.[6] R. Shu, A. Tang, B. Drouin, Q. Jane Gu, “A 54-84 GHz Switch With 35dB Isolation,” IEEE Radio Frequency Integrated Circuits Symposium, Jun. 2015.[7] A. I. Lee, S. I. Tolstolutsky, V. V. Kazatchkov, A. V. Tolstolutskaya, “A Low Loss microwave solid GaAs SPST switch of range 18-40GHz,” 20th International Crimean Conference “Microwave & Telecommunication Technology, Jun. 2010.

0.65 dB Insertion Loss at 28GHz and 0.95 dB IL at 40GHz


22FDX® advantage for next-generation ADAS radar

Case Study: Radar Radio Architecture (3TX x 4RX)

• 3Tx/1Rx transceiver and block-level designs used for inputs to estimate the die size of the transceiver and the total power

• High power 14dBm PA with 15% PAE

• Low Noise Rx (7dB DSB NF)

• All Digital PLL with FMCW modulation

• Low phase noise DCO

• All blocks have been hardware verified

• With 4 Rx + 3 TX and digital interface the die size is estimated to be ~ 14mm2

• The total power of 4 RX + 2 TX with 50% duty cycle and TX @ full power is ~ 600mW (including LDO losses)

Blocks 1.2V Domain 1.8V Domain

4 Full Receivers with LO generation (mW) (incl. ADC)

95 75

DPLL +DCO + LO Line Drivers (mW) 69 4

2 Transmitters with PA (mW) 77 245

SERDES + Digital (mW) 29 0

Misc. 6 4

Total (mW) 276 328

77GHz 3Tx/4Rx Radar Transceiver with 600mW power consumption


3-Stack Power Amplifier

Two-Way Power Combiner

Two thick Copper metals are used (QA and QB)

77GHz Transmitter Measured Results Summary

14dBm 77GHz PA in 22FDX®

High Pout and PAE for ADAS long range radar

Leverages:

• FET Stacking for higher Pout

• Dual UTM Cu metals for low loss power combiner

• Back gate bias for tight Pout vs temp control (+/- 1dB)


SiGe BiCMOS Overview

• High performance SiGe HBT + CMOS

– Bandgap engineered with graded Ge profile in base region to enhance device performance

• Technology optimized for RF/analog applications

– Rich suite of additional devices and features, such as PIN, SBD, HAVAR, TSV

– Low loss BEOL metal/dielectric stacks with dual UTM levels

• HBT performance advantages and ease of design vs FET’s

– High fT AND fMAX

– >300GHz in production

– Roadmap to >500GHz, with 500GHz ft / 700GHz fmaxdemonstrated in a bipolar-only process *

– Higher breakdown voltage

– Better at generating power, particularly at high temperature

– Gm/um2 is much larger

– 1/f noise is 100x lower

– Much better transistor matching

Graded base bandgapadvantages• speeds electrons across base

(higher fT)

• reduces gC (improves Early voltage VA) for improved gain

• Increases gain (higher IC, gm

for a given VBE)* Heinemann B et al 2016 SiGe HBT with fT/fmax of 505 GHz/720 GHz IEEE Int. Electron Devices Meeting (IEDM)


• FET is lateral device with performance driven

by gate length scaling.

• Lg scaling for higher ft results in increased

wiring parasitics (both R and C)

• Intrinsic device parasitics need to be

optimized for improved mmWave

performance

• Rg becomes a limiter to fmax

• CMOS fmax peaks at ~450GHz in the 32nm –

22nm nodes and then decreases at more

advanced nodes

RGv

RchRlk

Csb Cdb

Rsil

Cgsx Cgdx

• HBT is a vertical device with performance

driven by both vertical and lateral scaling

• ft improvement through vertical scaling

• fmax improvement requires lateral scaling

for reduced Rb and Ccb

• Super-self-alignment schemes allow for low

parasitics while keeping high-ft

• 500GHz ft / 700GHz fmax demonstrated *

• > 500GHz technology will be needed for next

generation 6G and sub-THz applications

E

C

B

SiGe HBT and CMOS FET Comparison

* Heinemann B et al 2016 SiGe HBT with fT/fmax of 505 GHz/720 GHz IEEE Int. Electron Devices Meeting (IEDM)


SiGe HBT delivers higher output power PA at mmWave vs FET’s

• Higher breakdown voltage avoids the need for FET-stacking approach used in SOI Higher current density

• Improved ability to perform at speed at the top of the stack

• FETs more sensitive to parasitics in the metal stack

HBT breakdown voltage

BVCEO - Lowest BV when base is open

BVCBO - Highest BV when emitter is open

Most of the realistic BV for a circuit application is in

between the two extremes (BVCER)

Plot shows Ic increase from avalanche multiplication for a

forced Ib and with different RB

As RB decreases, BV increases from BVCEO to BVCBO limit

fT, fMAX, for SiGe & CMOS at the top metal & bottom metalA Comparison of the Degradation in RF Performance Due to Device Interconnects in Advanced SiGe HBT and CMOS TechnologiesRobert L. Schmid, Ahmet Ça˘grı Ulusoy, Saeed Zeinolabedinzadeh, and John D. Cressler

SiGe’s advantage in Phased Arrays

130nm SiGe:

BVceo 1.8

BVcbo 6V


90nm SiGe BiCMOS9HP Technology

130nm / 90nm SiGe BiCMOS Metrics

Technology Aspect Units130nm

SiGe90nm SiGe

Node nm 130 90

nFET fT GHz 95 150

Emitter Width (We) nm 120 100

Self Gain (gm/gds) 1600 990

fT NPN GHz 210 310

fmax NPN GHz 265 370

MSG/MAG 30GHz dB 18.6 19.6

Nfmin at 30GHz dB 1.6 1.1

Gassoc at 30GHz dB 9.6 11.3

BVcbo / ceo V 6.0 / 1.8 5.3 / 1.68

• Self-aligned emitter base junction

• MB HBT in addition to HP device

• ft/fmax 145/350GHz

• 8.4V BVcbo

• mmWave passives: SBD, PIN,

HAVAR, VNCAP, MIMs, Inductors

• CMOS: 1.2V, 2.5V, 3.3V FETs

• 10LM stack with thick Cu/Al levels

C

EBC

B


mmWave SiGe PA Capability

• 28GHz 23dBm 42% peak PAE Outphasing PA

• Leverages higher breakdown voltage of SiGe HBT to deliver high output power and efficiency

Source: B. Rabet, J. Buckwalter, A High-Efficiency 28GHz Outphasing PA with 23dBm Output Power Using a Triaxial BalunCombiner, ISSCC 2018


SiGe BiCMOS 5G Phased Array Transceiver

Source: Bodhisatwa Sadhu, Yahya Tousi, et al, A 28GHz 32-Element Phased-Array Transceiver IC with Concurrent Dual Polarized Beams and 1.4 Degree Beam-Steering Resolution for 5G Communication, ISSCC 2017

Highly integrated 32-element phased array Transceiver + Beamformer Front End in 130nm SiGe


Metrics SiGe8HP / 8XP 45RFSOI 22FDX

RF

NFET, npn 120nm 40nm 2xCPP 17nm 3xCPP

ft / fmax GHz210 / 265 (HP)250 / 340 (XP)

290 / 410 350 / 430

V DC (nominal) V 3.3 1.1 0.8

Vmax RF V ~ 3.5 ~ 1.4 ~ 1.8

PFET, pnpft / fmax GHz

17 / 22 245 / 305 270 / 315

Substrate Resistivity 10 Ohm-cm> 1K Ohm-cm

(Trap rich)10 Ohm-cm

Digital Logic

Density Gate/mm2

300K 1.5M 5.5M

SiGe and SOI Device Compare


Application requirements drive optimal radio partitioning

5GFEM-Centric Designs: high performance with architecture flexibility

Integration-Centric Designs: low system cost and low SOC power consumption

45RFSOI 22FDX• High Ft / Fmax• Hi-Resistivity substrate for high

power handling and low loss• FET stacking for higher Pout

(>20dBm Psat)• 1.5M gates/mm2 logic density

• High Ft / Fmax and high GM/I• FET stacking for higher Pout vs

CMOS• Back-gate bias• 5.5M gates/mm2 high density

low power logic

SPDT

SPDT

LNA

PAPower combiner/splitter

Up/Down conversion

LNA

PA

/2

/2

ADC/DAC

SPDT

SPDT

LNA

PAPower combiner /splitter

Up/down conversion

LNA

PA

/2

/2

ADC/DAC

Combiner / splitter

Digital Phase shifter

Modem + Host Processor

Digital Phase shifter

SiGe• SiGe HBT for higher BV without stacking • Higher Pout and linear efficiency

- 31 -WM-09 – New challenges and new trends mixing active and passive devices in silicon technology: from components to tunable RF functions

Summary• mmWave application requirements are driving innovation in

technology/device design, circuit design, and system implementation

• Differentiated silicon technologies can deliver optimal solutions for the performance, integration and cost challenges at mmWave

• SOI and SiGe BiCMOS technology and circuit examples reviewed

• PD-SOI: High resistivity substrate and FET stacking => high performance mmWave beamformer + FEM

• FD-SOI: Superior FET electrostatics, high density low power logic and unique back-gate for power/performance tuning => mmWave SOC integration

• SiGe BiCMOS: high breakdown voltage HBT => higher PA Pout and PAE

Thank you


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