POLITECNICO DI MILANOSiLLis: A Simplified

Language For Monitoring and

Debugging FPGA-based Systems

Paolo Roberto Grassi

Relatore: Prof. Donatella Sciuto

Correlatore: Ing. Marco Domenico Santambrogio

2

OutlineOutline

IntroductionThesis GoalsState of ArtProblem Definition

Listener: General Structure

SiLLisGrammarPaths and GuardiansTranslation

Case StudiesReconfiguration MonitorPerformance Monitor

Concluding Remarks

3

IntroductionIntroduction

The process where a system is exercised and its resulting response is analyzed to ascertain whether it behaved correctly or not is called testing.Debugging is a methodical process of finding and reducing the number of bugs, or defects, in a computer program or a piece of electronic hardware thus making it behave as expected

Thesis GoalsThesis Goals

Definition of a high level language for the convenient description of hardware components for monitoring of communication lines on FPGAs

The project aims at overcoming the following limits that affect commercial and non-commercial tools :

Debugging InvasivityLimited Debugging PeriodQuality of Gathered Data

The project is focused on on-line, self, system-level, at-speed, compact, in-circuit testing

4

State of ArtState of Art

Lots of solutions were proposed to solve the problem of FPGA-debugging:

External devices connected to the I/O pins of the FPGAInternal components with TAP (Test Access Port) interfaceClock Gating [*]

5

[*] J.N. Tombs, et al. “The implementation of a FPGA hardware debugger system with minimal system overhead”, in FPL, 2004, pg. 1062-1066

State of Art – Commercial SolutionsState of Art – Commercial Solutions

Xilinx® ChipScope Pro™ChipScope inserts logic analyzer, bus analyzer and virtual I/O low-profile software cores directly in the system, allowing the possibility to view any internal signal or node, including embedded hard or soft processors

Synplicity® Identify®

It allows you to navigate your design graphically and mark signals directly in RTL as probes or sample triggers

SignalTap® II by Altera®

Provides a solution that allows you to examine the behavior of internal signals, without using extra I/O pins, while the design is running at full speed on an FPGA device

6

Problem DefinitionProblem Definition

Blind-Monitor: It captures the data every clock cycle, store it in memory or transfer it directly to an external application

Listener: It read the data, filter that and, eventually, recognize and understand if something happens

7

Monitoring Time Memory Requirement

Monitoring Time Memory Requirement

rTnf

Mt

0 )(0 rTnftM

rTnf

Mt

0 )(0 rTnftM

Listener: General StructureListener: General Structure

In order to have a feasible, non-stopping, debugging activity, the following relation must be satisfied:

8

0 0

1

0

1

0

),(),(i i

OUT

n

kSYS

n

k

fikefikhOH

SiLLis: Simplified Language for ListenersSiLLis: Simplified Language for Listeners

Every listener is composed of:Parameter Definition (optional)Interface Definition (required)Internal Variable Definition (opt.)External Variable Definition (opt.)Paths (optional)Guardians (optional)

It provides some Special (predefined) functions:

sleep(n)wait(A)resetflush(A)

9

parameter LOW_TRIGGER = 3; HIGH_TRIGGER = 9;end parameter;

interface input : in STD_LOGIC_VECTOR(0 to 8); increment : in STD_LOGIC_VECTOR(0 to 8);end interface;

internal_variables data : STD_LOGIC_VECTOR(0 to 8);end internal_variables;

external_variables reset_data : STD_LOGIC_VECTOR(0 to 8);end external_variables;

path (increment>0) is data = reset_data; sleep(1); if input < LOW_TRIGGER then flush(data); else loop_until input > HIGH_TRIGGER then data = data + increment; flush(data) end loop_until; end if;end path;

guardian (input>HIGH_TRIGGER) is wait(input<LOW_TRIGGER); reset;end guardian;

SiLLis: Paths and GuardiansSiLLis: Paths and Guardians

Paths and guardians contain the code related to the filtering logicEach guardian can contain a set of paths, but paths cannot contain guardiansThe effect of the activation is different for paths and guardians:

When a path is activated, it inhibits the activation of other pathsWhen a guardian is activated, it inhibits the activation of both paths and guardians. If a path is activated, its execution is temporary frozen

10

Condition

Current State Effect

Path False Not important Nothing

Path True No guardians or paths activated Path activated, other paths inhibited

Path True One guardian or path activated Nothing (path inhibited)

Guardian False Not important Nothing

Guardian True No guardians activated Guardian activated, everything inhibited

Guardian True No guardians activated, path activated

Guardian activated, path frozen

Guardian True One guardian activated Nothing (guardian inhibited)

SiLLis State Machine ManagerSiLLis State Machine Manager

The Guardians State Machine controls the output of the two state machinesIt is activated by triggers at runtimeIt blocks the Paths State Machine in order to manage the event

11

Paths State Machine

Guardians State Machine

SiLLis TranslatorSiLLis Translator

The SiLLis description is translated into synthesizable VHDL in order to be integrated into the systemTo easily perform the VHDL composition, SiLLis uses vMagic, a Java API that allows to write VHDL from Java Class definitions

12

First Case Study: Reconfiguration MonitorFirst Case Study: Reconfiguration Monitor

13

The first case study used to prove the usability of SiLLis is a runtime monitor for dynamic reconfigurabilityThe system contains a controller for the pendulum that is reconfigured at runtimeA SiLLis component catches the partial bitstream that goes to the reconfiguration controller filtering all the other unuseful data

Processor

Reconfiguration Controller

SiLLis Listener

Motor

Encoders

M E1 E2

BUS

Pendulum Controller

Visualization

SDRAM

First Case Study: Reconfiguration MonitorFirst Case Study: Reconfiguration Monitor

Processor

Reconfiguration Controller

SiLLis Listener

Motor

Encoders

M E1 E2

BUS

Pendulum Controller

Visualization

SDRAM

1. Processor Request2. Reconfiguration Controller SDRAM Access3. Bitstream Transfer

14

First Case Study: Experimental ResultsFirst Case Study: Experimental Results

Blind-Monitor Area Occupation

SiLLis Reconfiguration Listener Area Occupation

Throughput comparison

Logic Utilization Used Available (VP30)

Utilization (VP30)

Number of Slices 132 27.392 1%

Number of Slice Flip-Flops 131 27.392 1%

Number of 4 input LUTs 193 13.696 1%

Logic Utilization Used Available (VP30)

Utilization (VP30)

Number of Slices 134 27.392 1%

Number of Slice Flip-Flops 133 27.392 1%

Number of 4 input LUTs 234 13.696 1%

Logic Utilization Data Size Available (VP30)

Utilization (VP30)

Blind-Monitor 64 bit 100 MHz 800 MB/sec

SiLLis Listener 200 KB 10 Hz 2 MB/sec(64-bit PLB bus running at 100 MHz)

15

Second Case Study: Performance MonitorSecond Case Study: Performance Monitor

SiLLis listener are integrated into the GigaNoC systemDuring the process of data gathering performed by the listeners (L), additional information is added to the data The information contains the timestamp of the current clock cycle and the indentifier of the signal

17

Second Case Study: Experimental ResultsSecond Case Study: Experimental Results

FPGA-resource requirements on a Xilinx Virtex-II 8000Component Slices Flip

FlopsLUTs BRAMs

Processing Element (PE)

15.362

8.719 22.233 80

Switch Box (SB) 14.133

13.340 16.383 -

Listeners (L1,L2) 171 110 267 -

Delay Statistics of GigaNoC traffic load experiments

18

Concluding RemarksConcluding Remarks

The state of art presents a set of commercial and non-commercial solutionsIn order to solve problems of blind-monitors, listeners were proposedPre-defined structure of a listener permits the definition of languages for its convenient descriptionSiLLis combines an easy grammar and a powerful set of instructionsThe power of SiLLis has been shown in the areas of network-on-chip and reconfigurable architectures

Future Works:Additional functions can be integrated, which will be useful to describe the desired behavior more confortablyDifferent application fields: Parallel Computing, Multi-Procesor Systems, Multi-FPGA Systems, Adaptive Systems19

20

QuestionsQuestions

Thanks for your attention...