Dr. Mariam Md Ghazaly BEKC4883 1 Industrial Talk; Manufacturing Systems in E&E Sector Prepared by Mohd Azizi bin Chik SilTerra Malaysia April 28 th 2013 2 GROUND RULE • Discussion on related topic only • Formality tolerate • Can stop any time for emergency case, but raise hand first • Try to have fun • Three Ways Communication 3 Expected candidates in this class • Everyone that new to Wafer Fab operation … new employee, partnership, internships, researchers, or visitors of SilTerra. Others that equivalent are also invited … 4 5 Content Guidelines (2 of 2) • Introduction to Manufacturing operation (02:00pm – 04.00pm), Group discussion (2:30 pm to 3:30 pm), Results reviews • Simulation modeling for Manufacturing Operation • Capacity, Bottleneck, & Product Mixed • Dispatching Rules Policies and review basic company case study – Working Group Presentation (1hrs, Group presentation 5 min each) • Exercise for Dispatching Rules • Presentation and proposal (Discussion) 6 Electrical & Electronic (E&E) Outlook 1 Brief on Semiconductor Fabrication 2 Advance Manufacturing Application Outlook 3 4 Introduction to Manufacturing Operation & Production Scheduling Session I Session II
Transcript
Dr. Mariam Md Ghazaly BEKC4883
1
Industrial Talk; Manufacturing Systems in E&E Sector
Prepared by Mohd Azizi bin Chik
SilTerra Malaysia
April 28th 2013
2
GROUND RULE
• Discussion on related topic only
• Formality tolerate
• Can stop any time for emergency case, but raise hand first
• Try to have fun
• Three Ways Communication
3
Expected candidates in this class
• Everyone that new to Wafer Fab operation … new employee, partnership, internships, researchers, or visitors of SilTerra. Others that equivalent are also invited …
4
5
Content Guidelines (2 of 2)
• Introduction to Manufacturing operation (02:00pm – 04.00pm),
Group discussion (2:30 pm to 3:30 pm), Results reviews
• Dispatching Rules Policies and review basic company case study
– Working Group Presentation (1hrs, Group presentation 5 min each)
• Exercise for Dispatching Rules
• Presentation and proposal (Discussion)
6
Electrical & Electronic (E&E) Outlook1
Brief on Semiconductor Fabrication2
Advance Manufacturing Application Outlook3
4Introduction to Manufacturing Operation & Production Scheduling
Session I
Session II
Dr. Mariam Md Ghazaly BEKC4883
2
7
Source, Malaysia Economic Transformation Annual Report 2012
8
Source, Malaysia Economic Transformation Annual Report 2012
9
Source, Malaysia Economic Transformation Annual Report 201210
Source, Malaysia Economic Transformation Annual Report 2012
11
ELECTRONIC PROCESS SUPPLY CHAIN
Raw Wafer Fabrication
Packaging & Assembly
PCBA Final Product Assembly
Wafer Fabrication The most complicated processcompared to others in electronic chain
12
Global Semiconductor Forecast
• Semiconductor outlook for the next 3 years is still healthy 7.9 CAGR 2012- 2015 (IC foundry Almanac 2012).• Stable Demand for 8” matured technology and conversion of 6 to 8 by IDM (Gartner Oct 2011).
Dr. Mariam Md Ghazaly BEKC4883
3
13
Fab Cluster Expanding in China
14
Wafer Fabrication & Bumping Facility at Hsinchu, Taiwan
(6 fab facilities)
(1 fab facility)
(7 fab facilities)
(1 fab facility) (1 fab facility) (1 fab facility)
(1 fab facility)
(1 fab facility)
(1 fab facility)
15
Wafer Fabrication & Bumping Facility at Woodlands, Singapore
Woodlands
(6 fab facilities) (1 fab facility)
(1 fab facility)
(1 fab facility)
(1 fab facility)
(1 fab facility)
16
Malaysia’s Electronic Clusters
Melaka
Johor
Selangor / KL
Perak
Negeri Sembilan
Kedah
Semiconductor Front End
Silterra Hamad
a
Infineo
n
Semiconductor Back End
AIC Intel Hitachi
System / Module / Device
Sharp Fuji Akrion
Applied Materials ASML
KLA Tencor Asyst
Celestica Metex Wong
Equipment
Sharp Onkyo Aviza
Axcelis Intevac Varian
Lam
Research
QT Services
Semiconductor Front End
S.E.H. MEMC
Semiconductor Back End
Freescal
e
TI Toshiba
Spansion ChipPac
k
NEC
System / Module / Device
Sensata Flextron
ic
Nichia
ChungHu
a
Equipment
WD Epson Samsung
Panasoni
c
Sony Flextronic
s
Hitachi Sharp Onkyo
Canon
Semiconductor Back End
ST Micro ST Memory
System / Module / Device
Seagate Mitsui Mitsutoyo
Nemic-Lamda PCA
Tech
Ronnie Hokuden FCI
Komag Pioneer
Equipment
Brother Celestica Sharp
Flextroni
cs
Kenwoo
d
Sanyo
Mitsubis
hi
Panasoni
c
Podoyo
Mitsumi Seiko
Semiconductor Back End
Carsem Unisem IDS
System / Module / Device
Murata
Semiconductor Back End
On Semi NXP
System / Module / Device
Alps TDK NHK
Equipment
Samsun
g
Xyratex
Semiconductor Back End
Intel AMD Linear
Spansion Marvell Globetro
nic
Osram Lumileds Altera
IDT Avago ASE
Fairchild Hitachi Sumitom
o
System / Module / Device
Seagate Plexus Knowles
Smart
Mo
Kingston Jabil
Sanmina Kontron Flextroni
c
Solectro
n
Komag Molex
Equipment
Dell Solectro
n
VDO
Agilent Sanyo LKT
Inventec Ben-Q Penta
Clarion Bosch Vitrox
Penang
Semiconductor Back End
Infineon Qimonda
Dominant NS
System / Module / Device
TEAC Qualiteck
Muhlbeuer Flextronic
Equipment
Panasonic Creative
Semiconductor Front End
X-Fab
System / Module / Device
Taiyo
Yuden
Toko
Sanmina Komag
Sarawak
Silterra
17
2010 Foundry Ranking by Gartner. Clear lines are drawn. Its Top 4 and the rest…
18
Silterra Malaysia Sdn Bhd
• Top Fab 2002• Frost & Sullivan 2009 Award High Voltage Tech Implementation• Product Excellent Award 2009• Capacity 30K Wafers per Month• Consistent Utilization of more than 100%• SilTerra continues at full utilization last year. In 2010, SilTerra supplied 25.6% of DDI’s global market (source RSSM 2011).
Dr. Mariam Md Ghazaly BEKC4883
4
19
Breakdown by Degrees of Engineering in FAB
20
Q&A OR DISCUSSION
• At least 3
21
Short Video
• SilTerra
22
Electrical & Electronic (E&E) Outlook1
Brief on Semiconductor Fabrication2
Advance Manufacturing Application Outlook3
4 Introduction to Manufacturing Operation & Production Scheduling
Session I
Session II
23
What’s in a Chip
24
Relative Size Comparison (Size does matter!)
Dr. Mariam Md Ghazaly BEKC4883
5
25
PROCESS COMPLEXITY
Wafer fabrication process, is a process to make mask layers. These represent basicstructure like transistors, capacitor, insulator and etc. Process steps are between 300to 900 steps, almost 100% re-entrance to same equipment. More than 35% Re-entrance at 10 to 18 times. Cycle time varies from 30 to 90 days. Cycle timemeasurement is DPML = days per mask layer
26
Introduction: Adding Layers …
27
Short Video
• Silicon Magic
28
Q&A OR DISCUSSION
• At least 3
29
Electrical & Electronic (E&E) Outlook1
Brief on Semiconductor Fabrication2
Advance Manufacturing Application Outlook3
Session I
Session II4 Introduction to Manufacturing Operation &
Production Scheduling
30
Toshiba CorporationSource Iwai RSSM 2011
1970’s
Dr. Mariam Md Ghazaly BEKC4883
6
31
300 mm Super clean room in Tsukuba,Selete
Toshiba OitaWorks
300 mm Fab TSMC
Now
Source: Iwai RSSM 2011 32
In a futureNo person is necessary!
Source: Iwai RSSM 2011
33
FAB LAYOUT
34
Further Advanced Manufacturing Systems Architecture
w1
35
Fab7 Command and Control Center (C3) … début in 2007
36
APF New Architecture
Slide 34
w1 - Try to keep titles consistent, if "F7" indicates "Fab 7" then we suggest keeping to "Fab 7" as previous slides indicate it as such.wuuf, 8/18/2004
Dr. Mariam Md Ghazaly BEKC4883
7
37
Example: Server configuration for dispatching/data collection related
Storage
38
“Imagination is more important than knowledge. Knowledge is limited. Imagination encircles the world”
Albert Einstein
Scientist
Knowledge and Imagination
39
Electrical & Electronic (E&E) Outlook1
Brief on Semiconductor Fabrication2
Advance Manufacturing Application Outlook3
Session I
Session II 4 Introduction to Manufacturing Operation & Production Scheduling
40
One MillionUnits
Product Time-to-Market Is Vital
B&W TVCable TVColor TVVCRPCCellularPCSDVD
The impact of being late to market is becoming very significant. Faster cycle time needed, also resulted in lowered down equipment capacity
High Ranges Product Mix vs. Variable Process Cycle Time
44
V = IR
Variability = Income Reduction
Dr James Ignizio, IntelISSM 2003
Introduction: OHM’s Law
45
• There are many sources of variability– Process variability
– Flow variability
– Equipment failure
– Batch Sizes
– Equipment Setup Changeover Times
– AMHS delivery times
– In consistent WIP levels
– Huge Data collection
– Loading Plan or Demand Plan
– Inefficient dispatch policies
– Inconsistent dispatching
Introduction: Sources of Variability
46
DISPATCHING RULE GOAL
• Overall main goal
– Lot delivery time (OTD)
• Dispatching based on priority, due date (Critical Ratio, CR = ((due date – current date)/remaining cycle time)
with quality consideration given*
– Reduce Cost (high move, more capacity, improve Efficiency)
• Optimum possible batching, not breaking allowable queue time
47
Others Common Dispatching Rule available
• Others Business Rule available, are– FCFS ( First Come First Come First Serve)
– SPT ( Shortest processing Time)
– EDD (Earliest Due Date)
– CR* (Critical Ratio) * Currently used for dispatching
48
First Come First Serve (FCFS)
• Selection of the product to be process is based on the arrival time. Product reach first, will be selected to be process first.
• In factory, Its it preferred to use in the situation of low loading or utilization. (traditional method to serve common interest in service industry)
Dr. Mariam Md Ghazaly BEKC4883
9
49
Shortest Processing Time
• Selection of the product to be process is based on the shortest processing time. Usually when there is significant amount of WIP due to unexpected down-time from module.
• This is temporary dispatching policies during high WIP situation and when certain criteria met.
50
Earliest Due Date
• Selection of the product to be process is based on the earliest due date. Usually during moderate loading with less product-mixed
51
Critical Ratio
• Selection of the product to be process is based on the smallest ratio of due date vs remaining processing time. Mainly used during moderate WIP level for production required re-entrance processing, and high product-mixed.
52
GROUP ASSIGNMENT
53
Dispatching Rule Computation
• Calculation is being done for 5 seconds
Collect the required information from various systems
Data structure formatting
Formula computation
Organizing the output configuration
Calculation for “CR,”, lot assignments,… What & Where Display difference color & at what equipment
54
BREAK 10 MINUTES
Dr. Mariam Md Ghazaly BEKC4883
10
55
DISPATCHING (PHOTO)
56
DISPATCHING (DIFFUSION)
57
Example of APF Programming
Close similar to C ++ programming …
58
CASE STUDY –ALIKE
59
Roles of APF/RTD at SilTerra
APF Reports and RTD are one of the key tools to improve manufacturing efficiency andthe breakdowns are as follows with examples in the next few slides.
60
Current Dispatching Policies
• Total Dispatch Rule = 72, Almost all are design to optimize move in each tool type capability.
Dr. Mariam Md Ghazaly BEKC4883
11
61
Benchmarking Dispatching Policies
62
OPTIONS: HYBRID DISPATCH POLICIES
63
Hybrid Type Sample: Critical Ratio with Starvation Avoidance
Critical Ratio :
• To meet customer delivery date
Starvation Avoidance :
• To ensure bottleneck tools always have WIP to run
64
Calculations Details• Critical Ratio :
(Due Date – Current Time) / Remaining Plan Cycle Time
• Starvation Avoidance : Time Required at the bottleneck / Lot Plan cycle time
to bottleneck
Ø Time Required at Bottleneck :
((å (Time_to_BN x WIP)) - (Time_to_BN x WIP)) + ((Bottleneck Bottleneck TCT x Bottleneck WIP)TCT x Bottleneck WIP))) - Buffer
It Means………..(Total Work Time for WIP to BN) + (Work Time at BN
) – WIP Buffer Time
65
Starvation Avoidance
66
Critical Ratio Vs Starvation Avoidance
Dr. Mariam Md Ghazaly BEKC4883
12
67
Final Ranking
68
Q&A
69
Summary
• New Learning regards– Overall picture about semiconductor fabrication, its
complexity and our application in today environment
