SIMPLIFY ENERGY-EFFICIENT DESIGNS WITH COST-EFFECTIVE …

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SIMPLIFY ENERGY-EFFICIENTDESIGNS WITH COST-EFFECTIVESoC PLATFORM

11/15/19

TSMC OIP Ecosystem Forum Santa Clara, Beijing, Israel – October 2019Pierre Gazull, Business Development Manager

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1THE QUEST FOR ENERGY-EFFICIENCY

15/11/2019 3

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CAN YOU FIND THE DIFFERENCES ?

? ? ?

? ? ?

BatteryAutonomyDuty CycleProcessing Load


CAN YOU FIND THE DIFFERENCES ?Battery

AutonomyDuty CycleProcessing Load

High Mostly ON Hours

Low Mostly OFF Years


CAN YOU FIND THE SIMILARITIES ?

?

?

? ??

Key ChallengeMarketConstraintsMissions

?


CAN YOU FIND THE SIMILARITIES ?

Connect

TTM

Cost Battery LifeSense

Key ChallengeMarket ConstraintsMissions

Process

ENERGY-EFFICIENCY REQUIRED


HOW TO IMPROVE ENERGY-EFFICIENCY ?

• Moore’s law

(slowing down !)

• Low Vdd / NTV

operation

• Ultra-low leakage

devices

• Low-power

techniques

(DVFS,..)

• Use of ePMU

• Low-power modes

• Low-leakage IP

• Energy-Efficient IP

PROCESS NODE DESIGN TECHNIQUES ARCHITECTURE

• Advanced SoC

architecture

• Optimized power

regulation network


KEY IoT PROCESS NODES

55 nm• ULP• eFlash

40 nm• LP/ULP• Low Vdd• eFlash / RRAM

22 nm• ULL / ULP• Low Vdd• MRAM


POWER MODES & ENERGY-EFFICIENCY

SoC running - All blocks ON µA / MHz

Logic Domain & SRAM in retentionIO and AON/RTC active < 1 µA

SoC running in LP modeMCU OFF - RF OFF µA / MHz

Logic domain OFF - SRAM OFFIO disabled - AON/RTC active < 500 nA

Only wake-up pin remain activeAON/RTC is OFF < 100 nA

Low Leakage IPs

for Sleep Modes & AON Domain

Energy-Efficient IPs

for On-Demand Domain SoC running in LP mode

MCU ON - RF OFF µA / MHz

ACTIVE

LOW POWER

SLEEP

DEEP SLEEP

SHUT OFF

STOP

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2OUR JOURNEY TO ENERGY-EFFICIENCY

15/11/2019 11


OUR JOURNEY TO ENERGY-EFFICIENCY

Launched as Mixed Signal ASIC design center

CONSISTENT SET OF IP CLUSTERS• Always ON domain• Sensor hub/Trigger domain• Active power domain • Fast modes transition

POWER MANAGEMENT AS IP PLATFORM• Unified IP specifications• Modular & configurable IPs • For fastest and safest design-in of most Energy-Efficient SoCs

SPEEDSYSTEM PLATFORM FOR ENERGY-EFFICIENT DESIGNAccelerate the cost-effective design of Energy Efficient SoCs

START OF THE VENTURE• Memories & standard-cells• Delta-sigma converters & MCUs• Power management & ULP clocks

1985

1998

2014

2016

2019


55 nm ULP eFlash

FOUNDATION IP• Single & Dual Port SRAM• ROM• 6T HD/UHD and 9T standard cells libraries

POWER MANAGEMENT IP• LDO & Ultra-low quiescent LDO• High-efficiency DCDC• POR-BOR• 32 kHz ULP RC & Xtal oscillators

CLICK : automated power gating solution with built-in control of in-rush current

AON cluster with less than 0.5 µA consumption in deep sleep mode

Demonstrates Dolphin’s capability to implement a

complex SoC with advanced low-power techniques

TAISHAN demochip (T/O 2016)• 12 mm2 in TSMC 55nm ULP eFlash• 6 power modes, 4 power domains


“Dolphin Integration brought one of their PMU (aka VREG)

solutions to the test chip, in order to bring energy efficient

conversion of incoming battery voltage.

Arm selected this partner for their structure design approach

to safely generating an optimised power management unit

according to any chip’s specific requirement. This capability is

key for Arm partners who want to develop integrated IoT

systems and will help them optimize SoCs faster and without

risk.”

Mike Eftimakis

40 nm LP/ULP eFlash

POWER MANAGEMENT IP• LDO & Ultra-low quiescent LDO• High-efficiency Low BoM DCDC• POR-BOR• 32 kHz ULP RC & Xtal oscillators

ARM MUSCA-B1 TEST CHIP LEADS THE WAY INDEVELOPING SECURE IoT CHIP DESIGNS FASTER

PixArt Imaging selects voltage regulators IPsfrom Dolphin Integration for its ultra-low power MCU Sensor in 40 nm

INGChips selects Dolphin Integration's PowerManagement IP Platform for its ultra LowPower Bluetooth Low-Energy SoC in 40 nmeFlash


AON Cluster

INTRODUCING 22 ULL IP PORTFOLIO

Voice Acquisition

(ADC)

Keyword Spotting

Speech Recognition

Language Processing

WhisperTrigger(Voice Activity

Detection)

ULP VOICE ACTIVITY DETECTION

FAST WAKE-UP ULP ADC

Wake-Up Signal

POWER MANAGEMENT IP

Low quiescent LDO

Ultra-low IqµLDO

Capless LDOHigh-Efficiency Low BoM DC-DC

32 kHz ULP OSCPOR-BOR

1 ms wake-up 104 dB dynamic range

Ultra-low latencyUp to 8 channels

Automatic Gain Control

Active Noise Cancellation

8 uA

RTC


3PUSHING ENERGY-EFFICIENCY FURTHER


PUSHING ENERGY-EFFICIENCY TO THE NEXT LEVEL

69%49%

46%32%

24%23%

17%13%

9%7%6%

4%2%

RTL Clock GatingPower Gating

Block-level Clock GatingMulti Voltage

DVFSPower Intent (UPF)

Memory GatingData Gating

Memory vs Register fileBus Architectures

Memory Caching/BankingRegister sharing

Other

Source : Semiengineering, 500+ RTL designers surveyhttps://semiengineering.com/micro-architectural-exploration-for-low-power-design/

Most Popular

Rarely Used

Further EE improvements are calling for new architectural approach

Power Management Techniques are gaining momentum in IC/ASIC design

Source : Wilson Research Group and Mentor, A Siemens Business, 2018 FunctionalVerification Study


ENABLING AI AT THE VERY EDGE

Mr WOLF – ETH Zürich

Technology CMOS 40 nm LP

Chip area 10 mm2

VDD range 0.8 V - 1.1 V

Memory Transistors 576 Kbytes

Logic Transistors 1.8 Mgates

Frequency Range 32 kHz – 450 MHz

Power Range 72 µW – 153 mW

DVFS modes 6 modes

Source : ESSIRC 2018, Mr.Wolf, a 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IoT Edge Processing


ENABLING AI AT THE VERY EDGE

SoC domain

LOG-interco

I/OµDMA

APB-interco

RISC-V

Sh Sh Sh Sh

DSP cluster

LOG-interco

RISC-V#0

AON domain

PMU Regulators

RTC

Pr Pr #0 #1 #15

L1 Memory

RISC-V#1

RISC-V#7

DMA

………

….

POR-BOR

L2 Memory

• Optimized Always-On• Very low BoM• Fast and safe integration• Secured transitions• Accurate DVFSNicolas Gaude, Dolphin Design - Enabling AI at the Edge in TSMC 40nm

TSMC Symposium Europe, April 2019

• On-demand capacity• Switchable memories• Interleaved partitioning• Logarithmic intrinsic

delay• Reduced congestion

• Dedicated DSP cluster for intensive computational tasks

• Shared L1 memory supports single-cycle concurrent access from different cores

• Cluster DMA controller to transfer data between shared L1 scratchpad and L2 memory


SILICON RESULTS

12x

Source : ESSIRC 2018, Mr.Wolf, a 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IoT Edge Processing


DRAWBACKS OF TRADITIONAL APPROACHES

• Use of individual IP, sub-optimal

global solution

• Iterative addition to build chips with

drawbacks of increasing costs related

to architecture and verification with

new nodes

• Long design flow times and large

pool of various technical expertise

60% of HW design costs in

Architecture and

Verification

Software

Hardw

are

Source : IBS, Design Activities & Strategic Implications, Cost of Advanced Designs (2018)


EDGE APPLICATIONS Power Management Platform

SoC Platform

Up to 10X Up to 100X

SPEED PLATFORM : ENERGY-EFFICIENCY WITHOUT LIMITS

Pre-configured & Qualified IP Clusters

Automated and secure design of SoC

power network

Streamlined generation of input files for standard EDA flows

Configurable energy-efficient SoC architecures

OUR TURNKEY SOLUTION FOR ARCHITECTURE, POWER NETWORK DESIGN AND IMPLEMENTATION OF AN ENERGY-EFFICIENT SOC


POWER MANAGEMENT PLATFORMDEFINE & OPTIMIZE YOUR SOC POWER NETWORK

BUILDa set of power networks

1




1

IP Models Library

Power state table

SoC specifications




1

IP Models Library

Power state table

SoC specifications

EXPLORE & CHECKeach architecture

2




1

IP Models Library

Power state table

SoC specifications


2

IP compatibility checks

Figures of Merit




1

IP Models Library

Power state table

SoC specifications


2


Figures of Merit

GENERATEstandard EDA files

3




1

IP Models Library

Power state table

SoC specifications


2


Figures of Merit

GENERATEstandard EDA files

3

PMU RTL

Top-Level UPF

Top-Level RTL


KEY TAKEAWAYS

1. Established energy-efficient IP portfolio for key IoT process nodes

2. Expanding our power management & audio IP portfolio to TSMC 22nm ULL

3. Introducing SPEED platform, our turnkey solution to handle architecture,

power network design and implementation of an energy-efficient SoC

4. A new corporate identity

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