IJSRD - International Journal for Scientific Research & Development| Vol. 3, Issue 04, 2015 | ISSN (online): 2321-0613

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Simulation of New Cascaded Multilevel Inverter with Reduced Number

of Switches using SPWM

Megana I G1 Chethan C.P

2

1,2M.Tech Student

1,2Department of Electrical Electronics Engineering

1,2Reva Institute of Technology and Management, Bangalore

Abstract— Multilevel inverter have become more popular

over the years in electric high power applications with the

promise of less disturbance and the possibility to function at

low switching frequencies than ordinary two level inverter.

Though multilevel inverter more advantages features usage

of more umber of switches in the conventional type leads to

the limitation of its wide area applications. Therefore a new

multilevel inverter topology is introduced with reduced

number of switches and gate driver circuitry, there by

resulting in minimum switching losses which will further

reduce installation cost. The performance of new multilevel

inverter is measured in terms of THD using carrier based

PWM technique. The results are validated using MATLAB.

Key words: MATLAB, THD

I. INTRODUCTION

In recent years, industry has begun to demand higherpower

equipment in the megawatt level. Controlled ac drives which

are in the megawatt range are connected to the medium-

voltage network. But today, it is very difficult to connect a

single power semiconductor switch directly to medium

voltage grids. For these reasons, a new family of multilevel

inverters has emerged as the solution for working with

higher voltage levels.

These multilevel inverters include an array of

power semiconductors and capacitor voltage sources, from

which we get a stepped output voltage waveforms. The

commutation of the switches permits the addition of the

capacitor voltages, which reach high voltage at the output,

while the power semiconductors must withstand only

reduced voltages. Three different topologies have been

proposed for multilevel inverters: diode-clamped or neutral

clamped; capacitor- clamped or flying capacitors; and

cascaded multilevel inverter with separate dc sources. In

addition, several modulation and control strategies have

been developed or adopted for multilevel inverters including

the following: multilevel sinusoidal pulse width modulation

(PWM), multilevel selective harmonic elimination, and

space-vector modulation (SVM).

II. CASCADED MULTILEVEL INVERTER

A cascaded multilevel inverter topology is introduced here,

which is based on the series connection of single-phase

inverters with separate dc sources. Fig 1.shows the circuit

for five level inverter with two H-bridge connected in

series. The resulting phase voltage is the addition of the

voltages generated by the different bridge. Each single-

phase full-bridge inverter generates three voltages at the

output: +Vdc , 0, and -Vdc. On further addition of one more

H-bridge two more level are generated. Therefore resulting

output ac voltage swings from +2Vdc to – 2Vdc with five

levels, and the staircase waveform is nearly sinusoidal, even

without filtering.

III. CONVENTIONAL 7-LEVEL CASCADED MLI

A conventional seven level multilevel inverter requires three

H-bridge connected in series shown in Fig 2.. Total twelve

switches are required. When compared with other two

topology of multilevel inverter cascaded is more

advantageous as it requires less number of

components[1].As it is mentioned simplicity is the main

advantage researches are carried out in the area of multilevel

inverter so that modification are made to conventional type.

Fig. 1: Cascaded Five Level Multilevel Inverter

Fig. 2: Cconventional 7 Level Inverter

Simulation of New Cascaded Multilevel Inverter with Reduced Number of Switches using SPWM

(IJSRD/Vol. 3/Issue 04/2015/059)

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A new seven level inverter with 9 switches and

three dc sources[2] was developed which gave desired seven

level stepped waveform with low THD. Further

investigation has been carried out which uses seven switches

and three dc sources which gave desired output with low

THD. Yet further improvement from the existing topology

were made which results into 6 switches with four dc

sources to get desired seven level output[3].this made a

drastic move in the development of different topology since

THD is low and gate diver required is less. Aiming at

reducing the switches still further to the maximum possible

extent and also to reduce the complexity, a new topology is

introduced which uses five switches and four dc sources and

this would be the least possible way of reducing the

switches.

IV. PROPOSED 5 SWITCH TOPOLOGY

The proposed MLI configuration uses one less switch when

compared to the existing 6 switches [3]. This circuit is the

simplest design compared to conventional and all other

existing topologies.

Generalized expression for output voltage levels for the new

topology proposed is

𝑚 = (2∗𝑛−3),

Where 𝑚 =number of output voltage levels,

𝑛 = number of switches

Or 𝑚 = (2 ∗ V −1),

where V = number of dc sources.

The design of the pulse generation circuit makes

this topology differ from others so as to obtain the unique

pulse pattern to turn on the switches at the proper instant.

Switches S1, S2, and S3 need to be compulsorily

unidirectional or else the output waveform will get distorted.

Reduced switches make the circuit more compact in size .

Though the usage of 4 dc sources for the generation of 7-

level MLI results in less utilization of sources. H-Bridge are

not used. Just 2 switches are used for the polarity reversal.

Table 1. represent the switching scheme for the proposed

topology.

Fig. 3: 7 Level 5 Switches Proposed Topology

This topology is further implemented for nine level

output. This circuit consist of total six switches where S5

and S6 switches are used for polarity and S1-S4 are used for

generation of levels. This consists of total five dc voltage

sources shown in Fig 4., the switching table is as shown in

Table 2.

Switch

1

Switch

2

Switch

3

Switch

4

Switch

5

Output

voltage

OFF OFF ON OFF ON +Vdc

OFF ON OFF OFF ON +2Vdc

ON OFF OFF OFF ON +3Vdc

OFF OFF OFF OFF OFF 0

ON OFF OFF ON OFF -Vdc

OFF ON OFF ON OFF -2Vdc

OFF OFF ON ON OFF -3Vdc

Table 1: Switching Table for 5 Switches

V. SIMULATION CIRCUIT

The proposed circuit consists of 5 unidirectional mosfet

switches. The resistive load with 10ohms is connected. Four

10V dc input voltages are used Fig5. Shows the simulation

circuit of proposed topology

Similarly for nine level six mosfet switches are used along

with five dc voltage sources shown in Fig 7.

For the 10 ohm resistive load mosfet block parameters are

FET resistance=0.01ohms,

internal diode resistance=10kilo ohms

VI. METHODOLOGY

The pulse generation is essential in order to turn on the

switches in the appropriate manner in order to obtain desired

output level. The simplest carrier based technique is used

which is further divided into phase shifting and level

shifting. Level shifting is preferred over phase shifting.. in

level shifting PWM we have three methods phase

disposition(PD), phase opposition disposition(POD),

alternate phase opposition disposition(APOD). While using

level shifting scheme, an „N‟ level inverter requires „N-1‟

carrier waves.

Fig. 4: Nine Level Cascaded MLI

Simulation of New Cascaded Multilevel Inverter with Reduced Number of Switches using SPWM

(IJSRD/Vol. 3/Issue 04/2015/059)

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In phase disposition all carrier waves are in phase

shown in Fig 8. In POD the carrier waves below zero

reference line out of phase with the carrier above zero

reference line shown in Fig 9. . In APOD alternate carrier

waves are in phase and he neighboring waves are out of

phase shown in Fi 10.

Switc

h 1

Switc

h 2

Switc

h 3

Switc

h 4

Switc

h 5

Switc

h 6

Output

voltage

ON OFF OFF OFF OFF ON +Vdc

OFF ON OFF OFF OFF ON +2Vdc

OFF OFF ON OFF OFF ON +3Vdc

OFF OFF OFF ON OFF ON +4Vdc

OFF OFF OFF OFF OFF OFF 0

OFF OFF OFF ON ON OFF -Vdc

OFF OFF ON OFF ON OFF -2Vdc

OFF ON OFF OFF ON OFF -3Vdc

ON OFF OFF OFF ON OFF -4Vdc

Table 2: Switching Table for Nine Level

Fig. 5: Matlab Model For Fie Switches 7 Level

Fig. 6: Pulse Generation Circuit for Switch S1

Fig. 7: Matlab Model for Nine Level

Fig. 8: Carrier Alignment for POD pwm

Fig. 9: Carrier Alignment for PD pwm

Fig. 10: Carrier Alignment for APOD pwm

Simulation of New Cascaded Multilevel Inverter with Reduced Number of Switches using SPWM

(IJSRD/Vol. 3/Issue 04/2015/059)

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Fig. 11: Seven Level Output Waveform

Fig. 12: THD for POD Technique

Fig. 13: THD for PD Technique

Fig. 14: THD for APOD Technique

Fig. 15: Nine Level Output Waveform

Fig. 16: THD for Nine Level POD

PWM Technique POD APOD PD

Proposed 5 switch 7 level 17.94% 18.74% 18.91%

Table 3: THD Comparison

levels THD

Seven level 17.94%

Nine level

Table 4: THD Comparison for Seven and Nine Level Using

POD

VII. PULSE GENERATION CIRCUIT

The reference signal comparing with carrier generating

pulse which is then modified feeding to logic gates in order

to get the required pattern to trigger the switches at the

proper instant. For examples switches S1 needs to have a

pulse so as to obtain +Vdc and −3Vdc shown in fig 6 and

S2 requires +2Vdc and −2Vdc. S3 conducts +3Vdc and

−Vdc. Also, switches S5 and S4 conduct positive and

negative half cycles, respectively.

VIII. CONCLUSION

The 7-level MLI using just 5 switches is successfully

introduced simulating the circuitry using

MATLAB/SIMULINK and observed a clear stepped 7-level

waveform. It is found that the POD-PWM dominates all

other PWMs in the proposed configuration. Further

implementation is done for nine level and desired stepped

output with lower THD when compared to seven level is

obtaioned. Hence we can say that as number of level

increases THD level reduces.. The new design is simple in

its outlook with very few components. The new 7-level mli

topology has lower THD compared to conventional

topologies.

Simulation of New Cascaded Multilevel Inverter with Reduced Number of Switches using SPWM

(IJSRD/Vol. 3/Issue 04/2015/059)

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REFERENCES

[1] José Rodríguez, “Multilevel Inverters: A Survey of

Topologies,Controls, and Applications”, IEEE

Transactions On Industrial Electronics, Vol. 49, No.

4, August 2002

[2] T V V S Lakshmi, Noby George, Umashankar S and

Kothari D P “ Cascaded seven level inverter with

reduced number of switches “2013 International

Conference on Power, Energy and Control (ICPEC).

[3] S. Umashankar, T. S. Sreedevi, V. G. Nithya, and D.

Vijayakumar ” A New 7-Level Symmetric Multilevel

Inverter with Minimum Number of Switches”ISRN

ElectronicsVolume 2013, Article ID 476876,

[4] Jacob James Nedumgatt, D. Vijayakumar, A.

Kirubakaran, S.Umashankar “A multilevel inverter

with reduced number of switches”.