Simultaneous switching noise analysis and low-bounce buffer design

S.-J.Jou, W.-C.Cheng and Y.-T.Lin

Abstract: An accurate equation to estimate simultaneous switching noise (SSN) created by CMOS output buffers is proposed. This analytic equation includes the carrier velocity saturation effects of a short-channel MOS transistor. Simulation results show that the proposed closed-form equation estimates the SSN precisely and the error is below 10% as compared with HSPICE simulation results. Design procedures of a low-bounce tapered buffer which take SSN into consideration are also proposed. Several output buffer design examples are demonstrated to show the significant improvement of the low-bounce buffer design. A test c h p of the output buffer is implemented to operate at 400 MHz and the measurement results match the design specifications.

1 Introduction

In recent years, increasing numbers of high-density and high-speed integrated circuits are required to switch large amounts of output signals simultaneously [l]. However, simultaneous switching noise (SSN) or supply bounce that is generated along the parasitic inductance of powerlground lines ( VDdGND) has become significant [2]. The buffers that drive output pads are the main contribution to the SSN. The circuit diagram of typical output pad buffers of a chip residing in a package is shown in Fig. 1. In general, a pair of VDdGND pads is used to supply the power of sev- eral output pads. There are parasitic inductors, resistors and capacitors along the pads, bonding wires and pin- package path. Generally, the parasitic resistor is very small and can be neglected when the operational frequency of the signal is not very high. Also, a lumped capacitance model is used to model the output loading when the propagation delay time between chips is smaller than the rise and fall time of the signal. Large current fluctuations can occur in the V D D or GND leads when the number of simultaneously switching outputs (SSO) is large. So there are voltage bounces across these parasitic inductances during signal transients. Since SSN will cause bouncing of the effective supply voltage, the signal will be delayed and distorted at the outputs of the buffers. Moreover, if the peak magnitude of SSN exceeds the threshold voltage of the transistors, it can even cause malfunction of the circuits that are con- nected to the same VDD and GND pins. Therefore it is nec- essary to estimate SSN more accurately and to decrease SSN in the output buffers. A number of formulas have been proposed to predict SSN in the literature [34]. How- ever, they are too simple to accurately predict the SSN occurring in submicron CMOS circuits. We propose a new closed-form equation to predict SSN based on the alpha- power law model [7] of MOS devices.

0 IEE, 2001 IEE Proceedings online no. 20010624 D o t 10.lO49/ipcds:20010624 Paper first received 2nd November 1999 and in revised form 19th June 2001 The authors are with the Department of Electrical Engheering, National Cen- tral University, Chug-Li, Taiwan, Republic of China

Because of the large off-chip loading, in general, output buffers are usually tapered to minimise propagation delay and to provide current driving capability. Traditionally, the analysis and synthesis of a tapered buffer has focused on the issues of propagation delay, area and power consump- tion [S-1 11. However, several papers have shown the effects of the SSN in the design of buffers [12, 131. Therefore the constraints of SSN will be considered for the design of out- put buffers [14]. In this way, not only timing but also noise associated with the output buffers can be controlled within specification.

2 Analysis of SSN

The last stage of an output buffer is the main source of SSN because of its high driving capability. Therefore we focus the analysis of SSN caused by the last stage of the tapered buffer. To analyse SSN, we reduce the block dia- gram of the chippackage interface of one buffer shown in Fig. 1 to the simple circuit model shown in Fig. 2u. The input signal V, is assumed to be a pulse function with rise time tlin and fall time 9,. CVDD (Cvss) is the parasitic capacitance along the bonding wire, lead frame and pin- package for V D D (GND) line. The effects of capacitors Cvss and CvDD can be neglected in present day packaging systems [3]. Cpad is the parasitic capacitance of the output pad and C, is the lump capacitance of the pin and output loading. Fig. 3 shows the simulation results of SSN (V,) by using HSPICE with the typical value shown in Fig. 26 and V D D equals 5V. The technology used is TSMC 0 . 6 ~ CMOS single-poly triple-metal process. Fig. 3u indicates that the maximal SSN of V, is increased if the number of SSO is increased. This is because the slew rate of discharg- ing current at V,, and GND lines is increased. Note that, due to the negative feedback effect L,,, the maximal SSN is not a linear function of the number of SSO. Also, due to the increase of voltage bounce when the number of SSOs is increased, Fig. 36 shows that the signal delay time will also increase.

Conventionally, Shockley’s square-law model [ 151 is used in the analysis of MOSFET circuits owing to its simple close-form equation. However, by excluding the velocity saturation effects of submicron technology, Shockley’s model cannot regenerate the voltage+xrrent characteristics

303 IEE Proc.-Circuits Devices Sysr., Vol. 148, No. 6, December 2001

N buffers are switching

n

7-

\- -&

quiet buffers

-r

Fig. 1 Block diugrum of ch+p

quite line

I !

t,=l n s

m-

- - b

Fig. 2 Chihackuge mtefuce a Electrical model, b Typical values WJL = 300pm/0.6pm; WJL = 135pm/0.6pm

304

t a

I

5 10 15 20 25 0- ' 0

No. of switching outputs b

Fig.3 Muxwwn SSN and output signal deluy tune for dferent "bers of ssos

of short-channel MOSFET transistors. Therefore the alpha-power law MOSFET model [7] that includes velocity saturation efl'ects is used in the analysis of SSN. Using the alpha-power law model, we can write the drain current I , of MOSFET in a form like that of Shockley's model as follows:

cutoff region I D = O VGS s%h I D = kl (Viis - V&) 5 VDS

VGS > L& and VDS < V&

VGS > I& and VDS 2 V&

linear region

I D = ~ , ( K G s - %)" saturation region

(1) IEE Proc -Circurtr Devices Sysr , Vol 148, No 6. December 2001

where V,, is the gate-source voltage, VDs is the drain- source voltage, k l = IDd[VDo(VDD - V,h)a'2] and k, = ZDd (VDD - V,,)" are drivability factors. The typical value of a ranges from 1 .O to 1.3 for NMOS transistors in submicron CMOS technology. This model is based on four parame- ters: V,, (threshold voltage), a (velocity saturation index), VDo (drain saturation voltage at VGs = VDD) , and ID, (drain current at VGs = VDs = VDD). Basically, the alpha power law model is a curve-fitting model and the four parameters can be easily derived from the measurement data. This model is more accurate in the saturation region than in the linear region; that is what we want in the analysis of SSN.

input \

to1 trin tDO time

Fig.4 Dischavge wavefbrm of output hj@r

It is always the case that the last stage in the buffer drives a hgher capacitance load (C, is larger than several pF) than the predriver in the output buffer. Thus, it is true that the NMOS (PMOS) transistor stayed in their saturation region throughout most of the low-to-high (high-to-low) transition time of the input signal. Fig. 4 shows a simple diagram to describe the high-to-low situation of the output signal when the input signal changes from low to high. Furthermore, it is always the case that when the ramp sig- nal of the input reaches VDD, the SSN reaches the maxi- mum value. This is because the derivative of ZD with respect to time is largest when VGs and VDs are at their maximum value. If n buffers which share the common GND line are switched simltaneously from high to low, the discharge cur- rent flowing through L,,ss is

i ( t ) = nzd(t) = nksn(Kn(t) - V,(t) - v,,)"" (2) The switching noise V, that is built up in the node n can be written as

di(t) dt Vn(t) = Lvss-

d dt = nksnLvss-((V,n(t) - Vn(t) -

for tt L t L trtn (3) where V,,(t) is a ramp input with slew rate Sr and can be expressed as V,,(t) = Srt and t , = t,,(V,/VDD) = V,,/S,.. V,(t) has its maximum value V,,,,l,K when t equals t,.,,,, therefore

Vn(t) = nksnLvssan(Kn(t) - K ( t ) - Vtn)Qn- l

(4)

where Pl, = Vl,,/VDD and P,,,, = V,,maJVDD. Eqn. 6 indicates that V,,,, is not only dependent on ksn but also on trjn. Because (1 - P',,,,, - P,,)"~ is always smaller than one, to have simple close-form equation of V,,t7,, we take the power series of (1 - P,,,,, - P,)& and neglect the terms with order hgher than two. Finally, we have the fol- lowing equation:

(7) where A = l/2nkmL,. Theoretically, all values of a, except a, = 1 can be used in eqn. 7. As a, = 1, we can solve eqn. 3 directly and in this case it is the same as that pro- posed in [5]

t - f

Vn(t) = nksnLvssSr 1 - r - 7 L k - n L : . q ) (8)

O Y 1 I I I I a

I

0 5 20 25

b Comparkon of estimated maxi" simultunem witching no& by

lo sso l5

Fig.5 using dijferent methds -+- HSPICE - -0- - Vaidyanath [4] -a-- ours - -0- - Vemuru [SI - -A- - Senthinathan [3] a V,, = 3.3V; b V,, = 2V

IEE Proc.-Circuits Devices Syst., Vol. 148, No. 6, December 2001 305

Table 1: Comparisons of average error and RMS error

Supply voltage 5V 3.3v 2.5V 2 v

Average (%) RMS (%) Average (%) RMS (%) Average (%) RMS (%) Average (%) RMS (%)

183.22 Senthinathan [3] 10.1 1 53.13 18.82 95.61 28.25

Vaidyanath [41 7.40 88.20 5.41 29.34 13.66 69.11 21.14 109.79

40.54

Ours 5.38 34.49 3.58 18.32 1.27 11.02 5.47 31.53

145.44 35.42

36.00 3.83 Vemuru [51 5.32 29.63 6.35 38.25 3.93

In the same manner, the SSN in node P (V,( f ) ) when the output voltage changes from low to high can be derived. The estimation of V,,,,, of the circuit shown in Fig. 2b is shown in Fig. 5 and Table 1. Senthmathan [3] and Vaidy- anath [4] use Shockley's model. Although Vemuru [5] also uses the alpha-power law model, it assumed that a, = 1 in the manipulation of di(t)/dt in eqn. 3. For the case that V D D equals 5V, a, equals 1.0658, thus Vemuru and our- selves have comparable results. However, for the cases where V D D equals 3.3, 2.5 and 2V, a, is higher than 1 and our results are much more accurate than that of Vemuru. Therefore it is obvious that our SSN equation is more gen- eral and precise as compared with others. This is particu- larly true for short-channel MOSFET transistors. The average error as compared with HSPICE is below 10%. According to eqn. 7, once the design specifications of n, L,, k,, and t,,, are known, maximum SSN can be analyti- cally calculated. However, the delay time of output buffer also depends on k,, and trm. So eqn. 7 must be used with a delay time equation and we can design an output buffer with both timing and SSN specifications.

3

To predict the timing performance of the output buffer we derive the rise time trout and fall time trout, based on the alpha-power law model [7]. Referring to Fig. 4, we sepa- rate the fall time to three regions: tol - t,,,, frIn - too and tDO - to9. The rise and fall time can be expressed as follows (see the Appendix for the detailed derivation):

Delay time estimation of output buffer

+ (e - 1) * trin

+ (4 l + c U - 1) *t f zn

O.~VDD k s p * VZD ( 1 - I&.) @ * In ___ VDO

(10) -(>L * VD, +

The comparisons of eqns. 9 and 10 with HSPICE simula- tion results are shown in Table 2. Thus, these equations are withn 10O/0 error in estimating the rise and fall times of the output buffer. In the following Section we use them in the design of i1 tapered buffer.

Table 2: Comparisons of derived tmUr and trout with HSPICE simulation results

HSPICE simulation Eqns. 9 and 10 Error (%) c~ (PF) trout/tfout (ns) trouthout (ns)

5 0.63/0.60 0.63/0.63 0.0/5.0

7 0.7210.70 0.75/0.75 4.0/6.6

9 0.83/0.80 0.88/0.88 5.619.0

1.00/0.99 8.0D.O 11

13 1.0311.03 1 .I 2/1 .I 2 8.0/8.0

15 1 .I 6/1 .I 5 1.2411.25 6.4/8.0

VDD= 3V, trin/tfin = 1 ns/l ns, W, = 600ym and W, = 200ym

0.9210.92

4 Tapered buffer design considering SSN effects

Suppose we need a tapered buffer to drive a capacitance load C, = 20pF, with V D D = 5V, and the parasitic induct- ance Lvdd = I&, = 10nH. The design based on the equa- tion (split-capacitance load model: SPCL [9]) that only minimises signal propagation delay and does not consider SSN caused by parasitic inductance will have a channel width of the last stage buffer of 2893/1033pm (PMOS/ NMOS). The HSPICE simulation results with and without Lvdd and L , included are shown in Figs. 6a and b. It is very clear that the output waveform is deformed and delay time td and rise (fall) time are aggravated because of the parasitic effecl. Thus neglecting the SSN during the design of an output buffer can-cause an unacceptable result.

According to eqn. 7 we can express ks, as

By merging eqns. 9 and 11 we have

t f o u t = trin (1 - Rn)

306

i

IEE Proc.-CircuitA Devices Syst., Vol. 148. No. 6, December 2001

CL * (VDD - VDO) * n * Lvss

tapered slew-

stage stage

input signal +- prebuffer - controlled -

CL * VDO * n * LVSS * a o1

* ~0"; ' * ( I -vn,ma,:-En) o.lvDD 1 - *In ~ *-

Qn,maz * (1 - Qtn) VDO tinr

(12) trout can be derived by the same procedures and has a simi- lar form. There are three parameters in eqn. 12: tfout, tri, and V,,,,,. Therefore there are two ways to use eqn. 12. The first is to assign a desired Vn,,u.JV,,M,y value and a program is used to obtain a minimum tfou~trout under V,,,d V,,mu,y constrains and obtain a reasonable trinltfi" by solving this nonlinear equation. The other way is to assign a desired tfou&,t value and a program is used to obtain a minimum Vn+JVp,Mx and a reasonable t,/t,, of input signal. Once triJtlin and Vn,,J V,,,, are known, eqn. 1 I can be used to obtain k,ynlksp (hence WIL of the MOS device). Thus, to design a low-bounce output buffer, a possible structure of the output buffer is shown in Fig. 7. In the bouncing constrained stage A, the procedures described are carried out to design WIL of the PMOS and NMOS in this stage. A simple flowchart of an analysis and synthesis program to automate the design process is shown

SSN constrained

stage _____

time, ns a

time, ns b

Fig, 6 a Without parasitic inductance b With parasitic inductance V, and VOut graphs:

Simuluted output wavefom of output tqwed hffw

Current graph ~ ~ ( V D D )

I ( "ss) _ _ _ _ ~ Vour vin _ _ _ _

in Fig. 8. This program allows the user to assign desired V,,,,.JV,,,ux (method 1) or tfoU/tro,, (method 2) value. The requirement of trin/tfi, of stage A is passed to stage B. Because the MOSFET WIL in stage A is determined, the loading of stage B is known, the WIL of this stage is designed so that the required slew rate can be achieved. Finally, in stage C, traditional minimum delay calculation equations based on the SPCL model [9] are used to design tapered buffers so that they have a minimum delay time and have the capability to drive stage B. Thus, we use stage A and stage B to control the required SSN and output transient time and stage C to minimise the delay of driving stage B. The design procedures have been implemented in

LVDD T /L

stage C stage B

Lvss

staie A

Fig. 7 Architecture ojlow-bounce bujjer

input desired Gout, trout

set V , max=Vn, max'0

Vn, "=V,, ,,+0.05V calculate t,,

calculate trin Use Newton-Raphson Use Newton-Raphson to solve eqn.12

+nJ e' rin>O and trin>Go no+

calculate tfin Use Newton-Raphson

Use eqn. 11 to obtain size of

PMOS and NMOS

end L-.-/

Fig. 8 Syntheskflo\vchart ofstuge A

IEE Proc.-Circuits Devices Syst. , Vol. 148, No. 6, December 2001 307

an automated buffer synthesis program. Raphael [19], 5 Design and implementation examples which is a 3-D RLC analysis system, is used to get the parasitic C and L, given the structure of the package inter- face. The SPICE netlist file is then generated for the buffer circuit shown in Fig. 7.

Tables 3-6 show some design examples by varying the out- put loading, the numbers of SSO, the parasitic inductance value, and rise (fall) time of the output waveform. The

Table 3: Comparison of SSN and rise time and fall time with HSPICE simulation results for different output loading

Power Estimated Simulated WdWn of Error (%) of Vn,max dissipation

(mW) troudtfout (ns) troutlrfout (ns) stage A (w) rrout4out V,,max

C, = 8pF O . M . 4 3 0.48-0.58 0.9510.80 0.8910.75 54412 1 0 6.316.2 5.80

CL= 12pF 0.504.44 0.554.64 1.1510.95 1.0310.85 6911284 10.0110.0 8.02

CL= 16pF 0.524.41 0.55-0.61 1.2011.05 1.1010.95 8741325 9.1110.5 10.80

C,= 18pF 0.504.43 0.584.61 1.3011.10 1 .I 611 .OO 8651370 12.0110.0 11.61

CL = 20pF 0.48-0.43 0.59-4.67 1.3511.20 1.2211.08 9911343 10.7111.1 13.03 VDD=~V, n= 1, LVDD= Lvss= IOnH, Vn,,,= Vp,,ax=0.5V

Table 4: Comparisons of SSN, rise and fall times with HSPICE simulation results for varying number of output drivers

Estimated Simulated WdWn of Error (%) of troutltfout (ns) rroutltfout (ns) stage A ( ~ m ) troutltfout

Vp,max Vn,max

n = 2 0.504.42 0.56-0.60 1.4511.25 1.3511.15 4951171 6.818.0

n = 4 0.494.43 0.534.64 2.0511.75 2.0011.57 3511125 2.411 0.0

n = 6 0.514.43 0.49-0.70 2.5012.10 2.3611.98 297L112 5.615.7

n = 8 0.48-0.40 0.55-0.66 2.9012.45 2.8012.39 247192 3.412.4

n = 10 0.474.40 0.604.75 3.2512.70 3.2912.52 2 1 8/90 1.216.6

VDD=~V, C,= IOpF, LvDD= Lvss= IOnH, V,,,,= Vp,max=0.5V

Table 5: Comparisons of SSN, rise and fall times with HSPICE simulation results for different parasitic inductance value

LVDD = 15 nH 0.49-0.37 0.424.46 1.2510.65 1.1910.60 59431 1 4.817.6 Lvss = 5 nH

LvDD = 13 nH 0.45-4.40 0.48-0.54 1.2010.75 1.13l0.68 5491279 5.819.3 LVSS = 7 nH

LVDD =I 1 nH 0.49-0.43 0 .54 .58 1 .I 010.85 1.0010.77 6041246 9.019.4 Lvss = 9 nH

LvDD= 9nH 0.45-0.42 0.54-4.65 1.0010.90 0.9210.80 6561261 8.011 1 .I Lvss = 11 nH

LVDD = 7 nH 0.404.41 0.53-0.58 0.9011 .OO 0.8310.90 703121 8 7.7110.0 Lvss= 13nH

LVDD= 5nH 0.34-4.41 0.51-0.65 0.7511.05 0.7010.97 8641225 6.6l7.6 Lvss= 15nH

Table 6: Comparisons of SSN, rise and fall time with HSPICE simulation results for varying rise and fall time of output buffer

Estimated Estimated Simulated WdWn of Error (%) of troutItfout (ns) v ~ m x

1.011 .o 0.51-0.46 0.45-0.46 0.5510.40 0.9110.87 6771200 9.011 3.0

1 .2/1.2 0.374.37 0.334.27 0.4010.30 1.0811 .I 7 50711 50 10.012.5

1.411.4 0.24-4.25 0 .234.24 0.3010.20 1.3511.34 41 011 35 3.514.2

1.611.6 0.16-0.20 0.164.17 0.2510.15 1.6311.56 33011 22 1.812.5

1.811.8 0.12-4.16 0.16--0.11 0.20/0.15 1.8211.89 285188 1.115.0

2.012.0 0.104.13 0.104.10 0.2010.15 2.1 712.1 3 237I75 8.516.5

Vp,maxlVn,max (VI troutltfout (ns) stage A (pm) troutltfout Vn,max

VDD= 3v, n= 1, = Lvss = IOnH, C, = 1OpF

308 IEE Proc.-Circuits Devices Sysl., Vol. 148, No. 6, December 2001

Table 7: Performance comparisons of tapered buffers designed with SPCL and our three-stage structure

Delay time

output (ns) Total power Stage A (mw) Vmax Vn,max WplWn (pm)

trout (ns) tfout (ns) input to

1.35 1.40 387211530

0.77 0.76 14291372

SPCL 12.85 First ring = 0.47 First ring = 0.64 2.39

Ours trooJtfooot constraint 8.77 0.67 0.68 2.09

Ours v,,, v,,,, (0.5V) constraint 7.19 0.93 0.82 2.30 0.45 0.51 599/219 V,,g=BV, CL=lOpF,Lv~~=Lvss=lOnH

errors for these cases as compared with HSPICE simula- tion results are about 10Yn.

The design results are listed in Table 7 for the case of SPCL, SSN constrained (method 1) and output rise- and fall-time constrained (method 2) cases. The tIout and tf,,, of the SPCL cases are measured by the first transient of signal and ignoring the successive ringing. In method 2, we set trout and qOut roughly equal that of SPCL. The design results show that our design has much smaller V,,l,,, and Vp,mu, and the MOSFET size used in stage A is only 33% of the SPCL case. In method 1, the V,,,,, and V,,,,,,, are set to be 0.5V and the size of MOSFET used in stage A is only 15% of the SPCL case with roughly the same total delay time.

Several SSN reduction techniques have been proposed [13, 1&18]. These can significantly reduce SSN when they are applied to the traditional buffers that are designed with- out considering SSN effects. For example, a well-known architecture of a weighted and distributed buffer is shown in Fig. 9 [13]. The switching time of PMOS and NMOS transistors are controlled individually. When the input sig- nal is changed, PMOS1 or NMOS1 are switched first, and with some delay PMOS2 or NMOS2 are then switched. By applying this method to our three-stage low-bounce buffer, the PMOS (NMOS) of stage A is divided equally into PMOS1 and PMOS2 (NMOS1 and NMOS2).

Fig. 10 shows the simulation results of the combined architecture and our original three-stage output buffer. The combined architecture has little improvement in SSN. Ths is because our buffer architecture has already taken the SSN into consideration. Thus, extra effort can have little improvement on SSN. The simulation results of this exam- ple together with other methods are given in Table 8. Usu- ally, due to extra control logic required to implement these schemes, the power and delay time are increased.

time, ns Fig. 10 weighted and distributed method (i) ours (ii) ours with weighted and distributed method

Sinzuhtwn results of’ output bu&r of our &sign cuui inchding

Test chips for the proposed tapered buffer designs are implemented by using TSMC single-poly triple-metal 0 . 6 ~ CMOS process. In this design example, Vn,p,,,, is set to be 0.5V and can operate at 400MHz when VDD is 3V. Fig. 11 shows the layout of this low-bounce output buffer. There are two inverters in stage C. In the design of this low-bounce output buffer the parasitic inductance of power and ground path is estimated to be 7nH (we choose the pad with shortest bonding wire for the VDD and GND).

Table 8: Summary of HSPICE simulation results with and without techniques for reducing simultaneous switching noise

~ _ _ _ _

Ours Ours with weight and Ours with charge- Ours with controlled Ours with adaptive distributed [I31 sharing (1OpF) [I71 slew rate [I81 method [I91

Total power (mW) 8.77 11.26 9.21 11.83 17.53

trout(n4 0.67 0.84 0.71 0.85 0.63

trout (ns) 0.68 0.90 0.69 0.90 0.94 Delay time input to output (ns) 2.09 2.20 3.45 3.25 3.19

Vp,max (V) 0.77 0.75 0.70 0.75 0.74

Vn,max (V) 0.76 0.69 0.68 0.55 0.54 Total area ( Wx L) (pm2) 1221.54 1291.86 1382.88 2208.78 3627.36

IEE Proc -Oicur t~ Device7 SyJt, Vol 148, No 6, December 2001 309

Fig. 12 is the measured output waveform of a 400MHz signal. It is seen that Vp,, is only around 2.2V. This is because the overall loading capacitance in this measure- ment setup is estimated to be 5pF, which is larger than 3pF that we assumed in the design process. The measured VDD and ground bouncing waveforms by probing VDD and GND pads are shown in Fig. 13. There is ten times attenu- ation in the probe so the V,,,, and V,,,, is around OSV. The measurement results show that the design constraints of SSN is well within the design specifications.

Fig. 11 Luyout dbgtm of4ooMHz three-stuge tupered bufler

59 acqs c------T-------l

f +

I I

I

t 1 OOmV -; M 2.00ns ChT 1.34V

Fig. 12 Cl: 398.94MHz

Measured output wuvefom of output bufler

6 Conclusions

An analysis of SSN created by output buffer in packaged CMOS chip has been presented. By using the alpha-power law model, a new closed-form expression was developed for SSN caused by output buffers. The simulation results showed that it is more accurate as compared with other existing formulas and the error is within 10% as compared with HSPICE simulation results. By using the derived SSN equation and the rise and fall time equations of the output buffer, we can estimate the timing and SSN performance of the output buffer. Furthermore, a three-stage low-bounce output buffer structure and their design procedures are pro- vided. The synthesis results show that the design results are about 10% in error as compared with HSPICE simulation results. Implementation results show that the proposed low-bounce output buffer and design procedures provide a better solution when designing a tapered buffer.

310

t 1 M2.00ns Chlf 294V i , , , , b

Fig. 13 Memired bounce noise ~ v u v e f o m a VDD C1: 416.33MHz b GND C1: 460.30MHz

7 Acknowledgments

This work was supported by the National Science Council, Republic of China under grant NSC-88-2215-E-008-024. The chip was fabricated through the chip implementation centre of the National Science Council.

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9

The case shown in Fig. 4 is considered in the derivation. Region I: to, - t; NMOS is operated in the saturation region and the behaviour of output voltage Vu can be described as

Appendix: Derivation of delay formula

a,,+l 1 V o ( t ) = -

t T i n ID0 * - * (2- - Gn) cL(l - E.) Q + 1 t r in

+ Knit ( 1 4 ) where Knit is a constant. When t equals t,, V, will equal VDD and Knit is V D D . Thus

According to the definition of to, we have

Finally

trzn - to1 = trzn *

( 1 7 ) Region II: trin - tDp. The input is at a constant voltage VDD and the n-channel NMOS is operated in saturation region. Therefore the output load C, is discharged by a constant current IDo

t r 5 t 5 to0 (18) dV0 ( t ) CL - = -Io0

d t When t equals trin, Vo(t) must satisfy both eqns. 17 and 18, so the solution is

Gn + a! * t , ( 1 9 ) 1 IDO CL ( l + a Vo(t) = V D O - - * t - ~

Because too is the time when V, equals Voo so

Finally

Region III: to0 - top' The input is a constant voltage VDD but NMOS is operated in the linear region. Thus

The solution of V,(t) is then - l*IDO * ( t -tD" 1

Vo(t) = V D o * e CL*"DO ( 2 3 )

0 . 1 V D D = VDO * e c ~ * v ~ u ( 2 4 )

According to the definition of tog, we have - l*ID"*( tog- tDo)

Thus

Combining eqns. 17, 21 and 25, we have the fall time of the output buffers

The rise time of the output buffers can be derived in the same manner.

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