ISD4004 SERIES
Publication Release Date: March 2017
- 1 - Revision 1.32
ISD4004 SERIES
SINGLE-CHIP, MULTIPLE-MESSAGES
VOICE RECORD/PLAYBACK DEVICES
8-, 10-, 12-, AND 16-MINUTE DURATION
ISD4004 SERIES
Publication Release Date: March 2017
- 2 - Revision 1.32
1. GENERAL DESCRIPTION ............................................................................................................... 3
2. FEATURES ....................................................................................................................................... 4
3. BLOCK DIAGRAM ............................................................................................................................ 5
4. PIN CONFIGURATION ..................................................................................................................... 6
5. PIN DESCRIPTION ........................................................................................................................... 7
6. FUNCTIONAL DESCRIPTION ....................................................................................................... 12
6.1. Detailed Description ................................................................................................................ 12
6.2. Serial Peripheral Interface (SPI) Description .......................................................................... 13
6.2.1 OPCODES ....................................................................................................................... 14
6.2.2 SPI Diagrams ................................................................................................................... 15
6.2.3 SPI Control and Output Registers .................................................................................... 16
7. TIMING DIAGRAMS ....................................................................................................................... 18
8. ABSOLUTE MAXIMUM RATINGS.................................................................................................. 20
8.1. Operating Conditions............................................................................................................... 21
9. ELECTRICAL CHARACTERISTICS ............................................................................................... 22
9.1. Parameters For Packaged Parts ............................................................................................. 22
9.2. Parameters For Die ................................................................................................................. 25
9.3. SPI AC Parameters ................................................................................................................. 26
10. TYPICAL APPLICATION CIRCUIT ................................................................................................. 27
11. PACKAGING AND DIE INFORMATION ......................................................................................... 30
11.1. 28-Lead 300-Mil Plastic Small Outline IC (SOIC) ................................................................ 30
11.2. 28-Lead 600-Mil Plastic Dual Inline Package (PDIP) .......................................................... 31
11.3. Die Information .................................................................................................................... 32
12. ORDERING INFORMATION .......................................................................................................... 34
13. VERSION HISTORY ....................................................................................................................... 35
ISD4004 SERIES
Publication Release Date: March 2017
- 3 - Revision 1.32
1. GENERAL DESCRIPTION
The ISD4004 ChipCorder® series provides high-quality, 3-volt, single-chip record/playback solutions for
8- to 16-minute messaging applications ideally for cellular phones and other portable products. The CMOS-based devices include an on-chip oscillator, anti-aliasing filter, smoothing filter, AutoMute
®
feature, audio amplifier, and high density multilevel Flash memory array. The ISD4004 series is designed to be used in a microprocessor- or microcontroller-based system. Address and control are accomplished through a Serial Peripheral Interface (SPI) or Microwire Serial Interface to minimize pin count.
Recordings are stored into the on-chip Flash memory cells, providing zero-power message storage. This unique single-chip solution utilizes Nuvoton’s patented multilevel storage technology. Voice and audio signals are directly stored onto memory array in their natural form, providing high-quality voice reproduction.
ISD4004 SERIES
Publication Release Date: March 2017
- 4 - Revision 1.32
2. FEATURES
Single-chip voice record/playback solution
Single 3 volt supply
Low-power consumption
Operating current:
- ICC_Play = 15 mA (typical)
- ICC_Rec = 25 mA (typical)
Standby current:
- ICC_Standby = 1 µA (typical)
Duration: 8, 10, 12, and 16 minutes
High-quality, natural voice/audio reproduction
AutoMute feature provides background noise attenuation
No algorithm development required
Microcontroller SPI or Microwire™ Serial Interface
Fully addressable to handle multiple messages
Non-volatile message storage
100K record cycles (typical)
100-year message retention (typical)
On-chip oscillator
Power-down feature to reduce power consumption
Available in die, PDIP, and SOIC
Packaged type: Lead-Free
Temperature:
- Commercial (die): 0°C to +50°C
- Commercial (packaged units): 0°C to +70°C
- Industrial (packaged units): -40°C to +85°C
ISD4004 SERIES
Publication Release Date: March 2017
- 5 - Revision 1.32
3. BLOCK DIAGRAM
Internal Clock Timing
Sampling Clock
3,840K Cell
Nonvolatile
Multilevel Storage
Array
Analog Transceivers
Deco
de
rs
Power Conditioning
5-Pole Active
Antialiasing Filter
5-Pole Active
Smoothing Filter
Amp AUDOUT
VCCA
VSSA
VSSA
VSSA
XCLK
AmpANA IN-
ANA IN+
AM CAP
Device Control
SCLK SS MOSI MISO INT RAC
AutoMuteTM
Feature
VSSD
VCCD
ISD4004 SERIES
Publication Release Date: March 2017
- 6 - Revision 1.32
4. PIN CONFIGURATION
SOIC / PDIP
SS
MOSI
MISO
VSSD
NC
NC
NC
NC
NC
NC
VSSA
VSSA
AUD OUT
AM CAP
VCCD
XCLK
INT
RAC
VSSA
NC
NC
NC
NC
VCCA
ANA IN+
ANA IN-
NC
SCLK
ISD4004
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ISD4004
NC
NCV
CCA
ANA IN+
ANA IN-
NC
AM CAP
NC
AUD OUT
VSSA
VSSA
NC
NC
NC
VSSA
RAC
NC
NC
INT
XCLKV
CCD
SCLK
SS
MOSI
MISOV
SSD
NC
NC
TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ISD4004 SERIES
Publication Release Date: March 2017
- 7 - Revision 1.32
5. PIN DESCRIPTION
PIN NAME FUNCTION
SOIC /
PDIP
SS 1 Slave Select: This input, when LOW, will select the
ISD4004 device.
MOSI 2 Master Out Slave IN: This is the serial input to the ISD4004 device when it is configured as slave. The master microcontroller places data on the MOSI line one half-cycle before the rising edge of SCLK for clocking into the device.
MISO 3 Master In Slave Out: This is the serial output of the ISD4004 device. This output goes into a high-impedance state if the device is not selected.
VSSA / VSSD 11, 12, 23 / 4
Ground: The ISD4004 series utilizes separate analog and digital ground busses. The analog ground (VSSA) pins should be tied together as close as possible and connected through a low-impedance path to power supply ground. The digital ground (VSSD) pin should be connected through a separate low-impedance path to power supply ground. These ground paths should be large enough to ensure that the impedance between the VSSA pins and the VSSD pin is less than 3 Ω. The backside of the die is connected to VSS through the substrate. For chip-on-board design, the die attach area must be connected to VSS or left floating.
NC 5-10, 15, 19-22
Not connected
AUD OUT [1]
13 Audio Output: This pin provides an audio output of the stored data and is recommended be AC coupled. It is capable of driving a 5 KΩ impedance REXT.
[1]
The AUD OUT pin is always at 1.2 volts when the device is powered up. When in playback, the output buffer connected to this pin can drive a load as small as 5 KΩ. When in record, a built-in resistor connects AUD OUT to the internal 1.2-volt analog ground supply. This resistor is approximately 850 KΩ, but will vary somewhat according to the sample rate of the device. This relatively high impedance allows this pin to be connected to an audio bus without loading it down.
ISD4004 SERIES
Publication Release Date: March 2017
- 8 - Revision 1.32
PIN NAME FUNCTION
SOIC /
PDIP
AM CAP 14 AutoMute™ Feature: The AutoMute feature only applies for playback operation and helps to minimize noise (with 6 dB of attenuation) when there is no signal (i.e. during periods of silence). A 1 µF capacitor to ground is recommended to connect to the AM CAP pin.
This capacitor becomes a part of an internal peak detector which senses the signal amplitude. This peak level is compared to an internally set threshold to determine the AutoMute trip point. For large signals, the AutoMute attenuation is set to 0 dB automatically but 6 dB of attenuation occurs for silence. The 1 µF capacitor also affects the rate at which the AutoMute feature changes with the signal amplitude (or the attack time).
The AutoMute feature can be disabled by connecting the AM CAP pin directly to VCCA..
ANA IN- 16 Inverting Analog Input: This pin transfers the signal into the device during recording via differential-input mode.
In this differential-input mode, a 16 mVp-p maximum input signal should be capacitively coupled to ANA IN- for optimal signal quality, as shown in Figure 1: ANA IN Modes. This capacitor value should be equal to that used on ANA IN+ pin. The input impedance at ANA IN- is normally 56 KΩ.
In the single-ended mode, ANA IN- should be capacitively coupled to VSSA through a capacitor equal to that used on the ANA IN+ pin.
ANA IN+ 17 Non-Inverting Analog Input: This pin is the non-inverting analog input that transfers the signal to the device for recording. The analog input amplifier can be driven single ended or differentially.
In the single-ended input mode, a 32 mVp-p (peak-to-peak) maximum signal should be capacitively connected to this pin for optimal signal quality. The external capacitor associated with ANA IN+ together with the 3 KΩ input impedance are selected to give cutoff at the low frequency end of the voice passband.
In the differential-input mode, the maximum input signal at ANA IN+ should be 16 mVp-p capacitively coupled for optimal signal quality. The circuit connections for the two modes are shown in Figure 1.
ISD4004 SERIES
Publication Release Date: March 2017
- 9 - Revision 1.32
PIN NAME FUNCTION
SOIC /
PDIP
VCCA / VCCD 18 / 27 Supply Voltage: To minimize noises, the analog and digital circuits in the ISD4004 devices use separate power busses. These +3V busses are brought out to separate pins and should be tied together as close to the supply as possible. In addition, these supplies should be decoupled as close to the package as possible.
RAC 24 Row Address Clock: This is an open drain output that provides the signal of a ROW with a 200 ms period for 8 KHz sampling frequency. (This represents a single row of memory.) This signal stays HIGH for 175 ms and stays LOW for 25 ms when it reaches the end of a row.
The RAC pin stays HIGH for 109.37 µsec and stays LOW for 15.63 µsec in Message Cueing mode (see Message Cueing section for detailed description). Refer to the AC Parameters table for RAC timing information at other sample rates.
When a record command is first initiated, the RAC pin remains HIGH for an extra TRACL period. This is due to the need of loading the internal sample and hold circuits in the device. This pin can be used for message management techniques.
A pull-up resistor is required to connect this pin to other device.
INT 25 Interrupt: This is an open drain output pin. This pin goes
LOW and stays LOW when an Overflow (OVF) or End of Message (EOM) marker is detected. Each operation that ends with an EOM or OVF will generate an interrupt. The interrupt will be cleared the next time an SPI cycle is initiated. The interrupt status can also be read by an RINT instruction.
A pull-up resistor is required to connect this pin to other device.
Overflow Flag (OVF) – The Overflow flag indicates that the end of memory has been reached during a record or playback operation.
End of Message (EOM) – The End of Message flag is set only during playback operation when an EOM is found. There are eight EOM flag position options per row.
ISD4004 SERIES
Publication Release Date: March 2017
- 10 - Revision 1.32
PIN NAME FUNCTION
SOIC /
PDIP
XCLK 26 External Clock Input: The ISD4004 series is configured at the factory with an internal sampling clock frequency
centered to 1 percent of specification. The frequency is
then maintained to a variation of 2.25 percent over the entire commercial temperature and operating voltage ranges. The internal clock has a –6/+4 percent tolerance over the industrial temperature and voltage ranges. A regulated power supply is recommended for industrial temperature range parts. If greater precision is required, the device can be clocked through the XCLK pin as follows:
Part Number Sample Rate Required Clock
ISD4004-08M 8.0 kHz 1024 kHz
ISD4004-10M 6.4 kHz 819.2 kHz
ISD4004-12M 5.3 kHz 682.7 kHz
ISD4004-16M 4.0 kHz 512 kHz
These recommended clock rates should not be varied because the anti-aliasing and smoothing filters are fixed. Otherwise, aliasing problems can occur if the sample rate differs from the one recommended. The duty cycle on the input clock is not critical, as the clock is immediately divided
by two. If the XCLK is not used, this input must be
connected to ground.
SCLK 28 Serial Clock: This is the input clock to the ISD4004 device. It is generated by the master device (typically microcontoller) and is used to synchronize the data transfer in and out of the device through the MOSI and MISO lines, respectively. Data is latched into the ISD4004 on the rising edge of SCLK and shifted out of the device on the falling edge of SCLK.
ISD4004 SERIES
Publication Release Date: March 2017
- 11 - Revision 1.32
32m Vp-pSignal
0.1 F
0.1 F
ANA IN+
ANA IN-
3K
3K
53K
53K
1.2V
To Filter
Internal to the device
-
+
Single-Ended Input Mode
16m Vp-pInput Signal
0.1 F
0.1 F
ANA IN+
ANA IN-
3K
3K
53K
53K
1.2V
To Filter
Internal to the device
-
+
Differential Input Mode
16m Vp-p
180°
Input Signal
FIGURE 1: ISD4004 SERIES ANA IN MODES
RAC
TRAC
(200 ms)
25 msT
RACL
FIGURE 2: RAC TIMING WAVEFORM DURING NORMAL OPERATION
(example of 8KHz sampling rate)
ISD4004 SERIES
Publication Release Date: March 2017
- 12 - Revision 1.32
6. FUNCTIONAL DESCRIPTION
6.1. DETAILED DESCRIPTION
Audio Quality
The Nuvoton’s ISD4004 ChipCorder® series is offered at 8.0, 6.4, 5.3 and 4.0 kHz sampling
frequencies, allowing the user a choice of speech quality options. Increasing the sampling frequency will produce better sound quality, but affects duration. Please refer to Table 1: Product Summary for details.
Analog speech samples are stored directly into on-chip non-volatile memory without the digitization and compression associated with other solutions. Direct analog storage provides higher quality reproduction of voice, music, tones, and sound effects than other solid-state solutions.
Duration
The ISD4004 Series is a single-chip solution with 8-, 10-, 12-, and 16-minute duration.
TABLE 1: PRODUCT SUMMARY OF ISD4004 SERIES
Part Number Duration
(Minutes)
Sample Rate
(kHz)
Typical Filter Pass
Band (kHz) *
ISD4004-08M 8 8.0 3.4
ISD4004-10M 10 6.4 2.7
ISD4004-12M 12 5.3 2.3
ISD4004-16M 16 4.0 1.7
* This is the –3dB point. This parameter is not checked during production testing and may vary due to process variations and other factors. Therefore, the customer should not rely upon this value for testing purposes.
Flash Storage
The ISD4004 series utilizes on-chip Flash memory, providing zero-power message storage. The message is retained for up to 100 years typically without power. In addition, the device can be re-recorded typically over 100,000 times.
Memory Architecture
The ISD4004 series contains a total of 3,840K Flash memory cells, which is organized as 2,400 rows of 1,600 cells each. The address bits (A0-A15) are used to access various rows for multiple messages of different durations.
ISD4004 SERIES
Publication Release Date: March 2017
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Microcontroller Interface
A four-wire (SCLK, MOSI, MISO & SS ) SPI interface is provided for controlling and addressing
functions. The ISD4004 is configured to operate as a peripheral slave device, with a microcontroller-based SPI bus interface. Read and write operations are controlled through this SPI interface. An
interrupt signal ( INT ) and internal read only Status Register are provided for handshake purposes.
Programming
The ISD4004 series is also ideal for playback-only applications, where single- or multiple-messages playback is controlled through the SPI port. Once the desired message configuration is created, duplicates can easily be generated via a programmer.
6.2. SERIAL PERIPHERAL INTERFACE (SPI) DESCRIPTION
The ISD4004 series operates via SPI serial interface with the following protocol.
First, the data transfer protocol assumes that the microcontroller’s SPI shift registers are clocked on the falling edge of the SCLK. However, for the ISD4004, the protocols are as follows:
1. All serial data transfers begin with the falling edge of SS pin.
2. SS is held LOW during all serial communications and held HIGH between instructions.
3. Data is clocked in on the rising edge of the SCLK signal and clocked out on the falling edge of the SCLK signal, with LSB first.
4. Playback and record operations are initiated when the device is enabled by asserting the SS
pin LOW, shifting in an opcode and an address data to the ISD4004 device (refer to the Opcode Summary in the following page).
5. The opcodes contain <16 address bits> and <8 control bits>.
6. Each operation that ends with an EOM or Overflow will generate an interrupt. The Interrupt will be cleared the next time a SPI cycle is initiated.
7. As Interrupt data is shifted out of the MISO pin, while address and control data are simultaneously shifted into the MOSI pin. Care should be taken such that the data shifted in is compatible with current system operation. Because it is possible to read an interrupt data and start a new operation within the same SPI cycle.
8. An operation begins with the RUN bit set and ends with the RUN bit reset.
9. All operations begin after the rising edge of SS .
ISD4004 SERIES
Publication Release Date: March 2017
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6.2.1 OPCODES
The available Opcodes are summarized as follows:
TABLE 2: OPCODE SUMMARY
Instructions
OpCodes
Descriptions
Address (16 bits)
<A0 – A15>
Control bits (8 bits)
XXX C0 C1 C2 C3 C4
POWERUP <XXX……XXX> XXX 0 0 1 0 0 Power-Up: Device will be ready for an operation after TPUD.
SETPLAY <A0 – A15> XXX 0 0 1 1 1 Initiates playback from address <A0-A15>.
PLAY <XXX……XXX> XXX 0 1 1 1 1 Playback from the current address (until EOM or OVF).
SETREC <A0 – A15> XXX 0 0 1 0 1 Initiates a record operation from address <A0-A15>.
REC <XXX……XXX> XXX 0 1 1 0 1 Records from current address until OVF is reached or Stop command is sent.
SETMC <A0 – A15> XXX 1 0 1 1 1 Initiates Message Cueing (MC) from address <A0-A15>.
MC [1]
<XXX……XXX> XXX 1 1 1 1 1 Performs a Message Cueing from current location. Proceeds to the end of message (EOM) or enters OVF condition if no more messages are present.
STOP <XXX……XXX> XXX 0 1 1 X 0 Stops the current operation.
STOPPWRDN <XXX……XXX> XXX X 1 0 X 0 Stops the current operation and enters into standby (power-down) mode.
RINT [2]
<XXX……XXX> XXX 0 1 1 X 0 Read Interrupt status bits: Overflow and EOM.
Notes:
C0 = Message cueing
C1 = Ignore address bit
C2 = Master power control
C3 = Record or playback operation
C4 = Enable or disable an operation
[1]
Message Cueing can be selected only at the beginning of a playback operation.
[2] As the Interrupt data is shifted out of the ISD4004, control and address data are being shifted in. Care should be taken such that the data shifted in is compatible with current system operation. It is possible to read interrupt data and start a new operation at the same time. See Figures 5 - 8 for references.
ISD4004 SERIES
Publication Release Date: March 2017
- 15 - Revision 1.32
6.2.2 SPI Diagrams
Output Shift RegisterMISO
MOSI
Row Counter
A0-A15
P0-P15
(Loaded to Row Counter
only if IAB = 0)
OVF EOM
LSB
P0 ... P15
Input Shift Register
Select Logic
X X X
LSB
A0A15
C
0
C
4
FIGURE 3: SPI INTERFACE SIMPLIFIED BLOCK DIAGRAM
The following diagram describes the SPI port and the control bits associated with it.
MISO OVF EOM P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 0 0 0 0 0 0
LSB MSB
MOSIA0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
LSB MSB
C0 C1 C2 C3 C4x x x
Message Cueing (MC)
Ignore Address Bit (IAB)
Power Up (PU)
Play/Record (P/R)
RUN
FIGURE 4: SPI PORT
Notes: 1. For MOSI, LSB is the 1st bit shifted into the ISD4004.
2. For MISO, LSB is the 1st bit shifted out from the ISD4004.
ISD4004 SERIES
Publication Release Date: March 2017
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6.2.3 SPI Control and Output Registers
The SPI control register provides control of individual function such as play, record, message cueing, power-up, power-down, start, stop and ignore address pointer operations.
TABLE 3: SPI CONTROL REGISTERS
Control Bit Control Register Bit Device Function
C0 MC
=
=
1
0
Message Cueing function
Enable Message Cueing
Disable Message Cueing
C1 IAB [1]
=
=
1
0
Ignore Address bit
Ignore input address register (A0-A15)
Use the input address register (A0-A15)
C2 PU
=
=
1
0
Power Up
Power-Up
Power-Down
C3 P/R
=
=
1
0
Playback or Record
Play
Record
C4 RUN
=
=
1
0
Enable or Disable an operation
Start
Stop
Address Bits A0-A15 Input address register
TABLE 4: SPI OUTPUT REGISTERS
Output Bits Description
OVF Overflow
EOM End-of-Message
P0-P15 Output of the row pointer register
[1]
When IAB (Ignore Address Bit) is set to 0, a playback or record operation starts from address (A0-A15). For consecutive playback or record, IAB should be changed to a 1 before the end of that row (see RAC timing). Otherwise the ISD4004 will repeat the operation from the same row address. For memory management, the Row Address Clock (RAC) signal and IAB can be used to move around the memory segments.
ISD4004 SERIES
Publication Release Date: March 2017
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Message Cueing
Message cueing (MC) allows the user to skip through messages, without knowing the actual physical location of the messages. It will stop when an EOM marker is reached. Then, the internal address counter will point to the next message. Also, it will enter into OVF condition when it reaches the end of memory. In this mode, the messages are skipped 1,600 times faster than the normal playback mode.
Power-Up Sequence
The ISD4004 will be ready for an operation after power-up command is sent and followed by the TPUD timing (25 ms for 8 KHz sampling rate). Refer to the AC timing table for other TPUD values with respect to different sampling rates.
The following sequences are recommended for optimized Record and Playback operations.
Record Mode
1. Send POWERUP command.
2. Wait TPUD (power-up delay).
3. Send POWERUP command.
4. Wait 2 x TPUD (power-up delay).
5. a). Send SETREC command with address xx, or
b). Send REC command (recording from current location).
6. Send STOP command to stop recording.
7. Wait TSTOP/PAUSE.
For 3 & 4), please refer to Apps Brief 39A: recorded pop elimination in the ISD4000 series.
For 5.a), the device will start recording at address xx and will generate an interrupt when an overflow (end of memory array) is reached, if no STOP command is sent before that. Then, it will automatic stop recording operation.
Playback Mode
1. Send POWERUP command
2. Wait TPUD (power-up delay)
3. a). Send SETPLAY command with address xx, or
b). Send PLAY command (playback from current location).
4. a). Send STOP command to halt the playback operation, or
b). Wait for playback operation to stop automatically, when an EOM or OVF is reached.
5. Wait TSTOP/PAUSE.
For 3.a), the device will start playback at address xx and it will generate an interrupt when an EOM or OVF is reached. It will then stop playback operation.
ISD4004 SERIES
Publication Release Date: March 2017
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7. TIMING DIAGRAMS
TSSH
TSSmin
TSCKhiT
SSS
TDIS
TDIH
TSCKlow
TPD
TPD
TDF
(TRISTATE)
LSB
SS
SCLK
MOSI
MISO
FIGURE 5: TIMING DIAGRAM
SS
SCLK
MOSI
MISO
A8 A9 A10 C0 C1 C2 C3 C4
OVF EOM P0 P1 P2 P3 P4 P5
LSB
LSB
FIGURE 6: 8-BIT COMMAND FORMAT
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Publication Release Date: March 2017
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MOSI
MISO
LSB
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
XXP10P9P8 P11 P12 P13 P14 P15
LSB
P7P6P5P4P3P2P1P0EOMOVF
SS
C0 C3 C4C1 C2X XX
X XX X
SCLK
BYTE 1 BYTE 2 BYTE 3
FIGURE 7: 16-BIT COMMAND FORMAT
SS
SCLK
MOSI
MISO
≈
≈
≈
≈ ≈ ≈
≈ ≈ ≈
≈ ≈ ≈
≈
≈
≈
≈ ≈
≈≈
ANA IN
ANA OUT
Data
Play/Record Stop
Data
(Rec)
(Play)
TSTOP/PAUSE
TSTOP/PAUSE
FIGURE 8: PLAYBACK/RECORD AND STOP CYCLE
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
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8. ABSOLUTE MAXIMUM RATINGS
TABLE 5: ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)
CONDITIONS VALUES
Junction temperature 150°C
Storage temperature range -65°C to +150°C
Voltage applied to any pin (VSS –0.3V) to (VCC +0.3V)
Voltage applied to any pin (Input current limited to 20mA) (VSS –1.0V) to (VCC +1.0V)
Voltage applied to MOSI, SCLK, and SS pins
(Input current limited to 20mA)
(VSS –1.0V) to 5.5V
Lead temperature (soldering – 10 seconds) 300°C
VCC – VSS -0.3V to +7.0V
TABLE 6: ABSOLUTE MAXIMUM RATINGS (DIE)
CONDITIONS VALUES
Junction temperature 150°C
Storage temperature range -65°C to +150°C
Voltage applied to any pad (VSS –0.3V) to (VCC +0.3V)
Voltage applied to any pad (Input current limited to 20 mA) (VSS –1.0V) to (VCC +1.0V)
Voltage applied to MOSI, SCLK, and SS pins
(Input current limited to 20mA)
(VSS –1.0V) to 5.5V
VCC – VSS -0.3V to +7.0V
Note: Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability and performance. Functional operation is not implied at these conditions.
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8.1. OPERATING CONDITIONS
TABLE 7: OPERATING CONDITIONS (PACKAGED PARTS)
CONDITIONS VALUES
Commercial operating temperature range (Case temperature) 0°C to +70°C
Industrial operating temperature (Case temperature) -40°C to +85°C
Supply voltage (VCC) [1]
+2.7V to +3.3V
Ground voltage (VSS) [2]
0V
TABLE 8: OPERATING CONDITIONS (DIE)
CONDITIONS VALUES
Commercial operating temperature range 0°C to +50°C
Supply voltage (VCC) [1]
+2.7V to +3.3V
Ground voltage (VSS) [2]
0V
[1]
VCC = VCCA = VCCD [2]
VSS = VSSA = VSSD
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9. ELECTRICAL CHARACTERISTICS
9.1. PARAMETERS FOR PACKAGED PARTS
TABLE 9: DC PARAMETERS
PARAMETERS SYMBOLS MIN[2]
TYP[1]
MAX[2]
UNITS CONDITIONS
Input Low Voltage VIL VCC x 0.2 V
Input High Voltage VIH VCC x 0.8 V
Output Low Voltage VOL 0.4 V IOL = 10 µA
RAC, INT Output Low Voltage
VOL1 0.4 V IOL = 1 mA
Output High Voltage VOH VCC - 0.4 V IOH = -10 µA
Operating Current
- Playback
- Record
ICC
15
25
30
40
mA
mA
REXT = ∞ [3]
REXT = ∞ [3]
Standby Current ISB 1 10 µA [3] [4]
Input Leakage Current IIL 1 µA
MISO Tri-State Current IHZ 1 10 µA
Output Load Impedance REXT 5 KΩ
ANA IN+ Input Resistance RANA IN+ 2.2 3.0 3.8 KΩ
ANA IN- Input Resistance RANA IN- 40 56 71 KΩ
ANA IN+ or ANA IN- to AUD OUT Gain
AARP 23 dB 32 mVpp 1 KHz sinewave input
[5]
Notes: [1]
Typical values @ TA = 25°C and VCC = 3.0V. [2]
All Min/Max limits are guaranteed by Nuvoton via electronical testing or characterization. Not all specifications are 100 percent tested.
[3] VCCA and VCCD connected together.
[4] SS = VCCA = VCCD, XCLK = MOSI = VSSA = VSSA and all other pins floating.
[5] Measured with AutoMute feature disabled.
ISD4004 SERIES
Publication Release Date: March 2017
- 23 - Revision 1.32
TABLE 10: AC PARAMETERS (Packaged Parts)
CHARACTERISTIC SYMBOLS MIN[2]
TYP[1]
MAX[2]
UNITS CONDITIONS
Sampling Frequency ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M
FS 8.0 6.4 5.3 4.0
KHz KHz KHz KHz
[5]
[5]
[5]
[5]
Filter Pass Band ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M
FCF 3.4 2.7 2.3 1.7
KHz KHz KHz KHz
3 dB Roll-Off Point
[3][7]
3 dB Roll-Off Point[3][7]
3 dB Roll-Off Point[3][7]
3 dB Roll-Off Point[3][7]
Record Duration ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M
TREC 8 10 12 16
min min min min
[6]
[6]
[6]
[6]
Playback Duration ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M
TPLAY 8 10 12 16
min min min min
[6]
[6]
[6]
[6]
Power-Up Delay ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M
TPUD 25
31.25 37.5 50
msec msec msec msec
Stop or Pause in Record or Play ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M
TSTOP or TPAUSE 50
62.5 75
100
msec msec msec msec
RAC Clock Period ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M
TRAC 200 250 300 400
msec msec msec msec
[10]
[10]
[10]
[10]
RAC Clock Low Time ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M
TRACL 25
31.25 37.5 50
msec msec msec msec
RAC Clock Period in Message Cueing Mode
ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M
TRACM
125 156.3 187.5 250
µsec µsec µsec µsec
RAC Clock Low Time in Message Cueing Mode
ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M
TRACML 15.63 19.53 23.44 31.25
µsec µsec µsec µsec
Total Harmonic Distortion THD 1 2 % 32 mVpp 1 KHz sinewave input
[11]
ANA IN Input Voltage VIN 32 mV Peak-to-Peak [4] [8] [9]
ISD4004 SERIES
Publication Release Date: March 2017
- 24 - Revision 1.32
Notes: [1]
Typical values @ TA = 25°C, VCC = 3.0V and timing measurement at 50% of Vcc level. [2]
All Min/Max limits are guaranteed by Nuvoton via electrical testing or characterization. Not all specifications are 100 percent tested.
[3] Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions)
[4] Single-ended input mode. In the differential input mode, VIN maximum for ANA IN+ and ANA IN- is 16
mVp-p.
[5] Sampling Frequency can vary as much as 2.25 percent over the commercial temperature and voltage
ranges, and –6/+4 percent over the industrial temperature and voltage ranges. For greater stability, an external clock can be utilized (see Pin Descriptions)
[6] Playback and Record Duration can vary as much as 2.25 percent over the commercial temperature
and voltage ranges, and –6/+4 percent over the industrial temperature and voltage ranges. For greater stability, an external clock can be utilized (see Pin Descriptions)
[7] Filter specification applies to the antialiasing filter and the smoothing filter. Therefore, from input to
output, expect a 6 dB drop by nature of passing through both filters. [8]
The typical output voltage will be approximately 450 mVp-p with VIN at 32 mVp-p. [9]
For optimal signal quality, this maximum limit is recommended. [10]
When a record command is sent, TRAC = TRAC + TRACL on the first row address. [11]
Measured with AutoMute feature disabled.
ISD4004 SERIES
Publication Release Date: March 2017
- 25 - Revision 1.32
9.2. PARAMETERS FOR DIE
TABLE 11: DC PARAMETERS
PARAMETERS [6]
SYMBOLS MIN[2]
TYP[1]
MAX[2]
UNITS CONDITIONS
Input Low Voltage VIL VCC x 0.2 V
Input High Voltage VIH VCC x 0.8 V
Output Low Voltage VOL 0.4 V IOL = 10 µA
RAC, INT Output Low Voltage
VOL1 0.4 V IOL = 1 mA
Output High Voltage VOH VCC - 0.4 V IOH = -10 µA
Operating Current
-Playback
-Record
ICC
15
25
30
40
mA
mA
REXT = ∞ [3]
REXT = ∞ [3]
Standby Current ISB 1 10 µA [3] [4]
Total Harmonic Distortion THD 1 2 % 32 mVpp 1 KHz sinewave input
[5]
ANA IN+ or ANA IN- to AUD OUT Gain
AARP 23 dB 32 mVpp 1 KHz sinewave input
[5]
Notes: [1]
Typical values @ TA = 25°C and VCC = 3.0V. Sampling Frequency can vary as much as 2.25 percent over the commercial temperature and voltage ranges.
[2] All Min/Max limits are guaranteed by Nuvoton via electrical testing or characterization. Not all
specifications are 100 percent tested. [3]
VCCA and VCCD connected together.
[4] SS = VCCA = VCCD, XCLK = MOSI = VSSA = VSSA and all other pins floating.
[5] Measured with AutoMute feature disabled.
[6] The test coverage for die is limited to room temperature testing. The test conditions may differ from that
of packaged parts.
ISD4004 SERIES
Publication Release Date: March 2017
- 26 - Revision 1.32
9.3. SPI AC PARAMETERS
TABLE 12: AC PARAMETERS[1]
PARAMETER SYMBOL MIN TYP MAX UNITS CONDITIONS
SS Setup Time TSSS 500 nsec
SS Hold Time TSSH 500 nsec
Data in Setup Time TDIS 200 nsec
Data in Hold Time TDIH 200 nsec
Output Delay TPD 500 nsec
Output Delay to HighZ [2]
TDF 500 nsec
SS HIGH TSSmin 1 µsec
SCLK High Time TSCKhi 400 nsec
SCLK Low Time TSCKlow 400 nsec
CLK Frequency F0 1,000 KHz
Notes:
[1] Typical values @ TA = 25C, VCC = 3.0V and timing measurement at 50% of Vcc level.
[2] Tri-state test condition.
MISO
VCC
6.32K
10.91K
50pF (Includes scope and fixture capacitance)
ISD4004 SERIES
Publication Release Date: March 2017
- 27 - Revision 1.32
10. TYPICAL APPLICATION CIRCUIT
These application examples are for illustration purposes only. Nuvoton makes no representation or warranty that such application will be suitable for production.
Make sure all bypass capacitors are as close as possible to the package.
68HC705C8P
ISD4004
15-30 pF
C9
15-25 pF
C8
10 K
R7
47 K
R6
47 K
R5
39
38
1
2
37
35
11
10
9
8
7
6
5
4
19
18
17
16
15
14
13
12
21
22
23
24
25
26
27
28
34
33
32
31
30
29 3
2
28
1
16
17
24
25
26
14
13
11
12
23
18
4
27
13
14
5
6
7
3
2
16
9
8
4
1
12
15
10
11
C11
0.1 F
C10
0.1 F
C5
1 F
C4
1 F
C3 0.1 F
C2 0.1 F
C122 F
VCC
R1
10K
R2
1M
R3 100
R4
100K POT
LINE OUT
EXT
SPEAKER
C6
1 F C7
.1 F
J43
2
4
5
1
3
2
1
3
4
5
1
J1
U3
U1
U2
LM4860M
OCS1
OCS2
RESET
IRQ
TCAP
TCMP
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PD7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0/RDI
PD1/TD0
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
MISO
MOSI
SCLK
SS
ANA IN-
ANA IN+
RAC
INT
XCLK
AM CAP
VCCD
VSSD
VCCA
VSSA
VSSA
VSSA
AUD OUT
-IN
+IN
BYPASS
HP-IN1
HP-IN2
HPSENSE
SHUTDOWN
GAIN-OUT
V01
V02
VDD
GND
GND
GND
GND
GND
PDIP / SOIC
VCC
VCC
2
FIGURE 9: APPLICATION EXAMPLE USING SPI
ISD4004 SERIES
Publication Release Date: March 2017
- 28 - Revision 1.32
COP 820C ISD4004
R7
23
24
6
5
25
19
20
21
22 3
2
28
1
16
17
24
25
26
14
13
11
12
23
18
4
27
13
14
5
6
7
3
2
16
9
8
4
1
12
15
10
11
C9
0.1 F
C8
0.1 F
C5
1 F
C4
1 F
C3 0.1 F
C2 0.1 F
C122 F
VCC
R1
10K
R2
1M
R3 100R4
100K POT
LINE OUT
EXT
SPEAKER
C6
1 F C7
.1 F
J43
2
4
5
1
3
2
1
3
4
5
1
J1
U3
U1
U2
LM4860M
GND
RESET
VCC
CLI
D3
D2
D1
D0
MISO
MOSI
SCLK
SS
ANA IN-
ANA IN+
RAC
INT
XCLK
AM CAP
VCCD
VSSD
VCCA
VSSA
VSSA
VSSA
AUD OUT
-IN
+IN
BYPASS
HP-IN1
HP-IN2
HPSENSE
SHUTDOWN
GAIN-OUT
V01
V02
VDD
GND
GND
GND
GND
GND
PDIP / SOIC
C10
4.7 K
R6
4.7 K
R5
10
11
12
13
3.3 K
82 pF
7
8
9
10
G3
G2
G1
INT
SI
SK
G7
SO
L7
L6
L5
L4
L3
L2
L1
L0 11
12
13
14
15
16
17
18
1
4
2
3
26
27
28
VCC
VCC V
CC
2
FIGURE 10: APPLICATION EXAMPLE USING MICROWIRE
ISD4004 SERIES
Publication Release Date: March 2017
- 29 - Revision 1.32
PIC16C62A ISD4004
R7
8
1
20
14
16
15
3
2
28
1
16
17
24
25
26
14
13
11
12
23
18
4
27
13
14
5
6
7
3
2
16
9
8
4
1
12
15
10
11
C9
0.1 F
C8
0.1 F
C5
1 F
C4
1 F
C3 0.1 F
C2 0.1 F
C122 F
VCC
R1
10K
R2
1M
R3 100R4
100K POT
LINE OUT
EXT
SPEAKER
C6
1 F C7
.1 F
J43
2
4
5
1
3
2
1
3
4
5
1
J1
U3
U1
U2
LM4860M
VSS
MCLR
VDD
RC4
RC5
RC3
MISO
MOSI
SCLK
SS
ANA IN-
ANA IN+
RAC
INT
XCLK
AM CAP
VCCD
VSSD
VCCA
VSSA
VSSA
VSSA
AUD OUT
-IN
+IN
BYPASS
HP-IN1
HP-IN2
HPSENSE
SHUTDOWN
GAIN-OUT
V01
V02
VDD
GND
GND
GND
GND
GND
PDIP / SOIC
C10
4.7 K
R6
4.7 K
R5
OSC1
3.3 K
9
RC4
RB0
RC0 11
21
7
VCC
VCC V
CC
2
19 VSS
FIGURE 11: APPLICATION EXAMPLE USING SPI PORT ON MICROCONTROLLER
ISD4004 SERIES
Publication Release Date: March 2017
- 30 - Revision 1.32
11. PACKAGING AND DIE INFORMATION
11.1. 28-LEAD 300-MIL PLASTIC SMALL OUTLINE IC (SOIC)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
D
E F
B
G
C
H
INCHES MILLIMETERS
Min Nom Max Min Nom Max
A 0.701 0.706 0.711 17.81 17.93 18.06
B 0.097 0.101 0.104 2.46 2.56 2.64
C 0.292 0.296 0.299 7.42 7.52 7.59
D 0.005 0.009 0.0115 0.127 0.22 0.29
E 0.014 0.016 0.019 0.35 0.41 0.48
F 0.050 1.27
G 0.400 0.406 0.410 10.16 10.31 10.41
H 0.024 0.032 0.040 0.61 0.81 1.02
Note: Lead coplanarity to be within 0.004 inches.
ISD4004 SERIES
Publication Release Date: March 2017
- 31 - Revision 1.32
11.2. 28-LEAD 600-MIL PLASTIC DUAL INLINE PACKAGE (PDIP)
INCHES MILLIMETERS
Min Nom Max Min Nom Max
A 1.445 1.450 1.455 36.70 36.83 36.96
B1 0.150 3.81
B2 0.065 0.070 0.075 1.65 1.78 1.91
C1 0.600 0.625 15.24 15.88
C2 0.530 0.540 0.550 13.46 13.72 13.97
D 0.19 4.83
D1 0.015 0.38
E 0.125 0.135 3.18 3.43
F 0.015 0.018 0.022 0.38 0.46 0.56
G 0.055 0.060 0.065 1.40 1.52 1.62
H 0.100 2.54
J 0.008 0.010 0.012 0.20 0.25 0.30
S 0.070 0.075 0.080 1.78 1.91 2.03
q 0° 15° 0° 15°
ISD4004 SERIES
Publication Release Date: March 2017
- 32 - Revision 1.32
11.3. DIE INFORMATION
ISD4004 Series
o Die Dimensions (with scribe line) [1]
X: 166.6 1 mils
Y: 385.0 1 mils
o Die Thickness [2]
11.5 0.5 mils
o Pad Opening
Single pad: 90 x 90 microns
Double pad: 180 x 90 microns
Notes:
[1] The backside of die is internally connected to VSS. It MUST NOT be connected to any other potential or
damage may occur. [2]
Die thickness is subject to change, please contact Nuvoton as this thickness may change in the future. [3]
Double bond is recommended if treated as one pad.
MISO
MOSI
SS VCCD
SCLKINT RAC
VSSA
VSSD
VSSD
VCCD
XCLK
≈ ISD4004 ≈
VCCA
[3]ANA IN+AM CAP
AUD OUTVSSA
[3]
VSSA
ANA IN-V
SSA[3]
VCCA
[3]
ISD4004 SERIES
Publication Release Date: March 2017
- 33 - Revision 1.32
ISD4004 SERIES PAD COORDINATIONS
(with respect to die center)
Pad Pad Description X Axis (µm) Y Axis (µm)
VSSA Analog Ground 1885.2 4623.7
RAC Row Address Clock 1483.8 4623.7
INT Interrupt 794.8 4623.7
XCLK External Clock Input 564.8 4623.7
VCCD Digital Power Supply 387.9 4623.7
VCCD Digital Power Supply 169.5 4623.7
SCLK Slave Clock -14.7 4623.7
SS Slave Select -198.1 4623.7
MOSI Master Out Slave In -1063.7 4623.7
MISO Master In Slave Out -1325.6 4623.7
VSSD Digital Ground -1665.3 4623.7
VSSD Digital Ground -1836.9 4623.7
VSSA [1]
Analog Ground -1943.1 -4622.4
VSSA [1]
Analog Ground -1853.1 -4622.4
VSSA Analog Ground -1599.9 -4622.4
AUD OUT Audio Output 281.9 -4622.4
AM CAP AutoMute 577.3 -4622.4
ANA IN- Inverting Analog Input 1449.3 -4622.4
ANA IN+ Noninverting Analog Input 1603.5 -4622.4
VCCA [1]
Analog Power Supply 1853.7 -4622.4
VCCA [1]
Analog Power Supply 1943.7 -4622.4
Note: [1]
Double bond recommended if treated as one pad.
ISD4004 SERIES
Publication Release Date: March 2017
- 34 - Revision 1.32
12. ORDERING INFORMATION
When ordering the devices, please refer to the following valid ordering numbers and contact the local Nuvoton Sales Representatives for availability.
Type Durati
on
8 Minutes 10 Minutes 12 Minutes 16 Minutes
Packa
ge
Part # Order # Part # Order # Part # Order # Part # Order #
Die ISD4004-08MX I4408X ISD4004-10MX I4410X ISD4004-12MX I4412X ISD4004-16MX I4416X
Le
ad
-
Fre
e
PDIP ISD4004-08MPY I4408PY ISD4004-10MPY I4410PY ISD4004-12MP I4412PY ISD4004-16MPY I4416PY
SOIC ISD4004-08MSY I4408SY ISD4004-10MSY I4410SY ISD4004-12MS I4412SY ISD4004-16MSY I4416SY
ISD4004-08MSYI I4408SYI
ISD4004-10MSYI I4410SYI ISD4004-12MSI
I4412SYI ISD4004-16MSYI
I4416SYI
For the latest product information, access Nuvoton worldwide website at http://www.Nuvoton-usa.com
ISD4004-
Product Family :
Product Series :
ISD4000 Family
04 = Fourth Series (8-16 min)
Duration :
08M = 8 minutes
10M = 10 minutes
12M = 12 minutes
16M = 16 minutes
Special Temperature Field :
Blank = Commercial Package (0°C to + 70°C)
or Commercial Die (0°C to + 50°C)
I = Industrial (-40°C to + 85°C)
Packaged Units / Die :
X = Die
P = 28-Lead 600-mil Plastic Dual Inline Package (PDIP)
S = 28-Lead 300-mil Plastic Small Outline Package (SOIC)
Lead-Free Type:
Y = Lead-Free
ISD4004 SERIES
Publication Release Date: March 2017
- 35 - Revision 1.32
13. VERSION HISTORY
VERSION DATE DESCRIPTION
0 June 2000 Initial version
1.0 Feb. 2004 Reformat the document.
Add note for typical filter pass band.
Add memory architecture description.
Revise RAC timing parameter for MC.
Revise AutoMute: playback only.
Revise SPI, opcodes sections, record & playback steps.
Rename TRACLO to TRACL.
Revise AARP parameter.
Revise DC & AC parameters tables for die.
Revise die: (x,y) coordinates.
1.1 Apr. 2005 Add lead-free parts.
Revise the Ordering information.
Revise disclaim section.
1.2 Oct. 2005 Revise Packaging information.
1.3 Jul. 2007 Remove the leaded package option
Remove the extended temperature option
Update the external clock description
Revise Ordering Information section
1.31 Oct 31, 2008 Change to Nuvoton logo
Revise MISO description
1.32 March, 2017 Removed TSOP Package not recommended for new design
ISD4004 SERIES
Publication Release Date: March 2017
- 36 - Revision 1.32
Headquarters Nuvoton Technology Corporation America Nuvoton Technology (Shanghai) Ltd.
No. 4, Creation Rd. III 2727 North First Street, San Jose, 27F, 299 Yan An W. Rd. Shanghai, Science-Based Industrial Park, CA 95134, U.S.A. 200336 China Hsinchu, Taiwan TEL: 1-408-9436666 TEL: 86-21-62365999 TEL: 886-3-5770066 FAX: 1-408-5441797 FAX: 86-21-62356998 FAX: 886-3-5665577 http://www.Nuvoton-usa.com/ http://www.Nuvoton.com.tw/
Taipei Office Nuvoton Technology Corporation Japan Nuvoton Technology (H.K.) Ltd.
9F, No. 480, Pueiguang Rd. 7F Daini-ueno BLDG. 3-7-18 Unit 9-15, 22F, Millennium City, Neihu District Shinyokohama Kohokuku, No. 378 Kwun Tong Rd., Taipei, 114 Taiwan Yokohama, 222-0033 Kowloon, Hong Kong TEL: 886-2-81777168 TEL: 81-45-4781881 TEL: 852-27513100 FAX: 886-2-87153579 FAX: 81-45-4781800 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales.
The contents of this document are provided only as a guide for the applications of Nuvoton products. Nuvoton makes no representation or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice. No license, whether express or implied, to any intellectual property or other right of Nuvoton or others is granted by this publication. Except as set forth in Nuvoton's Standard Terms and Conditions of Sale, Nuvoton assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property.
The contents of this document are provided “AS IS”, and Nuvoton assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. In no event, shall Nuvoton be liable for any damages whatsoever (including, without limitation, damages for loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this documents, even if Nuvoton has been advised of the possibility of such damages.
Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only and Nuvoton makes no representation or warranty that such applications shall be suitable for the use specified.
The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in the Nuvoton Reliability Report, and are neither warranted nor guaranteed by Nuvoton. This product incorporates SuperFlash®.
Information contained in this ISD® ChipCorder® datasheet supersedes all data for the ISD ChipCorder products published by ISD® prior to August, 1998.
This datasheet and any future addendum to this datasheet is(are) the complete and controlling ISD® ChipCorder® product specifications. In the event any inconsistencies exist between the information in this and other product documentation, or in the event that other product documentation contains information in addition to the information in this, the information contained herein supersedes and governs such other information in its entirety. This datasheet is subject to change without notice.
Copyright© 2005, Nuvoton Technology Corporation. All rights reserved. ChipCorder® and ISD® are trademarks of Nuvoton Technology Corporation. SuperFlash® is the trademark of Silicon Storage Technology, Inc. All other trademarks are properties of their respective owners.