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Single Electron Transistor Instructor : Pei-Wen Li1
Single-Electron Transistors
Reference book:
Single Charge Tunneling Coulomb Blockade
Phenomena in Nanostructures
By Hermann Grabert and Michel H. Devoret, 1992
Referred Journal Review Papers:
Correlated discrete transfer of single electrons in ultrasmall tunnel juntions
By K. K. Likharev, IBM J. Res. Develop. Vol.32, p.144, 1989
Single-Electron Devices and Their Applications
By K. K. Likharev, Proceedings of the IEEE, vol.87, p.606, 1999
Single-Electron Memory for Gita-to Tera Bit Storage
By K. Yano et al., Proceedings of the IEEE, vol.87, p.633, 1999
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Single Electron Transistor Instructor : Pei-Wen Li2
Contents
Single Electron Phenomena: A General Introduction
Single Electron Transistor
Fabrication and Analysis Applications
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Single Electron Transistor Instructor : Pei-Wen Li3
Single Electron Phenomena: A General Introduction
.Scaling prospects for various
bit-addressable memories.
DRAM is expected to be bottlenecked atthe generation of 64 Gbit integration (70
nm technology) due to the problems with
the storage capacitor scaling.
Nonvolatile memory is going to be the
mainstream for 64Gbit-16Tbit memory.
SET/FET would be feasible starting from
~ 3 nm minimum feature sizes.
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SET Evolution
The manipulation of single electrons was demonstrated in the seminal
experiments by Millikan at the very beginning of 20 century.
Single Electron Device: in which the addition or substraction of a small number
of electrons to/from an electrode can be controlled with one-electron precision
using the charging effect.
They are not interesting not only as new physical phenomena in nanostructures but also
because they offer new operating principles for future ICs. Application: Memory, switch, Thermal meter
Advantages:
Good stability: is the strong incentive to explore the possibility of the devices.
atomic scale physical dimension ULSI possible Ultralow power operation: simply because they use very small number of electrons to
accomplish basic operation.
Fast operation: only a few electrons (
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Schematic of Single Electron Devices
A quantum dot is weakly coupled by tunnel barriers to two electron reserviors.Oxide
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A General Introduction
Recall that the motion of electrons in an infinite potential well is in a standing
waveform. That means that the energy of the particle in the infinite potential
well is quantized. That is, the energy of the particle can only have particular
discrete values.
integerpositiveaisnwhere
2
2
222
ma
nEE n
h==
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Charging Energy
Let a small conductor (island) be initially electroneutral, i.e., have exactly as
many (m) electrons as it has protons in its crystal lattice. In this state the island
does not generate any appreciable electric field beyond its borders, and a weak
external force may bring in an additional electron from outside. Now the net
charge of the island is (-e), and the resulting E field repulses the following
electrons which might be added.
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Charging Energy
The charging energy of the island isEC, where Cis the capacitance of the island:
When the size of the island becomes comparable with the de Brogliewavelength of the electron inside the island energy quantization
The energy scale of the charging effects is given by a more general notion, the
electron addition energy (Ea). In most cases of interest,E
acould be
approximated by
HereEk is the quantum kinetic energy of the addition electron; for a degenerate
electron gasEk= 1/g(F)V, where Vis the island volume andg(F) is the density
of states on the Fermi surface.
CeEC
2
=
kCa EEE +=
( )m
k
mW
nEN
22
22
2
2hh
+=
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Single Electron Transistor Instructor : Pei-Wen Li9
Electron Transfer in an quantum dot
The transport of electrons through the quantum dots is an interplay of resonant
tunneling and Coulomb blockade effects.
In the absence of charging effect, a conductance peak due to resonant tunneling
occurs when the Fermi energyEF in the source lines up with one of the energy
levels in the dot.
However, this condition is modified by the charging effect. The energy levelis renormalized by the charging effect
That is, the renormalized level spacing is enhanced above the
bare level spacing by the charging energy.
levelbaretheiswhere,21
2
*nnN E
CeNEE +
2
C
eEE +=
levelenergybaretheiswhere,2 2
222
nnF
Ema
nEE
h==
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Single Electron Transistor Instructor : Pei-Wen Li10
Single-electron tunneling through a quantum dot
The energy levels, EN, are modified by the charging effect. That is the
charging energy regulatesthe level spacing.
The spin degeneracy is lifted by the charging energy.
CeEE
2* +=
Bare Energy level
Normalized Energy level
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Single Electron Transistor Instructor : Pei-Wen Li11
Single-electron tunneling through a quantum dot
(a) , with N referring to the lowest unoccupied level in
the dot.
(b) An electron has tunneled into the dot,
)1(2
2
+=+ NeEC
eE FN
)(2
2
NeEC
eE FN +=
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Single Electron Transistor Instructor : Pei-Wen Li12
Addition Energy, Kinetic Energy
For 100-nm-scale devices,Ea is dominatedby the charging energyEc and is of theorder of 1 meV (~10 K). Since the thermalfluctuations suppress most single-electroneffects unless
these device have to be operated in the
sub-1-K range. Unpractical! If the island size is below ~ 10 nm,Ea
approaches 100 meV, and some singleelectron effects become visible at RT.
However, digital SE devices requireeven higher values ofEa to avoid thermallyinduced random tunneling events, so thatminimum feature size of SET has to besmaller than ~ 1nm. RT operation
Ea =EC+ E
TkE Ba 10
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Single Electron Transistor Instructor : Pei-Wen Li13
Single Electron Transistor
The resulting SET device is reminiscent of a usual MOSFET, but with a small
conducting island embedded between two tunnel barriers, instead of the usual inversion
channel.
The expression of the electrostatic energy W of this SET is
n1 and n2 are the number of electrons passed through the tunnel barriers one and two,
respectively, so that n = n1- n2, while the total island capacitance Ctotal is now a sum of
C0, C1, C2, and whatever stray capacitance the island may have. The external charge Qe
= C0Vg is just a convenient way to present the effect of the gate voltage Vg.
[ ] constCCnCneVCQneWtotaltotale
++= /2/)(1221
2
Vg
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Single Electron Transistor Instructor : Pei-Wen Li14
Single Electron Transistor (SET)
Operation principle:
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Single Electron Transistor Instructor : Pei-Wen Li15
Id-VdCharacteristics
Id-Vd is a function ofVg.
Coulomb Blockade Threshold Voltage Vth.
Coulomb gap
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Single Electron Transistor Instructor : Pei-Wen Li16
Coulomb Gap
Large bias (Vds)Id-Vds measurements
generally probe the excitation
spectrum of the dot. The conductance
peaks are associated with the excitedelectron states in the QD, appearing
whenever such an excitation is aligned
with the Fermi level of one of the S/D
leads.
The Coulomb-blockade gap is
manifested by the flat region of theId-
Vds curve spanning Vds ~ 0V. At theedge of the gap, the large peak in
differential conductance on either side
marks the threshold voltage above
which electrons can tunnel into the dot.
( dds
CC
eVgapCoulomb
+==
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Single Electron Transistor Instructor : Pei-Wen Li17
Coulomb Staircase
Unlike the Coulomb suppression of current in the neighborhood ofVds = 0 V
(Coulomb gap), the staircase is not a universal feature of the Coulomb blockade.
Rather, it is a special result of having very different tunneling rates through the
two tunneling barriers.Coulomb staircase
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Single Electron Transistor Instructor : Pei-Wen Li18
Coulomb Staircase
Increasing Vds, the quasi-fermi
level on Source lead is raised by
the bias potential; initially no
current flows because electrons atthe quasi-fermi level do not yet
have enough energy to overcome
the charging energy of the QD.
Eventually, Vds reaches the point
at which an electron can tunnel
from the Source lead onto theQD. current flow and a peakin G is observed.
h f C l b S
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Single Electron Transistor Instructor : Pei-Wen Li19
Physics of Coulomb Staircase
Increasing gate voltage Vgattracts more and more electrons to the island. The
discreteness of electron transfer through low-transparency barriers necessarily
makes this increase step like.
When one tunnel barrier is significantly more transmitting than the other tunnel
barrier, theI-Vbehavior of the dot can exhibit the namely Coulomb staircase
behavior, that is a stepwise curve.
What is surprising is that even such a simple device allows a reliableaddition/subtractionof single electrons to/from an island with an enormous
(and unknown) number of background electrons, of the order of one million in
typical low-temperature experiments with 100-nm-scale aluminum islands.
Id-V Characteristics
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Single Electron Transistor Instructor : Pei-Wen Li20
Id VgCharacteristics
Coulomb-Blockade Oscillation inId-Vgand conductance-Vg, where conductance
d
d
V
IG =
C d P i i
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Single Electron Transistor Instructor : Pei-Wen Li21
Conductance Positions
The gate-voltageposition of the conductance peaks, corresponding to charge-
degeneracy points, are determined at very low temperatures by the conditions
E(N) =E(N+1), which leads to eN+1
= (N+1/2)e2/C+ N+1.
(Recall that ,
where i represents the energy of the ith eigenstate relative to the Fermi level in
the QD and the summation is over the set of occupied states.) The spacing between conductance peaks ,
whereEa is the single-electron addition energy,
is the Coulomb charging energy andis the quantized level separation.
The gate-voltage position of the conductance peaks contains information aboutthe single-particle energies. (addition energy, charging energy, and quantized
level separation)
( )+=N
iNeC
NeNE
2)(
2
e
E
C
e
e
EV
dot
ag
+==
dotC
e
C d t P iti
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Single Electron Transistor Instructor : Pei-Wen Li22
Conductance Positions
In principle, unless the single-particle levels Iare equally spaced, the
conductance peaks are not exactly periodic in Vg. This is true as long as kT
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Single Electron Transistor Instructor : Pei-Wen Li23
Temperature Behavior of Conductance Peaks
At low temperatures, the heights of successive peaks in Vgvary non-monotonically and
adjacent peaks are separated by broad minima.
when kT
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Single Electron Transistor Instructor : Pei-Wen Li24
p f ff
conductance
G< 0
Fine
structure
S1 Vg/ Vd=Cd/Cg S2 Vg/ Vd=Cs/Cg
Device Parameters Extracted from the Rhombus Shapes
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Single Electron Transistor Instructor : Pei-Wen Li25
Device Parameters Extracted from the Rhombus Shapes
The electronic structure in the QD could be extracted from the contour plot of
the differential conductance as a function ofVgand Vd.
The ratio of the gate-dot (Cg), drain-dot (Cd), and source-dot (Cs) capacitances
can be calculated from the slope S1 and S2.
Cg: Cd: Cs = 1: S1 : S2
Then the gain modulation Cg /Ctotal, Ctotal= Cg+ Cd+ Cs The addition energyEa = Vg.
Electronic Structure extracted from I V
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Single Electron Transistor Instructor : Pei-Wen Li26
Electronic Structure extracted from I-V
Addition Energy
Charging Energy
Energy level spacing
Dot diameter
Minimum tunneling resistance for single-electron
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Single Electron Transistor Instructor : Pei-Wen Li27
charging
Implicit in the formulation of the Coulomb-blockade model is the condition that the
number of electrons localized in the dot island,N, is a well-defined integer. This is to say,
well defined in the classical sense, as opposed to a quantum definition which describesN
in terms of an average value , which is not necessarily an integer, and time-averagedfluctuations .
The Coulomb-blockade model requires that
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Single Electron Transistor Instructor : Pei-Wen Li28
Co-tunneling
Even if the minimum resistance criterion is met and single-electron chargingeffects are manifested, small quantum fluctuations, or uncertainties, inNare notentirely ruled out. In the classical Coulomb-blockade model there is then a fixed
number of electronsNon the QD and at T= 0 the charge on the QD does notfluctuate.
However, the fact that very small quantum fluctuation inNmay be presentcorresponds to electrons momentarily tunneling onto the QD, with an energy
deficit on the scale of the classical Coulomb charging energy. Essentially, the tunneling electron resides on the QD in a virtual charge state for
a sufficiently brief interval such that the energy uncertainty of this state is largerthan its classical energy deficit, subsequently tunneling out. This process has
been referred to as co-tunneling or macroscopic quantum tunneling of charge. The rational behind is that the total charge of the system (a macroscopic
variable) undergoes a transition through a classically forbidden intermediatestate, in apparent violation of the Coulomb blockade.
Elastic co-tunneling
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Single Electron Transistor Instructor : Pei-Wen Li29
Elastic co-tunneling
The tunneling of an electron into a certain energy state and the tunneling of an
electron from thesame state out of the dot. The end result of the two tunneling
events is that the state of the QD is unchanged, and as such, this is referred to as
elastic co-tunneling, which contributes a linear term to the I-V curve.
where is the average energy separation between eigenstates in the QD andE1(E
2) is the charging energy associated with adding (removing) a single electron
to (from) the dot. Note, in particular, that the resulting conductance scales
roughly as the ratio between the level spacing and the Coulomb gap U e2/C. The case of elastic co-tunneling depends, in principle, on the geometry of the
QD. This is because the electron involved has to couple to both leads; thus in a
sense it must traverse the dot in a virtual state.
VEEe
hIel
+
=
2122
21 11
8
Inelastic co-tunneling
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Single Electron Transistor Instructor : Pei-Wen Li30
Inelastic co tunneling
It corresponds to an electron tunnels into a certain state in the dot and a second
electron, from a different state, tunnels out of the dot. The state of the dot is
modified, leaving an electron-hole excitation. The resulting current is nonlinear
in Vds and temperature-dependent. The case of inelastic co-tunneling gives thefollowing well-known form
( ) VeV
kTEEe
hIinel
+
+
=
22
2
21221
2
11
6
Cotunneling
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Single Electron Transistor Instructor : Pei-Wen Li31
Cotunneling
The distinction is made between these two processes because their relative
contributions to the total net cotunneling current depend on the density of states
in the QD.
In metal QDs, in which the density of states is large, the elastic component of
co-tunneling is usually overwhelmed by the inelastic component.
In semiconductor QDs, in which the density of states is much smaller than in
metals, both elastic and inelastic terms can contribute to the co-tunnelingcurrent.
In practice, co-tunneling is expected to modify the classical picture of single-electron charging in the form ofexcess current in the region of the Coulomb-
blockade gap, in the case ofI-Vds measurements, or excess tunneling current
between conductance peaks in low-bias measurements.
Fabrication
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Single Electron Transistor Instructor : Pei-Wen Li32
Fabrication
To apply SETs for low power ICs, (i) room-temp operation; (ii) uniformity and
(iii) compatible with the LSI processes are required.
Task:
For room temperature operation, the quantum dot diameter should be less than 10
nm, which corresponds to the total capacitance about 1 aF.
E-beam lithography:
High cost and the following etching process is not easy to control Scanning probe microscopy (SPM) to place Au atoms in nanostructure.
Only applicable in specific substrate
Metal/Superconductor SET
Semiconductor SET
Epitaxial growth quantum dots (self-assembled) or 2DEG with side gate (depletion)
E-beam + dry etching
Fabrication
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Single Electron Transistor Instructor : Pei-Wen Li33
Fabrication
In addition to advanced e-beam lithography technology, matured and
controllable fabrication processes are needed to form small quantum dots (
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Single Electron Transistor Instructor : Pei-Wen Li34
f g g g ( )
Si quantum dot formed by 2D oxidation
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Single Electron Transistor Instructor : Pei-Wen Li35
q f y
Double-dot charge transport in SET/SHT
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Single Electron Transistor Instructor : Pei-Wen Li36
g p
Ge implantation/Ge Segregation
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Single Electron Transistor Instructor : Pei-Wen Li37
p g g
Application
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Single Electron Transistor Instructor : Pei-Wen Li38
pp
Major application fields: Memory
Digital-data-storage
Precision Measurement
Memory >> Logic We can use SE devices only in a memory cell, whereas keep using conventional
CMOS technology in the peripheral circuitry.
Memory cell technology has continuously changed, including the emergence offlash memory technology and ferroelectric-film memory technology.
The way of storing information is rapidly changing from the old regime, relying onpapers and other analog electronic means, to the digital regime in the multimedia era.
New needs of storing information are different from the older specifications inbandwidth, storage capacity, power consumption.
Fundamental difficulty in a logic functional unit since SE devices generally havepoor current-drive capability.
Application-Data Storage System
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Single Electron Transistor Instructor : Pei-Wen Li39
Quantum Information- Qubit
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Single Electron Transistor Instructor : Pei-Wen Li40
Developing a quantum computer is a basic endeavor in science
and technology.
The advantage of Si-based quantum computer is
Low cost
Large scale integration
Contrast to classical bits, |0> or|1> , a quantum computer consistsof Qubits, which could be represented by a superposition of|0>or|1> , i.e.,
|0> + |1> (where 2 + 2 =1)This huge parallelism makes it possible to solve some of the most
difficult problems, such as integer factorization.
Quantum Computer Roadmap: development status
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Single Electron Transistor Instructor : Pei-Wen Li41
After NTT Technical Review, June 2003
Roadmap of Quantum Computer
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Single Electron Transistor Instructor : Pei-Wen Li42
status of solid-state QC
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Single Electron Transistor Instructor : Pei-Wen Li43
Si-based Key Devices for QC
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Single Electron Transistor Instructor : Pei-Wen Li44
Source DrainIsland
Si
Figure 1. Schematic diagram for a single electron transistor and a
coupled quantum dots.
(singlet) |0> |1>
|0> |1>
(quantum bit).
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Room-Temperature Characterization of Ge SETs
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Single Electron Transistor Instructor : Pei-Wen Li46
Peak-to-valley current ratio (PVCR) of
1.92 is observed at room temperature
Clear offsets and plateaus are seen for
gate voltages corresponding to the drain
current valleys, while linear relations are
obtained for gate voltages correspondingto the drain current peaks.