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Approved for Public Domain Release (VS07-0571)
2007 BAE Systems
All rights reserved
A System-On-Chip Radiation HardenedMicrocontroller ASIC With Embedded
SpaceWire Router
Richard Berger, Laura Burcin, David Hutcheson, Jennifer Koehler, Marla Lassa,Myrna Milliser, David Moser, Dan Stanley, Randy Zeger, Ben Blalock, Mark Hale
International SpaceWire Conference 2007
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2Approved for Public Domain Release (VS07-0571)
2007 BAE Systems
All rights reserved
Introduction / Project Goals
The RAD6000MCTM microcontroller is being designed to consolidate all the
key elements needed for moderate levels of spaceborne computing into asingle ASIC
It is flexible enough for a wide variety of applications, from instrument
control to safe mode back-up
The RAD6000MC will be manufactured in BAE Systems RH15 150nm
radiation hardened technology, with a goal of 10x improvement in power-
performance vs. existing RAD600-based single board computers
Based on the space-proven RAD6000 CPU, it will include strong software
support for users
Green Hills Compiler
VxWorks operating system with possible addition of real time
embedded solution as well
Easy reuse/migration of existing RAD6000 application code
Reuse of existing RAD6000 infrastructure
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3Approved for Public Domain Release (VS07-0571)
2007 BAE Systems
All rights reserved
RAD6000MCTM Features Processor Units
RAD6000TM CPU
Selectable 33 or 66 MHz clock
Fixed and floating point execution units Up to 3 instructions/cycle
8KB unified D/I cache
Embedded Microcontroller (EMC)
SRAM and Non-volatile Memory with controllers
128 KB synchronous SRAM on-chip memory
32 KB C-RAMTM non-volatile program store
External Memory controller for SRAM, DRAM,C-RAM, etc.
Direct Memory Access (DMA) controller
I/O Bus and Communications Interfaces
33 MHz, 64-bit PCI interface (version 2.2)
16550 compatible UART
SpaceWire router with 4 serial links
Dual 1553 interface w/64 KB of on-chip SRAM
JTAG master and slave test controllers
Analog interfaces
12-bit, 8.25 Msps A-D converter
48 input programmable analog multiplexer
Three 12-bit 1 Ksps D-A converters
Planned Radiation Characteristics
Total Dose: 1Mrad (Si)
Single Event Effects
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4Approved for Public Domain Release (VS07-0571)
2007 BAE Systems
All rights reserved
RAD6000MC ASIC Block Diagram
On-Chip Bus (OCB) Connection Medium
EmbeddedMicrocontroller
(EMC)
64
OCB
Master
64
OCB
Slave
64KB
SRAM
Memory
OCB Slave
64KBSRAM
Memory
OCB Slave
6464
Programmable
Interrupt
Discretes
(PIDs)
MISC
32
OCB
Slave
JTAG
32
OCB Slave
JTAG Master
(JTAG)
33 MHz
PCI 2.2
64 64
OCB
Master
OCB
Slave
PCI-64
Clocks/Reset
Clock And
Test (CAT)
32
PLL
OCB Slave
Local Interface
Function (LIF)
64
OCB
Slave (2)
OCB
Master
64
JTAG
32
OCB Master
JTAG Slave
(JTAG)
I/O
RAD6000TMCPU
External
MemoryCOP
Memory
RAD6000MCTMMicrocontroller ASIC
OCB
Slave
32
COP
Master
33/66MHz
64
1553 A/B
64 64
OCB Slave
D1553 Core
64KB SRAM
UART
UART
32
OCB Slave
Up to 48 External
Analog Inputs
Analog
Multiplexer
A/DConverter
OCB
Master
OCB
Slave
64 3264
Analog I/O
Control (AIC)
OCB
Master
D/AConverter
3 External
Analog Outputs
SpaceWire
Router
and Links
SpaceWire I/F x4
64
OCB
Master
32
OCB
Slave
64
Router I/F (RIF)
OCB
Master
FIFO
FIFO
OCB
Master
OCB
Slave
64 3264
Router I/F (RIF)
OCB
Master
FIFO
FIFO
32KBC-RAMTM
Memory
64
OCB Slave
Reused
New
Minor Mod
Major Mod
DDC IP
Memory
Control
(MCTL)
64 3264
OCB
Master
OCB
SlaveOCB
Master
Direct Memory
Access (DMA)
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5Approved for Public Domain Release (VS07-0571)
2007 BAE Systems
All rights reserved
RAD6000 Microprocessor
Unified
8KB Data /
Instruction
Cache
MemoryInterface Unit
Input / OutputSequencer
UnitInstruction Queue &
Dispatch
Common On-ChipProcessor (COP)
Test Unit
Memory
ManagementUnit (MMU)
Memory Bus
w/ECC
I/O Bus
Data / Inst Addr
Data
VirtualAddress
Instructions
Data
Instruction Address
DataAddress
Data
COP Bus
Controls
to/from
Other Units
Branch Processor&Instruction Fetch
Pipeline
ControlUnit
Fixed
PointExecutionUnit (FXU)
Floating
PointExecutionUnit (FPU)
Cntl
Instructions
Cntl
Fixed and Floating Point Execution Units
Up to 3instructions
per cycle:
fixed, float,
and branch)
Unified
L1 cache
Test and
Diagnostics
Unit
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6Approved for Public Domain Release (VS07-0571)
2007 BAE Systems
All rights reserved
Local Interface Function (LIF) Block Diagram
RAD6000
Memory I/F
RAD6000
Memory Bus
PIO
I/F
RAD6000 I/O Bus
DMA
I/F
Configuration
Registers
OCB Master
I/F
OCB Slave
(0) I/F
OCB Master Stub OCB Slave (0) Stub
Memory
Configuration
I/F
Memory
Request
I/F
Memory
Controller
MC Bus
Memory
Controller
Request
Bus
OCB Slave
(1) I/F
OCB Slave (1) Stub
Contains Base
AddressRegisters used
for Address
Translation, to
extend RAD6000
27-bit (128 MB)
address to 4 GB
Wrap feature supports
use of on-chip Start-upROM using the C-RAM
core
Additional slaveOCB interface
supports direct
access to external
memory from other
on-chip cores
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Approved for Public Domain Release (VS07-0571)
2007 BAE Systems
All rights reserved
RAD6000 Memory Address Translation
RSC_MEM_ADDR (0:23)
3
ADDR (31:0)
Base Address Registers
(8) 16 MB Pages
Base Addr Attr
8 21 3
0s
To OCB or Memory Controller
The complete address
space is 4 GB, but the
available address spacefor the RAD6000 is 2 GB
The other 2 GB is
dedicated for the other
cores within the system
The complete RAD6000
(RSC) memory address
bus is 27 bits
Only the 24 mostsignificant bits (MSBs) are
brought out, since the
RAD6000 accesses 64-bit
(8 byte) words from
memory
The 3 least significant bits
(LSBs) are shown paddedbelow with zeros
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Approved for Public Domain Release (VS07-0571)
2007 BAE Systems
All rights reserved
On-Chip Bus Slave Memory Address Translation
OCB_ADDR (31:0)
3 Bits (26:24)
ADDR (31:0)
Base Address Regs
(8) 16 MB Pages
Base Addr Attr
8 24
To RSC I/O Bus, OCB, or Memory Controller
Bits (31:24)
Rd Snoop Disable
Wr Snoop Disable
For accesses within the 128 MB RSC
addressable region: The Attr field for thatpage determines if the access is snooped
Snooped accesses are passed directly to
the RSC I/O Bus
Non-snooped accesses pick up the Base
Addr field for the page and then are passed
to either the Memory Controller or OCB
For accesses above
the 128 MB RSC
addressable region:
The address is passed
directly to the Memory
Controller no
snooping
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10Approved for Public Domain Release (VS07-0571)
2007 BAE Systems
All rights reserved
Programmable Multiplexer and A/D Converter
Analog Multiplexer with programmableinput configurations, supporting single-
ended, differential, or mixed input signals
Select signals controlled from Analog I/O
Control digital core
12-bit Pipeline A/D converter with 1.5 bits per
stage (single stage shown) High performance Sample and Hold circuit with
Operational Transconductance Amplifiers
Digital error correction tolerates 500 mV of
comparator offset
Supported by Bandgap Reference circuit to
generate differential reference voltage
All (48)
Single
Ended
Inputs
All (24)
Differential
Inputs
32 SingleEnded
And 8
Differential
16 SingleEnded
and 16
Differential
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11Approved for Public Domain Release (VS07-0571)
2007 BAE Systems
All rights reserved
Wilkinson Architecture Three Channel D/A Converter
Wilkinson D/A
converter architecture Shared ramp
generator and digital
counter
Repeated
comparators and
track and hold amps
Pipelined gray code
digital counter uses
4,096 cycles for 12 bit
resolution @ 1 Ksps
Track and Hold
samples ramp voltage
when comparatorpulses
Minimal die and power
dissipation for low
speed conversion
Ramp
Generator
Digital
Counter
Track
and Hold
Amplifier
Digital
Comparator
Track
and Hold
Amplifier
Track
and Hold
Amplifier
Digital
Comparator
Digital
Comparator
12
12-bit
digital
inputs
12
4.125 MHz clock
Initiate
conversion
Analog
out
Analog
out
Analog
out
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12Approved for Public Domain Release (VS07-0571)
2007 BAE Systems
All rights reserved
Analog Circuit Test Chips
BGR
DAC
AnalogMultiplexer
Pipeline A/D Converter test chip Wilkinson D/A Converter, analog
multiplexer, and Bandgap Reference
test chip
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15Approved for Public Domain Release (VS07 0571)
2007 BAE Systems
All rights reserved
Summary
The RAD6000MC is a flexible microcontroller supported by a robust set of
digital and analog interfaces
A redundant MIL-STD-1553 is provided, with embedded SRAM that can
be used elsewhere if the interface is not used
A SpaceWire router with 4 serial links and dual internal ports is provided
for high speed transfer with minimal connections
A 64-bit PCI interface offers increased parallel bus throughput
Analog/Digital conversion is supported by a programmable multiplexer
A novel approach was employed to achieve multiple channels ofDigital/Analog conversion with very low power dissipation
Enhancements have been made to address previous limitations in the
RAD6000 microprocessors addressable memory space
The ASIC is built around a reusable core architecture and heavily leverages
reuse of validated and flight proven designs
RAD6000MC configuration can be matched to user applications, optimizingfeatures and power dissipation