Slide 1-1

Sequential Circuits

• Prelim on delays and performance• Sequential circuits

– CLU with feedback loops

– Bi-stable (aka S-R flip-flop)

– Next time:• Application of flip-flops

• Clocked flip-flops, clocked D-flip-flops

• Level-triggered, edge-triggered, master-slave flip-flops

Digital Techniques Fall 2007 André Deutz, Leiden University

Slide 1-2

The Inverter at the Transistor Level

Transistor symbol

Powerterminals

A transistor used as an inverter

Inverter transferfunction

(a) (b) (c) (d)

A A

BaseEmitterCollector

GND = 0 V

VCC = +5 VVCC

A

A

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

00.2 0.4 0.6 0.8

Vin– Input voltage– V

Vo

ut–

Out

put

v olta

ge–

V

Output voltage vs. Input voltage

1 1.2 1.4 1.6 1.8 20

Vout

VCC

Vin

RL

VCC = 5 VRL = 400

(Compare to our relay implementation of the inverter.)

Slide 1-3

Assignments of Logical 0 and Logical 1 to Voltage Ranges

(a) At the output of alogic gate

(b) At the input to alogic gate

Logical 1

Logical 0

+5 V

2.4 V

0.4 V0 V

Logical 1

Logical 0

+5 V

2.0 V

0.8 V

0 V

Forbidden range Forbidden range

Slide 1-4

Assignments of Logical 0 and Logical 1 to Voltage Ranges

(a) At the output of alogic gate

(b) At the input to alogic gate

Logical 1

Logical 0

+5 V

2.4 V

0.4 V0 V

Logical 1

Logical 0

+5 V

2.0 V

0.8 V

0 V

Forbidden range Forbidden range

Slide 1-5

Speed and Performance

• The speed of a digital system is governed by – the propagation delay through the logic gates and

– the propagation across interconnections.

Slide 1-6Propagation Delay for a NOT Gate

+5 V

0 V

+5 V

0 V

10%

The NOTOutput changes From 0 to 1

50%(2.5 V) 90%

10%50%(2.5 V)

90%

The NOTOutput changes From 1 to 0

Propagation Delay(Latency)

Time

Transitio

n Time

Transitio

n Time

(Rise time)

(Fall time)

Slide 1-7If you don’t believe in delays: think again (“nothing” is

instantaneous)

Digital Techniques Fall 2007 André Deutz, Leiden University

Switches in series => AND

Input 1 Input 2

Current / no current

Slide 1-8

Sequential Logic

• The combinational logic circuits we have been studying so far have no memory. The outputs always follow the inputs.

• There is a need for circuits with a memory, which behave differently depending upon their previous state.

• An example is the vending machine, which must remember how many and what kinds of coins have been inserted, and which behave according to not only the current coin inserted, but also upon how many and what kind of coins have been deposited previously.

• These are referred to as finite state machines, because they can have at most a finite number of states.

Slide 1-9 Classical Model of a Finite State Machine

io

ik

Synchronizationsignal

fo

State bits

fmCombinationallogic unit

Qn

sn

Delay elements (one per state bit)

Inputs Outputs

Dn

Q0

s0

D0

. . .

. . .

. . .

. . .

. . .

Slide 1-10

Feedback paths in a logic circuit

Digital Techniques Fall 2007 André Deutz, Leiden University

XY

XY Z

Slide 1-11

Feedback paths in a logic circuitS

R

Q

Q

AB

F = A + B

NOR

A B F

0 0 1

0 1 0

1 0 0

1 1 0

1

Slide 1-12

Digital Techniques Fall 2007 André Deutz, Leiden University

S-R flip-flop (aka bi-stable)• In which state can the S-R flip-flop

be?

– S=0 & R=0

• Q=0, Q` = 0 ?

• Q=0, Q` = 1 ?

• Q=1, Q` = 0 ?

• Q=1 , Q` =1 ?

– S=0 & R=1

• Q=0, Q` = 0 ?

• Q=0, Q` = 1 ?

• Q=1, Q` = 0 ?

• Q=1 , Q` =1 ?

Slide 1-13

Digital Techniques Fall 2007 André Deutz, Leiden University

S-R flip-flop (aka bi-stable)• In which state can the S-R flip-flop

be?

– S=1 & R=0 (use symmetry)

• Q=0, Q` = 0 ?

• Q=0, Q` = 1 ?

• Q=1, Q` = 0 ?

• Q=1 , Q` =1 ?

– S=1 & R=1

• Q=0, Q` = 0 ?

• Q=0, Q` = 1 ?

• Q=1, Q` = 0 ?

• Q=1 , Q` =1 ?

Digital Techniques Fall 2007 André Deutz, Leiden University

Slide 1-14

S-R flip-flop (aka bi-stable)• S and R are predominantly 0• Summary: When setting S to 1 momentarily, the latch ends up in state

Q=1, regardless of the previous state; when S drops back to 0 state will stay Q=1. Likewise, setting R to 1 momentarily forces the latch to Q=0. (When R=S=0, then Q=1 or Q=0 (both are stable) – if you never allow R=S=1, then Q=1 in case S was the most recent input set to 1; otherwise R was the most recent input set to 1.

• Thus S-R is a rudimentary 1-bit memory• S == set; R == reset (aka clear)• We have tacitly assumed that the NOR gate has delays! • State S=R=1 and Q=Q’=0 is stable – one of the troubles with this is that

we cannot predict anymore what happens when S and R return to 0.

Digital Techniques Fall 2007 André Deutz, Leiden University

Slide 1-15

A NOR Gate with a Lumped Delay

This delay between input and output is at the basis of the functioning the flip-flop (= important memory element)

A

B

A1

0

1

0

1

0

B

A + B

A + B

Timing behavior

Slide 1-16

An S-R Flip-Flop (a bi-stable)

The S-R flip-flop is an active-high (positive logic) device.

SQ

S

R

Timing behavior

QR

2

2

Q

Q

Qt St Rt Qi+1

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 (disallowed)

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 (disallowed)

Slide 1-17

Digital Techniques Fall 2007 André Deutz, Leiden University

Slide 1-18

Converting a NOR S-R to an NAND S-R

Active-highNOR Implementation

Push bubbles(DeMorgan’s)

Rearrangebubbles

Convertfrom bubblesto active-lowsignal names

SQ

QR

SQ

QR

QS

Q

QR

R

QS

Slide 1-19

A Circuit with a Hazard

It is desirable to be able to “turn off”the flip-flop so it does not respond tosuch hazards.

SC

B

AB

Q

A

QR

S

R

C

B

A

AB

Timing behavior

2

Glitch caused bya hazard

Q

Q

Slide 1-20

A Clock Waveform

In a positive logic system, the “action” happens when the clock is high, or positive. The low part of the clock cycle allows propagation between subcircuits, so their inputs are stable at the correct value when the clock next goes high.

Cycle time = 25 ns

Time

Am

plitu

de

Slide 1-21

A Clocked S-R Flip-Flop

The clock signal, CLK, turns on the inputs to the flip-flop.

S

CLK

Q

Q

R

R

S

CLK

Timing behavior

3

2

Q

Q

Slide 1-22

A Clocked D (Data) Flip-Flop

D

CLK

Symbol

Q

Q

Circuit

D

CLK

Timing behavior

2

2

Q

Q

D Q

C Q