Slide 1 / 14PSFEB Status ReportLHCb Team @ Clermont

Production Test preview of the PreShower Front-End Boards

February the 1rst, 2007

Slide 2 / 14PSFEB Status ReportLHCb Team @ Clermont

Production Test organisation

Interface automated tests :

Manual interventions :DAQ test with Analogic Wave Generator (sine signal)

Long term tests:

Provide dedicated data-sheets for valid boards

• I2C communication

• Phasers

• Connectivity

• Algorithm

•Characteristics measure- Measure the offsets- Bit Flip Rate failure for TrigPGA- AOB ?

Pedestal fluctuations …

Slide 3 / 14PSFEB Status ReportLHCb Team @ Clermont

Production Test Interface (1/3)

2. Fill the header part

1. Initialize the VME crate-‘Resman’ program (Resource Manager)- a simple test : flickering the memory board LEDs

3. Load a list of processes from an option file

Compulsory steps for launching the test (enabling the GO button)

- the board ID number- user name (to choose in a list)- PC DNS name- the crate used- CAT release (is automatically set)

‘Track test conditions’

Slide 4 / 14PSFEB Status ReportLHCb Team @ Clermont

Production Test Interface (2/3)

Possibility to change easily some test parameters from the interface (title, number of events, threshold)

A board is rejected if for one process : number of errors > threshold

A board is accepted if for all processes : number of errors <= threshold

Slide 5 / 14PSFEB Status ReportLHCb Team @ Clermont

Production Test Interface (3/3)

Slide 6 / 14PSFEB Status ReportLHCb Team @ Clermont

List of processes file

Name of the CAT process

Name of the CAT element which will be tested by the process

Title of the process in the Production Test

interface

Number of events, threshold

Delay (ms) applied just before the

process runningName of the

specific log file for the process

Possibility to reset GLUE or SPECS Mezzanine before

the process running

Slide 7 / 14PSFEB Status ReportLHCb Team @ Clermont

Log outputs

C:

LHCb

CAT

CATLPC

Production

001

Number of the board

001 directory

Detailed log file for each

process

Global log file

Explicit ASCII data filesCollected in separate folders

Slide 8 / 14PSFEB Status ReportLHCb Team @ Clermont

Log outputs : html browser

C:

LHCb

CAT

CATLPC

Production

001

Number of the board

001

Parse the log files to .html

Parsed global log file

Provide an html browser for log files

TODO: index.html with boards status summary +link to logs & data sheets

Index.html

Slide 9 / 14PSFEB Status ReportLHCb Team @ Clermont

Log outputs : html browser

Quick status

Expanded status

Popup link to detailed log

Slide 10 / 14PSFEB Status ReportLHCb Team @ Clermont

Table of processes & timing (1/2)

• I2C communicationI2C communication

8 FePGA registers 8x1000 8 FePGA parameters 8x100 TrigPGA registers 1000 TrigPGA injection RAM 3 SEQ 1000 3 delay chips 3x1000

4min30s

• Phaser 1Phaser 1

SPD 1 TOP neighbours 1 ECAL 1

1min

• Intraconnectivity FePGA - TrigPGAIntraconnectivity FePGA - TrigPGA

PS & SPD, 4 Mapping 2x4x5 2min

Slide 11 / 14PSFEB Status ReportLHCb Team @ Clermont

Table of processes & timing (1/2)

• Connectivity with other boardsConnectivity with other boards

Inputs : SPD, ECAL add & BCID, Top & Right neighbours Outputs : multiplicity, TVB clusters, Bottom & Left neighbours

5 evts

30s

• FePGA algorithmsFePGA algorithms

•TrigPGA algorithmsTrigPGA algorithms

Offsets + Trigger bits : 8x5 Gain + Trigger bits : 8x5 Alpha + Trigger bits : 8x5

4min

Global tests with RAMs+ 4 mapping 4x5+ 2 inversion 4x5

3min30

Total duration : 16min

“offset computation” & “bit flip rate determination” processes haven’t been implanted in this

protocol yet.

Slide 12 / 14PSFEB Status ReportLHCb Team @ Clermont

Results of the production test for boards 001 & 002

Board 001(TrigPGA APA 450)

Output Left PS neighbours : 4% error rate on bit #6 (after mapping)Details in ‘TestCONNECT_OUTPUT_neighbours.dat’

Bit Flip Rate threshold : 18%Offsets : ?

Board 002(TrigPGA APA 600)

OK (?)Bit Flip Rate threshold : 18%Offsets : ?

Interface automated tests :

+known issues : phasers blocking

Manual interventions :

DAQ test with Analogic Wave Generator (sine signal) ?

Long term tests:Pedestal fluctuations : ?

Slide 13 / 14PSFEB Status ReportLHCb Team @ Clermont

Documentation

• An illustrated user guide • A brief list of the processes• A description of each process

To be achieved

Slide 14 / 14PSFEB Status ReportLHCb Team @ Clermont

SUMMARY

Tasks to be done :

• Implant “offset computation” & “bit flip rate determination” processes into the production test interface DONE

• AWG : GPIB issues

• update “pipeline registers test” processes for completing the current list

• test the next release of the TrigPGA and write a process for testing its new functionality Messy I/Os

• web access for the board datasheets ongoing …

• complete the documentation

A first catalog of processes is available for testing the pre-series boards !

Current list of processesI2C Communication

PROCESS NAME ELEMENT TYPE CATProc FILE INFO Specific devices STATUS

PsFePGA_I2C PS_FE_PGA PsFEPGA_I2C.cpp Configuration registers: Takes into account the FEPGA release version.

OK

PsFePGA_I2C_PAR PS_FE_PGA PsFEPGA_I2C_PAR.cpp FE-PGA Configuration parameters OK

PsFePhaser_I2C Phaser 0, 1, 2 PsFePhaser_I2C.cpp OK

Test I2C Ps_SeqPGA Seq_PGA PsFeSeq_I2C.cpp OK

PSTrigPGA_I2C_INJRAM PsTrig_PGA PsTrigPGA_I2C_INJRAM.cpp OK

PSTrigPGA_I2C_CONFIG PsTrig_PGA PsTrigPGA_I2C_CONFIG.cpp TRIG Configuration parameters OK

ConnectivityPROCESS NAME ELEMENT TYPE CATProc FILE INFO Specific devices STATUS

Test_Connectivity FEPGA – TRIGA PS bits + 4 mapping type

FEB PsTrigPGA_PROC_IntraConnectivity.cpp Test FE-TRIG intra connectivity + mappings algorithms

OK

Test_Connectivirt FEPGA – TRIGA SPD bits + 4 mapping type

PsTrigPGA_PROC_IntraConnectivity.cpp OK

INPUT : SPD + RIGHT NEIGHBOURS

FEB PsTrigPGA_PROC_InputTest.cpp FEB I/Os Mem. Boards OK

INPUT : ECAL addresses OK

INPUT : ECAL BCID OK

INPUT : TOP OK

INPUT : RIGHT CORNER OK

OUTPUT : multi, ECAL addresses, BCIDs

OK

OUTPUT : neighbours OK

OUTPUT : VAL1 & VAL2 OK

Current list of processes

Phaser TestPROCESS NAME ELEMENT TYPE CATProc FILE INFO Specific devices STATUS

Phaser 1 test : ECAL FEB PsTrigPGA_PhaserTest Mem. Boards OK

Phaser 1 test : SPD FEB PsTrigPGA_PhaserTest OK

Phaser 1 test : TOP neighbours FEB PsTrigPGA_PhaserTest OK

DAQ AlgorithmsPROCESS NAME ELEMENT TYPE CATProc FILE INFO Specific devices STATUS

PsFePGA_PROC_OFFSET PS_FE_PGA PsFe_PGA_PROC_OFFSET.cpp injRAM, acqRAM + chan. B OK

PsFePGA_PROC_GAIN PS_FE_PGA PsFe_PGA_PROC_GAIN.cpp OK

PsFePGA_PROC_ALPHA PS_FE_PGA PsFe_PGA_PROC_ALPHA.cpp OK

Trigger AlgorithmsPROCESS NAME ELEMENT TYPE CATProc FILE INFO Specific devices STATUS

Global Process FEB PsTrigPGA_PROC_GlobalProcess.cpp injRAM, acqRAM + chan. B OK

Global Test with Memory Boards FEB PsTrigPGA_PROC_GlobalProcessWithTB.cpp

Mem. Boards OK, to include

Full DAQ PathPROCESS NAME ELEMENT TYPE CATProc FILE INFO Specific devices STATUS

Ps Offset Calculation FEB PsPedestals.cpp Pedestals measurement OK, to include

DAQ through ACQRAM FEB PSFEB_ACQRAM.cpp Data acquired with CROCs SPYRAM

AWG GPIB issue ?

Ps_data acqusition DAQ PSAcquisition.cpp Data acquired with CROCs SPYRAM