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Lp trnh VHDLwww.viethung-idt.com.vn
Ni dungGii thiu VHDL1Cu trc lp trnh2Cc i tng3Cc kiu d liu4Cc php ton5Cc mnh tun t6DES vi VHDL7AES vi VHDL8
I. Gii thiu VHDLL ngn ng m phng v tng hp phn cngVHSIC Hardware Description LanguageVHSIC = Very High Speed ICng dngPLD (Programmable Logic Device)CPLD (Complex PLD)FPGA (Field Programmable Gate Array)ASIC (Application-Specific IC)Cng c Xilinx ISE v Altera Quartus
I. Gii thiu VHDL (tip)c im ngn ngKhng phn bit ch hoa thngCc lnh c phn cch bi du ;Cc ch thch c bt u bi du --
M phng phn cng theo hng Top-downYu cu cht ch v kiu d liu
Ni dungGii thiu VHDL1Cu trc lp trnh2Cc i tng3Cc kiu d liu4Cc php ton5Cc mnh tun t6DES vi VHDL7AES vi VHDL8
II. Cu trcLibraryLibrary cha cc php ton c xy dng sn trn 1 kiu d liu no .EntityEntity th hin giao din bn ngoi ca vi mch (cc cng vo/ra).ArchitectureArchitecture th hin cu trc bn trong, chc nng, hot ng ca vi mch.
II. Cu trc (tip)LIBRARY IEEE;USE ...;--------------------ENTITY Example IS GENERIC (...); PORT (...);END Example;--------------------ARCHITECTURE Ex1 OF Example IS COMPONENT (...); GENERIC MAP (...); PORT MAP (...); BEGIN Process(...); End Process;END Ex1;
ARCHITECTURE Ex1 OF Example IS...END Ex2;
II.1. LibraryCc thnh phn (package) ca th vin chun IEEE:Dng chung vi tt c cc cng c lp trnh.IEEE cng khai m ngun ca th vin ny.Cc cng c pht trin ca cc hng khc nhau c th c th vin ring.
-- Cc th vin ny c khai bo sn khi to ProjectLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;
II.2. EntityXc nh: s lng, chiu, kiu cc cng vo/ra v mt s tham s khc.-- Entity DeclarationENTITY Adder IS GENERIC (iCount : INTEGER); PORT (A : IN STD_LOGIC_VECTOR(15 downto 0); B : IN STD_LOGIC_VECTOR(15 downto 0); S : OUT STD_LOGIC_VECTOR(15 downto 0); C : OUT STD_LOGIC);END Adder;
II.3. ArchitectureGia 2 t kha Architecture v Begin l khai bo, lit k cc phn t bn trong ca vi mch, bao gm:Tn hiu (signal)Thnh phn (component)Gia 2 t kha Begin v End l on m m t kt ni gia cc thnh phn bn trong v hot ng ca vi mch.
II.3. Architecture (tip)
Cng 1 Entity ta c th nh ngha nhiu Architecture khc nhau. Tuy nhin, 1 Architecture ch gn vi mt Entity xc nh.-- Architecture BodyARCHITECTURE Adder16 OF Adder IS
signal Cr : STD_LOGIC_VECTOR(16 downto 0);
BEGIN ... PROCESS (...) ... END PROCESS;END Adder16;
II.4 Khi nim ProcessCc cu lnh nm ngoi Process c thc hin ng thi (concurrent)Cc cu lnh nm trong Process c thc hin tun t (sequential)Process c kch hot khi 1 trong cc tn hiu trong sensitivity list thay i gi tr.Cc tn hiu trong sensitivity list thng l cc tn hiu u vo ca vi mch.PROCESS (Clk, Rst,...) ...END PROCESS;
II.4 Khi nim Process (tip)Nu c nhiu Process th cc Process ny c thc hin ng thi chuyn gi tr t mt process sang mt process khc ta phi dng tn hiu (signal)
Ni dungGii thiu VHDL1Cu trc lp trnh2Cc i tng3Cc kiu d liu4Cc php ton5Cc mnh tun t6DES vi VHDL7AES vi VHDL8
III. Cc i tng trong VHDLComponent: Mt thit k VHDL hon chnh c th c chia thnh nhiu thnh phn nh hn.Signal: biu din dy ni, kt ni cc cng ca cc thnh phn vi nhau.tn hiu ch i gi tr khi kt thc 1 chu k lnh v yu cu v ng b
III. Cc i tng trong VHDL (tip)Variable: l cc bin c s dng tnh ton, lu cc gi tr trung gian.bin nhn gi tr ngay khi c gn, gi tr mi ny c th c s dng ngay trong dng lnh tip theobin ch s dng c trong phm vi Process
III. Cc i tng trong VHDL (tip)KeyPlain DataClkCipher
Component_1
Component_2EncryptorKey_InKey_OutKey_InKey_1_2Clk1
III. Cc i tng trong VHDL (tip)
III. Cc i tng trong VHDL (tip)Architecture Example1 of Example is
-- Khai bo cc thnh phnComponent Component_1 Port ( Clk1: in std_logic; Key_In: in std_logic_vector(1 to 32); Key_Out: out std_logic_vector(1 to 32));End Component;...-- Khai bo tn hiu...-- Khai bo cc kt ni...-- M t hot ng...
End Example1
III. Cc i tng trong VHDL (tip)Architecture Example1 of Example is
-- Khai bo cc thnh phn...-- Khai bo cc tn hiusignal Key_1_2: std_logic_vector(1 to 32);
-- Khai bo cc kt ni...-- M t hot ng...
End Example1-- C th gn tr mc nh cho tn hiu khi khai bosignal wire: std_logic := 1;signal bus: std_logic_vector(3 downto 0) := 1010;
III. Cc i tng trong VHDL (tip)Architecture Example1 of Example is
-- Khai bo cc thnh phn...-- Khai bo cc tn hiu...-- Khai bo cc kt niCom1: Component_1Port map (Clk => Clk1, Key_In => Key, Key_Out => Key_1_2);-- M t hot ng...
End Example1
III. Cc i tng trong VHDL (tip)Architecture Example1 of Example is-- Khai bo cc thnh phn...-- Khai bo cc tn hiu...-- Khai bo cc kt ni...-- M t hot ngBegin Process (...) variable i: integer range 0 to 15; constant pi: real := 3.14; Begin ... End ProcessEnd Example1
III. Cc i tng trong VHDL (tip)GenericS dng Generic cho php khai bo cc tham s chung c th s dng mt cch linh hot, mm do trong nhiu tnh hung.Generic l thnh phn khng bt buc trong thit k VHDL.Entity Example is Generic (iCount: integer; iTime: time); Port (...); End Example;
III. Cc i tng trong VHDL (tip)LIBRARY IEEE;Use IEEE.std_logic_1164.ALL;
ENTITY Example IS GENERIC (rise, fall: time; load: integer); PORT (inA, inB, inC, inD: In std_logic; out1, out2: Out std_logic);END Example;
ARCHITECTURE Ex1 OF Example ISCOMPONENT Com1 GENERIC (rise, fall: time:= 10 ns; load: integer:= 0); PORT (a, b: In std_logic; c: Out std_logic);END COMPONENT;
BEGINU1: Com1 GENERIC MAP (10 ns, 12 ns, 3); PORT MAP (inA, inB, out1);U2: Com1 PORT MAP (inC, inD, out2);END Ex1;
Ni dungGii thiu VHDL1Cu trc lp trnh2Cc i tng3Cc kiu d liu4Cc php ton5Cc mnh tun t6DES vi VHDL7AES vi VHDL8
IV. Cc kiu d liubit, bit_vectorthng dng nh ngha bin (variable)ch nhn cc gi tr 0, 1std_logic, std_logic_vectorthng dng nh ngha tn hiu (signal)nhn cc gi tr: U (Uninitialized), 0, 1,X (Forcing Unknown), Z (High Impedance),booleantrue, false
IV. Cc kiu d liu (tip)Integer32 bit (-2,147,483,647 ... +12,147,483,647)a := 1; a := -1; -- nga := 1.0; -- saiReal32 bit (-10^38 ... +10^38) chnh xc: 7 ch s phn thp phna := 1; a := -1; -- saia := 1.0; -- nga := -1.0E10; a := 1.5E-20; -- ng
IV. Cc kiu d liu (tip)Kiu d liu t nh ngha1. Kiu d liu lit kThng dng khi m t trng thi2. Kiu d liu mng 1 chiuTYPE MyState IS : (Start, S1, S2, S3, Stop);...variable S : MyState;...S := S1;TYPE MyRegister IS ARRAY (0 to 255) OF INTEGER;...variable R : MyRegister;...R(1) := 1;
IV. Cc kiu d liu (tip)Kiu d liu t nh ngha3 Kiu d liu mng nhiu chiuThng dng vi chc nng bng tra gi tr (Lookup Table)
TYPE LUT IS ARRAY(0 TO 3, 0 TO 3) OF std_logic;...constant MyLUT : LUT := ((0, 0, 0), (0, 0, 0), (0, 0, 1));
IV. Cc kiu d liu (tip)TimeThi gian l kiu d liu vt l duy nht c nh ngha sn trong VHDLDng xc nh tr v ng b tn hiu (vi t kha wait)n v: fs, ps, ns, us, ms, sec, min, hr
variable T : time;...T := 1 ns;
IV. Cc kiu d liu (tip)C th ni: khng c khi nim p kiu trong VHDL. Mt s ngoi l:integer +/- bit_vector/std_logic_vectorXt v d:
TYPE long is integer range -100 to 100;TYPE short is integer range -10 to 10;Signal x: short;Signal y: long;...
y
IV. Cc kiu d liu (tip) chuyn i kiu d liu, c 2 cch:T vit mt on m chuyn d liu.Khai bo th vin v dng hm c sn.Gi std_logic_arith trong th vin IEEE c mt s hm chuyn i kiu d liu:conv_integer(p)conv_unsigned(p, b)conv_signed(p, b)conv_std_logic_vector(p, b)
Ni dungGii thiu VHDL1Cu trc lp trnh2Cc i tng3Cc kiu d liu4Cc php ton5Cc mnh tun t6DES vi VHDL7AES vi VHDL8
V. Cc php ton (tip)Php ton logicTon t: and or not xor nor nand xnorTon hng: boolean, bit, bit_vector, std_logic, std_logic_vectorCc ton hng vector phi cng kch thc v php ton c thc hin trn cc bit tng ng
V. Cc php ton (tip)Php ton so snhTon t: =, /=, =Tr v gi tr boolean (true/false)Php ton s hc*, /, ** (exp) ch dng vi integer, real, time.mod, rem ch dng vi integer.+,- dng vi c integer, real, time v bit_vector, std_logic_vector+,- cho php 1 ton hng integer v 1 ton hng bit_vector/std_logic_vector (THB)
V. Cc php ton (tip)Php ton shift (dch bit)Ton t: sll, srl, sla, sra, rol, rorTon hng tri: bit_vector/std_logic_vectorTon hng phi: integersignal DI : bit_vector (7 downto 0) := 11000110;signal DO : bit_vector (7 downto 0);
V d 1: (tr li)ENTITY Adder IS PORT (B : IN STD_LOGIC_VECTOR(15 downto 0); A : IN STD_LOGIC_VECTOR(15 downto 0); S : OUT STD_LOGIC_VECTOR(15 downto 0); C : OUT STD_LOGIC);END Adder;
ARCHITECTURE Adder16 OF Adder ISsignal Cr : STD_LOGIC_VECTOR(16 downto 0);BEGIN PROCESS (A, B) variable i : integer; Begin Cr(0)
V d 2: (cu hi)Xy dng b nhn 2 s 8bit i vi kiu std_logic_vector.(phn tr litham khom ngunkm theo)
V d 3: (cu hi)Xy dng b chia chia s 16bit cho s 8bit i vi kiu std_logic_vector.
Bi tp 1:Xy dng b cng 2 s du phy ng(hc vin t tm hiu s du phy ng)
Bi tp 2:Xy dng b nhn 2 s du phy ng(hc vin t tm hiu s du phy ng)
Ni dungGii thiu VHDL1Cu trc lp trnh2Cc i tng3Cc kiu d liu4Cc php ton5Cc mnh tun t6DES vi VHDL7AES vi VHDL8
VI. Cc mnh tun t1. IF2. CASE3. LOOPFor ... LoopWhile ... Loop4. WAITWait on ...Wait for ...Wait until ...
VI.2. Mnh CASE (tip)Ta c th s dng 1 di gi tr hu hn trong biu thc logic ca mnh CASE hoc IF.if (x = 12 to 14) then...end if;
case (D_In) is when 1000 to 1010 => ... ...end case;
VI.2. Mnh CASE (tip)Kt qu sai l do hin tng chp mch (short-circuit) khi tng hp.Thc t c rt nhiu tn hiu nhn gi tr t nhiu ngun (source) khc nhau (ngun tn hiu ca S l A, B, C, D).Cch x lNgi thit k/lp trnh phi phn gii gi tr t nhiu ngun khc nhau tn hiu ch nhn 1 gi tr duy nht ti 1 thi im (multi-source - single-driver).
VI.3. Mnh LOOP (tip)Dng vng lp ang thc hin d chuyn sang vng lp tip theo: NEXT.Dng vng lp ang thc hin d v thot hn khi vng lp: EXIT.C th c nhiu vng lp lng nhau, nhng lnh Exit ch c tc dng i vi vng lp trc tip cha n.
VI.4. Mnh WAITMnh WAIT dng tm dng Process trong mt khong thi gian no :Wait on tn_hiu_no__thay_i_gi_trWait until biu_thc_logic_nhn_gi_tr_trueWait for khong_thi_gian_xc_nhWait (khong_thi_gian_khng_xc_nh)
Wait on A, B;...Wait until Clk = 1;...Wait for 10 ns;...Wait;
VI.4. Mnh WAIT (tip)Khng phi tt c cc mnh VHDL u c th tng hp c.V d, wait for 10 ns l mt mnh thng dng trong m hnh ho, nhng n khng tng ng vi v cng khng th to ra mt phn t mc cng logic.
V d 4: (cu hi)Xy dng h dy on nhn xu 1101(phn tr li tham kho m ngun km theo)
Bi tp
Ni dungGii thiu VHDL1Cu trc lp trnh2Cc i tng3Cc kiu d liu4Cc php ton5Cc mnh tun t6DES vi VHDL7AES vi VHDL8
VII. M ha DES vi VHDLDES = Data Encryption StandardL thut ton m ha khi, lm vic vi khi d liu 64bit.Kha m ha 64bit (thc t ch c 56bit v 8bit cn li dng kim tra)V kha khng di, DES c ci tin thnh Triple_DES (thc hin DES 3 ln vi 3 kha)
VIII. M ha DES vi VHDL (tip)
VIII. M ha DES vi VHDL (tip)
VIII. M ha DES vi VHDL (tip)
Ni dungGii thiu VHDL1Cu trc lp trnh2Cc i tng3Cc kiu d liu4Cc php ton5Cc mnh tun t6DES vi VHDL7AES vi VHDL8
VIII. M ha AES vi VHDLAES = Advanced Encryption StandardL thut ton m ha khi, lm vic vi khi d liu 128bit.Kha m ha c th 128, 192 hoc 256bitc chnh ph Hoa K chnh thc s dng thay th Triple_DES.
VIII. M ha AES vi VHDL (tip)
VIII. M ha AES vi VHDL (tip)
VIII. M ha AES vi VHDL (tip)
VIII. M ha AES vi VHDL (tip)
VIII. M ha AES vi VHDL (tip)
So snh vi Embedded CVi x l, vi iu khin c sn tp lnh nn c th dng Embedded C lp trnh, cc lnh C s c dch sang ngn ng my dng nh phn.FPGA ch bao gm cc phn t Logic c bn nn phi s dng VHDL m phng v tng hp di dng ghp ni cc phn t logic.Lm vic vi VHDL i hi hiu su hn v cu trc v hot ng ca vi mch.
So snh vi VerilogGing nhau:Cng l ngn ng m phng v tng hp phn cng. C th so snh nh C++ v Java.Khc nhau:VHDL yu cu cu trc cht ch hn (c bit v kiu d liu) nn d pht hin li hn, tuy nhin li thng di dng hn v kh phn tch m ngun hn.VHDL c dng nhiu Chu u, Verilog c dng nhiu M (mc d c 2 u sinh ra M)
Ti liu tham khoVHDL Programming by Examples, Douglas L.Perry, McGraw Hill.Circuit Design with VHDL, Volnei A.Pedroni, MIT Press.1076 IEEE Standard VHDL Reference Manual, IEEE Computer Society.