Smart Card Reader 8-Bit OTP MCU with UART - · PDF fileP ll-high Resistors ... Internal Time...

Smart Card Reader 8-Bit OTP MCU with UART

HT56RU25

Revision: V1.10 Date: ne 0 01ne 0 01

Rev. 1.10 ne 0 01 Rev. 1.10 3 ne 0 01

HT56RU25Smart Card Reader 8-Bit OTP MCU with UART


Table of Contents

Features ............................................................................................................ 7General Description ......................................................................................... 8Block Diagram .................................................................................................. 8Pin Assignment ................................................................................................ 9Pin Description .............................................................................................. 10Absolute Maximum Ratings ...........................................................................11D.C. Characteristics ....................................................................................... 12A.C. Characteristics ....................................................................................... 14A/D Converter Electrical Characteristics ..................................................... 15Power-on Reset Characteristics ................................................................... 16DC/DC Converter and LDO Electrical Characteristics ............................... 16System Architecture ...................................................................................... 18

Clocking and Pipelining ......................................................................................................... 18Program Conter ................................................................................................................... 19Stack ..................................................................................................................................... 0Arithmetic and Logic Unit − ALU ........................................................................................... 1

Flash Program Memory ................................................................................. 21Strctre ................................................................................................................................ 1Special Vectors ..................................................................................................................... Look-p Table ........................................................................................................................ 3Table Program Example ........................................................................................................

Data Memory .................................................................................................. 25Strctre ................................................................................................................................ 5General Prpose Data Memory ............................................................................................ 6Special Prpose Data Memory ............................................................................................. 6

Special Function Registers Description ...................................................... 27Indirect Addressing Registers − IAR0, IAR1 ......................................................................... 7Memory Pointers − MP0, MP1 .............................................................................................. 7Bank Pointer − BP ................................................................................................................. 8Accumulator − ACC ............................................................................................................... 9Program Counter Low Register − PCL .................................................................................. 9Look-up Table Registers − TBLP, TBHP, TBLH ..................................................................... 9Status Register − STATUS .................................................................................................... 30Interrpt Control Registers .................................................................................................... 31Timer/Event Conter Registers ............................................................................................. 31Inpt/Otpt Ports and Control Registers ............................................................................. 31Plse Width Modlator Registers .......................................................................................... 31A/D Converter Registers − ADRL, ADRH, ADCR, ACSR ...................................................... 3Serial Interface Modle Registers ......................................................................................... 3

Rev. 1.10 ne 0 01 Rev. 1.10 3 ne 0 01



Port A Wake-up Register − PAWU ........................................................................................ 3Pull-High Registers − PAPU, PBPU, PCPU .......................................................................... 3Clock Control Register − CLKMOD ....................................................................................... 3Miscellaneous Register − MISC0, MISC1 ............................................................................. 3

Input/Output Ports ......................................................................................... 33Pll-high Resistors ................................................................................................................ 33Port A Wake-p ..................................................................................................................... 3Port A Open Drain Fnction .................................................................................................. 3I/O Port Control Registers ..................................................................................................... 3Pin-shared Fnctions ............................................................................................................ 35I/O Pin Strctres .................................................................................................................. 36Programming Considerations ................................................................................................ 37

Timer/Event Counters ................................................................................... 38Configuring the Timer/Event Counter Input Clock Source .................................................... 38Timer Registers − TMR0, TMR1L/TMR1H, TMR2, TMR3..................................................... 0Configuring the Timer Mode .................................................................................................. 1Configuring the Event Counter Mode .................................................................................... Configuring the Pulse Width Measurement Mode ................................................................. 3Programmable Frequency Divider − PFD ............................................................................. Prescaler ............................................................................................................................... I/O Interfacing ........................................................................................................................ 5Timer/Event Conter Pins Internal Filter ............................................................................... 5Programming Considerations ................................................................................................ 6Timer Program Example ....................................................................................................... 7

Pulse Width Modulator .................................................................................. 48PWM Overview ..................................................................................................................... 88+ PWM Mode Modlation .................................................................................................. 9PWM Otpt Control ............................................................................................................. 9PWM Register Pairs − PWMnH/PWMnL (n=0~3) ................................................................. 50PWM Programming Example ................................................................................................ 50

Analog to Digital Converter .......................................................................... 51A/D Overview ........................................................................................................................ 51A/D Converter Data Registers − ADRL, ADRH ..................................................................... 51A/D Converter Control Registers − ADCR, ADPCR, ACSR .................................................. 5A/D Operation ....................................................................................................................... 5A/D Inpt Pins ....................................................................................................................... 55Initialising the A/D Converter ................................................................................................. 55Programming Considerations ................................................................................................ 57A/D Programming Example ................................................................................................... 57A/D Transfer Fnction ........................................................................................................... 59

Rev. 1.10 ne 0 01 Rev. 1.10 5 ne 0 01



Serial Interface Function − SIM .................................................................... 60SPI Interface ......................................................................................................................... 60IC Interface .......................................................................................................................... 68IC Bs Commnication ........................................................................................................ 7

Peripheral Clock Output ................................................................................ 76Peripheral Clock Operation ................................................................................................... 76

Buzzer ............................................................................................................. 77PA0/PA1 Pin Fnction Control............................................................................................... 78

Interrupts ........................................................................................................ 79Interrpt Registers ................................................................................................................. 80Interrpt Operation ................................................................................................................ 8Interrpt Priority ..................................................................................................................... 85External Interrpt ................................................................................................................... 85External Peripheral Interrpt ................................................................................................. 87Timer/Event Conter Interrpt ............................................................................................... 87A/D Interrpt .......................................................................................................................... 88Smart Card Interrpt ............................................................................................................. 88Smart Card Insertion/Removal Interrpt ............................................................................... 88SIM (SPI/IC Interface) Interrupts .......................................................................................... 88Mlti-fnction Interrpt .......................................................................................................... 89Real Time Clock Interrpt ...................................................................................................... 89Time Base Interrpt ............................................................................................................... 91Programming Considerations ................................................................................................ 9

Reset and Initialisation .................................................................................. 93Reset Fnctions .................................................................................................................... 93Reset Initial Conditions ......................................................................................................... 95

Oscillator ........................................................................................................ 98System Clock Configurations ................................................................................................ 98 External Crystal/ Ceramic Oscillator − HXT ......................................................................... 98External RC Oscillator − ERC ............................................................................................... 99Internal High Speed RC Oscillator − HIRC ......................................................................... 100Internal Low Speed Oscillator − LIRC ................................................................................. 100External 32.768kHz Oscillator − LXT .................................................................................. 100External Oscillator − EC ...................................................................................................... 101Spplementary Oscillators .................................................................................................. 101

System Operating Modes ............................................................................ 102Clock Sorces ..................................................................................................................... 10Operating Modes ................................................................................................................. 105

Power Down Mode and Wake-up ................................................................ 106Power Down Mode .............................................................................................................. 106Entering the Power Down Mode ......................................................................................... 106Standby Crrent Considerations ......................................................................................... 106Wake-p .............................................................................................................................. 107

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Low Voltage Detector − LVD ....................................................................... 108LVD Operation ..................................................................................................................... 108

Watchdog Timer ........................................................................................... 109Watchdog Timer Operation ................................................................................................. 109Clearing the Watchdog Timer ...............................................................................................110

UART Interface ..............................................................................................111UART External Interface ......................................................................................................11UART Data Transfer Scheme...............................................................................................11UART Stats and Control Registers.....................................................................................11Bad Rate Generator ...........................................................................................................118UART Setp and Control..................................................................................................... 10UART Transmitter................................................................................................................ 11UART Receiver ................................................................................................................... 13Managing Receiver Errors .................................................................................................. 15UART Interrpt Strctre..................................................................................................... 16UART Power Down Mode and Wake-p ............................................................................. 17

Digital to Analog Converter − DAC ............................................................ 128Operation ............................................................................................................................ 18

DC/DC Converter and LDO ......................................................................... 129Smart Card Interface ................................................................................... 130

Interface Pins ...................................................................................................................... 130Card Detection .................................................................................................................... 131Internal Time Counter − ETU, GTC, WTC........................................................................... 131Elementary Time Unit − ETU .............................................................................................. 131Guard Time Counter − GTC ................................................................................................ 13Waiting Time Counter − WTC ............................................................................................. 133Smart Card UART Mode ..................................................................................................... 13Power Control ..................................................................................................................... 135Smart Card Interrpt Strctre ............................................................................................ 136Programming Considerations .............................................................................................. 137Smart Card Interface Stats and Control Registers ............................................................ 138

Configuration Options ................................................................................. 149Application Circuits ..................................................................................... 150Instruction Set .............................................................................................. 151

Introdction ......................................................................................................................... 151Instrction Timing ................................................................................................................ 151Moving and Transferring Data ............................................................................................. 151Arithmetic Operations .......................................................................................................... 151Logical and Rotate Operation ............................................................................................. 15Branches and Control Transfer ........................................................................................... 15Bit Operations ..................................................................................................................... 15Table Read Operations ....................................................................................................... 15Other Operations ................................................................................................................. 15

Rev. 1.10 6 ne 0 01 Rev. 1.10 7 ne 0 01



Instruction Set Summary ............................................................................ 153Table Conventions ............................................................................................................... 153

Instruction Definition ................................................................................... 155Package Information ................................................................................... 164

28-pin SSOP (150mil) Outline Dimensions ......................................................................... 16544-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions ........................................... 166

Rev. 1.10 6 ne 0 01 Rev. 1.10 7 ne 0 01



Features• Operatingvoltage:

♦ fSYS=32.768kHz:2.2V~5.5V♦ fSYS=4MHz:2.2V~5.5V♦ fSYS=12MHz:3.0V~5.5V♦ fSYS=20MHz:4.5V~5.5V

• Operatingcurrent:fSYS=1MHzat3V,170µA,typ.

• OTPProgramMemory:16K×16

• RAMDataMemory:1280×8

• 12levelssubroutinenesting

• Upto24bidirectionalI/Olines

• TinyPowertechnologyforlowpoweroperation

• Threepin-sharedexternalinterruptslines

• Three8-bitprogrammableTimer/EventCounterswithoverflowinterruptand7-stageprescaler

• One16-bitprogrammableTimer/EventCounterswithoverflowinterrupt

• ExternalCrystal(HXT),RC(ERC)and32.768kHz(LXT)crystaloscillators

• InternalhighspeedRCoscillator–HIRC

• FullyintegratedRC32kHzoscillator–LIRC

• Externallysuppliedsystemclockoption–EC

• WatchdogTimerfunction

• PFD/Buzzerforaudiofrequencygeneration–onlyavailablefor44-LQFPpackagetype

• DualSerialInterfaceModules(SIM):SPIandI2C

• 4operatingmodes:Normal,Slow,IdleandSleep

• 8-channel12-bitresolutionA/Dconverter–onlyavailablefor44-LQFPpackagetype

• 4-channel12-bitPWMoutputs–onlyavailablefor44-LQFPpackagetype

• 12-bitD/Aconverterwith8-levelvolumecontrol

• SmartcardinterfacecompatiblewithandcertifiabletotheISO7816-3standards

• DC/DCconverterandLDOfunction

• Lowvoltageresetfunction:2.1V,3.15V,4.2V

• Lowvoltagedetectfunction:2.2V,3.3V,4.4V

• Bitmanipulationinstruction

• Tablereadinstructions

• 63powerfulinstructions

• Upto0.2µsinstructioncyclewith20MHzsystemclockatVDD=5V

• Allinstructionsexecutedinoneortwomachinecycles

• Powerdownandwake-upfunctionstoreducepowerconsumption

• UARTInterfaceforfullyduplexasynchronouscomminucation

• Packagetype:28-pinSSOPand44-pinLQFP

Rev. 1.10 8 ne 0 01 Rev. 1.10 9 ne 0 01



General DescriptionTheTinyPowerTMA/DType8-bithighperformanceRISCarchitecturemicrocontrollerisspecificallydesigned forapplications that interfacedirectly toanalogsignals.Thedevice includesanalogfeaturessuchasanintegratedmulti-channelAnalogtoDigitalConverter,12-bitDigitaltoAnalogConverter,DC/DCConverterandLDO.

With their fully integratedSPIandI2Cfunctions,designersareprovidedwithameansofeasycommunicationwithexternalperipheralhardware.ThebenefitsofintegratedanalogfeaturessuchasA/D,D/A,etc.,andPWMfunctions,inadditiontolowpowerconsumption,highperformance,I/Oflexibilityandlow-cost,providesthedevicewiththeversatilityforawiderangeofproductsinthehomeapplianceandindustrialapplicationareas.Someoftheseproductscouldincludeelectronicmetering,environmentalmonitoring,handheldinstruments,electronicallycontrolledtools,motordrivinginadditiontomanyothers.

TheUARTmodule is contained in thisdevice. It can support the applications suchasdatacommunicationnetworksbetweenmicrocontrollers,low-costdatalinksbetweenPCsandperipheraldevices,portableandbatteryoperateddevicecommunication,etc.Thisdevicealso includesaSmartcard Interface,which iscompatiblewithandcertified to ISO7816standards, toprovidecommunicationwithvarioustypesofSmartCard.

TheuniqueHoltekTinyPower technologyalsooffers theadvantagesofextremely lowcurrentconsumptioncharacteristics,anextremely importantconsideration in thepresent trendfor lowpowerbatterypoweredapplications.TheusualHoltekMCUfeaturessuchaspowerdownandwake-upfunctions,oscillatoroptions,programmablefrequencydivider,etc.,combinetoensureuserapplicationsrequireaminimumofexternalcomponents.

Block Diagram

8-bitRISCMCUCore

Watchdog Timer

ResetCircit

Internal RC Oscillators

External XTAL/RC/EC

OscillatorsOTP

Program Memory

DataMemoryStack

External 3.768kHzOscillator

Low Voltage Reset

Interrpt Controller

Low Voltage Detect

D/AConverter

A/DConverter

OTP Programming

Memory

SIMs Timers UART SmartcardInterface

I/OPorts

PFD PWM

DC/DCConverterLDO

(＊) (＊)

(＊)

(*):Onlyavailablefor44-LQFPpackagetype.

Rev. 1.10 8 ne 0 01 Rev. 1.10 9 ne 0 01



Pin Assignment

HT56RU2544 LQFP-A

135678910

1 13115 1617 18 19 0 1

567893031333

3536373839013

AVSSVSS

LDOVSS

CR

STC

RD

VC

CLD

OIN

VO

CVSS

SELF

SELF

CC

8C

IO

CC

LK

PB0/SCK0/SCL0PB1/SDI0/SDA0PB/SDO0PB3PB/SDO1PB5/SDI1/SDA1PB6/SCK1/SCL1PB7/SCS1

PC6/PWM/PINT

PC/PWM0/SCS0

PA7/TM

R1/AN

7/VR

EFA

VDD

VDD

PA0/B

Z/INT0/A

N0

PA1/B

Z/INT1/A

N1

PC0/A

UD

/AN

PC

5/PWM

1/PCLK

PC/XT1

PC

1/PFD/A

N3

11

3

PC7/RES

3

PC3/XT

CC

NCNCNC

PA/OSC1PA3/OSC

CDET

PA/TM

R/TX/A

N

PA5/TM

R3/R

X/PW

M3/A

N5

PA6/TM

R0/A

N6

31019181716151

13

135678910111

HT56RU2528 SSOP-A

PA3/OSC CDET

CRDVCC

PC7/RES CC8CIOPA0/INT0CCCCLKCRST

PA1/INT1

LDOIN

LDOVSS

PA/TMR/TXPA5/TMR3/RX

PA7/TMR1VDD/AVDDVSS/AVSS

PA6/TMR0

PA/OSC1 SELF

VOCVSSSELF

5678

PB/SDO0PB1/SDI0/SDA0

PC/SCS0PB0/SCK0/SCL0

HT56RU25 28 SSOP-A

Rev. 1.10 10 ne 0 01 Rev. 1.10 11 ne 0 01



Pin DescriptionThefollowingtabledepictsthepinscommontoalldevices.

Pin Name I/O Configuration Option Description

Input/Output

PA0/BZ(*)/INT0/AN0(*) PA1/BZ(*)/INT1/AN1(*) PA/OCS1 PA3/OCS PA4/TMR2/TX/AN4(*) PA5/TMR3/RX/PWM3(*)/AN5(*) PA6/TMR0/AN6(*) PA7/TMR1/AN7(*)/VREF(*)

I/OBZ/BZ (*)

HXT or ERC or HIRC or EC

Bidirectional 8-bit inpt/otpt port. Each individal bit on this port can be configured as a wake-up input by the PAWU register control bit. Software instrctions determine if the pin is a CMOS otpt or Schmitt Trigger inpt. A pll-high resistor can be connected to each pin determined by the PAPU register.Port A is pin-shared with the A/D inpt pins. The A/D inpts are selected via software instrctions. Once a Port A line is selected as an A/D inpt the I/O fnction and pll-high resistor are disabled atomatically.The BZ/INT0 BZ/INT1, TMR2/TX, TMR3/RX/PWM3, TMR0 and TMR1 are pin-shared with PA0, PA1 and PA4~PA7 respectively.The OSC1 and OSC pins are connected to an external RC network or crystal determined by configration options for the internal system clock. If the RC system clock option is selected the OSC pin can be sed as an I/O pin. The internal system can come from the internal high speed RC oscillator, HIRC, which is selected by configuration options. When the HIRC is selected as the system oscillator the OSC1 and OSC pins can be sed as normal I/O pins. The abbreviation EC stands for External Clock mode. In the EC mode an external clock sorce is provided on OSC1 as the system clock.The VREF pin is the ADC reference voltage inpt pin. The “VREFS” bit in the ACSR register is sed to select either VREF or AVDD as the ADC reference voltage.

PB0/SCK0/SCL0 PB1/SDI0/SDA0 PB/SDO0 PB3 PB/SDO1 PB5/SDI1/SDA1 PB6/SCK1/SCL1 PB7/SCS1

I/O SIM0 SIM1

Bidirectional 8-bit inpt/otpt port. Software instrctions determine if the pin is a CMOS otpt or Schmitt trigger inpt. A pll-high resistor can be connected to each pin by the PBPU register.The SDO1, SDI1/SDA1, SCK1/SCL1 and SCS1 pins are the the SIM1 interface pins, pin-shared with PB4~PB7 respectively and enabled by a configration option as well as the SIM0 interface pins. When the configuration option enables the SIM function, the I/O fnction will be disabled.

PC0/AUD/AN(*) PC1/PFD(*)/AN3(*) PC2/XT1 PC3/XT2 PC/PWM0(*)/SCS0 PC5/PWM1(*)/PCLK PC6/PWM(*)/PINT

I/OPFD(*)

32.768kHz SIM0

Bidirectional 7-bit inpt/otpt port. Software instrctions determine if the pin is a CMOS otpt or Schmitt trigger inpt. A pll-high resistor can be connected to each pin determined by the PCPU register.The AUD pin is the adio otpt pin from the D/A Converter and pin-shared with PC0. When the D/A-Converter is enabled the PC0 I/O fnction will be disabled atomatically inclding any pll-high resistors. If the D/A Converter otpt AUD and the A/D Converter inpt AN are both enabled then the A/D converter otpt will be connected to the AN inpt channel allowing the D/A otpt to be measred by the A/D Converter.The PFD fnctional pin is pin-shared with PC1.The XT1 and XT2 are connected to a 32.768kHz crystal oscillator to form a clock sorce for fSUB or fSL.The PWM0 PWM1 and PWM pins are pin-shared with PC PC5 and PC6 respectively. PC is also pin-shared with SCS0 the chip select pin for the Serial Interface Modle 0.The PCLK is a peripheral clock output pin which is enabled by the “PCKEN” in the SIM0CTRL register and pin-shared with PC5.The PINT pin is the external peripheral interrpt pin and pin-shared with PC6.

Rev. 1.10 10 ne 0 01 Rev. 1.10 11 ne 0 01



Pin Name I/O Configuration Option Description

PC7/RES I/O RES

Schmitt Trigger reset inpt pin active low. The RES pin is pin-shared with PC7 whose fnction is determined by a configration option. When PC7 is configred as an I/O pin software instrctions determine if this pin is an open drain otpt or a Schmitt Trigger inpt withot pll-high resistor.

Power & GroundVDD P — Positive power spplyVSS P — Negative power spply grondAVDD P — Analog positive power spplyAVSS P — Analog negative power spply grondCVSS P — DC/DC Converter Negative power spply grondLDOVSS P — LDO Negative power spply grondISO 7816 - Smart Card InterfaceVO P — External diode connection pin for DC/DC converter

LDOIN P — LDO inpt voltage pinThis pin mst externally be connected to the VO pin

SELF P — External indctor connection pin for DC/DC converterThe two SELF pins shold externally be connected together

CRST O — Smart card reset otptCCLK O — Smart card clock otptCC I/O — Smart card C inpt/otptCC8 I/O — Smart card C8 inpt/otptCIO I/O — Smart card data inpt/otptCDET I — Smart card detection inpt

CRDVCC P — Positive power spply for external smart cardThe two CRDVCC pins shold externally be connected together

(*):Onlyavailablefor44-LQFPpackagetype.

Absolute Maximum RatingsSupplyVoltage................................................................................................VSS−0.3VtoVSS+6.0VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-40˚Cto85˚CIOHTotal....................................................................................................................................-80mAIOLTotal..................................................................................................................................... 80mATotalPowerDissipation........................................................................................................ 500mW

Note:Thesearestressratingsonly.Stressesexceeding therangespecifiedunder"AbsoluteMaximumRatings"maycausesubstantialdamagetothesedevices.Functionaloperationofthesedevicesatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicesreliability.

Rev. 1.10 1 ne 0 01 Rev. 1.10 13 ne 0 01



D.C. CharacteristicsTa=25°C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

Operating VoltageVDD Operating Voltage — — . — 5.5 VOperating Current

IDD1Operating Crrent (HXT, ERC OSC)

3V No load fSYS=fM=1MHz ADC off

— 170 50 µA5V — 380 570 µA

IDDOperating Crrent (HXT, ERC OSC)


— 0 360 µA5V — 90 730 µA

IDD3Operating Crrent (HXT, ERC, HIRC OSC)


— 0 660 µA5V — 900 150 µA

IDDOperating Crrent (EC Mode)

3V No load fSYS=fM=4MHz ADC and Clock input filter off

— 380 570 µA5V — 680 100 µA

IDD5Operating Crrent (HXT, ERC OSC)


— 700 1050 µA5V — 1300 1950 µA

IDD6Operating Crrent (HXT, ERC, HIRC OSC) 5V No load fSYS=fM=8MHz

ADC off — 1.8 .7 mA

IDD7Operating Crrent (HXT, ERC, HIRC OSC) 5V No load fSYS=fM=12MHz

ADC off — .6 .5 mA

IDD8Operating Crrent (HXT, ERC OSC) 5V No load fSYS=fM=20MHz

ADC off — 5.5 8.5 mA

IDD9

Operating Crrent (Slow Mode, fM=4MHz) (HXT, ERC, HIRC OSC)

3V No load fSYS=fSLOW=500kHz ADC off

— 150 0 µA

5V — 30 510 µA

IDD10


3V No load fSYS=fSLOW=1MHz ADC off

— 180 70 µA

5V — 00 600 µA

IDD11



— 70 00 µA

5V — 560 80 µA

IDD1



— 350 530 µA

5V — 700 1070 µA

IDD13



— 50 670 µA

5V — 890 130 µA

IDD1



— 500 900 µA

5V — 1000 1700 µA

IDD15Operating Crrent (fSYS=LXT or LIRC)

3V WDT off ADC offLXT in low power mode

— 8 16 µA5V — 15 30 µA

Standby Current

ISTB1Sleep Mode Standby Crrent (fM=4MHz HIRC, fSYS fSUB fS fWDT=off)

3V System HALT, WDT off, DC/DC converter off

— 0. 1.0 µA5V — 0.3 .0 µA

ISTB

Sleep Mode Standby Crrent (fM=4MHz HIRC, fSYS fWDT=fSUB=LXT or LIRC)

3V System HALT, WDT on, DC/DC converter off LXT in low power mode

— 1 µA

5V — 3 5 µA

Rev. 1.10 1 ne 0 01 Rev. 1.10 13 ne 0 01





ISTB3

Idle Mode Standby Crrent (fM=4MHz HIRC, fSYS=fM; fWDT fS=fSUB=LXT or LIRC)

3V System HALT, WDT off, SPI or IC on, PCLK on, PCLK=fSYS/8,LXT in low power mode

— 150 50 µA

5V — 350 550 µA

Input High/Low Voltage

VIL1Inpt Low Voltage for I/O Ports TMR and INT Pins — — 0 — 0.3VDD V

VIH1Input High Voltage for I/O Ports, TMR and INT Pins — — 0.7VDD — VDD V

VIL Input Low Voltage (RES) — — 0 — 0.VDD VVIH2 Input High Voltage (RES) — — 0.9VDD — VDD VSink/Source Current – GPIO

IOL1 I/O sink current (PA, PB, PC)3V

VOL=0.1VDD6 1 — mA

5V 10 5 — mA

IOH1 I/O source current (PA, PB, PC)3V

VOH=0.9VDD−2 −4 — mA

5V −5 −8 — mAIOL PC7/RES Sink Crrent 5V VOL=0.1VDD 3 — mASink/Source Currnt – Smartcard interface IO

IOL3 Card Clock (CCLK) Sink Current 5V

VO=5.5V

VCRDVCC=3V, VOL=0.1VCRDVCC0 — — µA

VO=5.5V VCRDVCC=5V, VOL=0.1VCRDVCC

60 — — µA

IOH3 Card Clock (CCLK) Source Current 5V

VO=5.5VVCRDVCC=3V, VOH=0.9VCRDVCC

0 — — µA


60 — — µA

IOL Card I/O (CIO) Sink Current 5V

VO=5.5VVCRDVCC=3V, VOL=0.1VCRDVCC

00 — — µA


600 — — µA

IOH4 Card I/O (CIO) Source Current 5V


15 — — µA


15 — — µA

IOL5Card Reset (CRST), C/C8 Sink Crrent 5V


00 — — µA


600 — — µA

IOH5Card Reset (CRST), C/C8 Sorce Crrent 5V


15 — — µA


15 — — µA

Pull-High Resistance

RPH1Pll-high Resistance for General I/O Ports & Card Detection (CDET)

3V—

0 60 80 kΩ5V 10 30 50 kΩ

RPH2 Pull-high resistance for Card I/O (CIO) 5V VO=5.5V, VCRDVCC=3V/5V 7.5 15.0 .5 kΩLVR/LVDVLVR1

Low Voltage Reset Voltage —LVR=2.1V Option 1.98 .10 . V

VLVR LVR=3.15V Option .98 3.15 3.3 VVLVR3 LVR=4.2V Option 3.98 .0 . V

Rev. 1.10 1 ne 0 01 Rev. 1.10 15 ne 0 01





VLVD1

Low Voltage Detector Voltage —LVD=2.2V Option .08 .0 .3 V

VLVD LVD=3.3V Option 3.1 3.30 3.50 VVLVD3 LVD=4.4V Option .1 .0 .70 V

VBG Bandgap reference with bffer voltage — — -3%× typ. 1. +3%×

typ. V

A.C. CharacteristicsTa=25°C



fSYS1System Clock (HXT, ERC, HIRC) —

2.2V~5.5V 00 — 000 kHz3.0V~5.5V 00 — 1000 kHz4.5V~5.5V 00 — 0000 kHz

fSYS System clock (LXT) — 2.2V~5.5V — 3768 — Hz

fMERC 4MHz External RC OSC 2.2V~5.5V

External RERC=150kΩ, Ta=0°C~70°C −7% +7% MHz

External RERC=150kΩ, Ta=-40°C~85°C −11% +11% MHz

fHIRC 4/8/12MHz Internal RC OSC

3V/5V Ta=25°C −2% +% MHz3V/5V Ta=25°C −2% 8 +% MHz

5V Ta=25°C −2% 1 +% MHz3V/5V Ta=0°C~70°C −5% +5% MHz3V/5V Ta=0°C~70°C −5% 8 +5% MHz

5V Ta=0°C~70°C −5% 1 +5% MHz2.2V~5.5V Ta=0°C~70°C −8% +8% MHz3.0V~5.5V Ta=0°C~70°C −8% 8 +8% MHz4.5V~5.5V Ta=0°C~70°C −8% 1 +8% MHz2.2V~5.5V Ta=−40°C~85°C −12% +1% MHz3.0V~5.5V Ta=−40°C~85°C −12% 8 +1% MHz4.5V~5.5V Ta=−40°C~85°C −12% 1 +1% MHz

fTIMER TMRn Inpt Freqency —2.2V~5.5V 00 — 000 kHz3.0V~5.5V 00 — 1000 kHz4.5V~5.5V 00 — 0000 kHz

fLIRC Internal 32kHz RC oscillator (LIRC) 5V 2.2~5.5V, Ta=25°C, after trimming 8.1 3.0 3. kHz

tRES External Reset Low Plse Width — — 10 — — µstINT Interrpt Plse Width — — 10 — — µs

tLVDS LVD Otpt Stable Time 5V LVR disable LVD enable Bandgap voltage ready — — 100 µs

tSST1System start-p timer period for HXT/LXT (without fast start-up) — Power on or wake p from

Idle mode 10 — — tSYS

tSSTSystem start-p timer period for HXT/LXT (with fast start-up) —

fSL=LXT — 1 tLXT

fSL=LIRC — 1 tLIRC

tSST3

System start-p timer period (Wake-up from HALT, fSYS on at HALT state)

— — — — tSYS

tSST System start-up timer period (Reset) — — 10 — — tSYS

Rev. 1.10 1 ne 0 01 Rev. 1.10 15 ne 0 01





tRSTD

System Reset Delay Time(Power On Reset, LVR reset, LVRC software reset WDTC software reset)

— — 5 50 100 ms

System Reset Delay Time(RES reset, WDT normal reset) — — 8.3 16.7 33.3 ms

tEERD EEPROM Read Time — — 1 tSYS

tEEWR EEPROM Write Timet — — 1 ms

Note:tSYS=1/fSYS,tLXT=1/fLXT,tLIRC=1/fLIRC

A/D Converter Electrical CharacteristicsTa=25°C



AVDD Analog operating voltage — VREF=AVDD 3.0 — 5.5 VVAD A/D Inpt Voltage — -pin LQFP 0 — VREF VVREF A/D Inpt Reference Voltage Range — AVDD=5V .1 — AVDD+0.1 V

DNL A/C Differential Non-Linearity — AVDD=5V, VREF=AVDD tAD=0.5µs −2 — LSB

INL ADC Integral Non-Linearity — AVDD=5V, VREF=AVDD tAD=0.5µs −4 — LSB

IADCAdditional Power Consmption if A/D Converter is Used

3V—

— 0.50 0.75 mA5V — 1.00 1.50 mA

tAD A/D Converter Clock Period — — 0.5 — 10 µs

tADCA/D Conversion Time (Include Sample and Hold Time) — 1-bit A/D Converter — 16 — tAD

tADS A/D Sampling Time — — — — tAD

tONST A/D on to A/D start — 2.7V~5.5V — — µs

Note:ADCconversiontime(tADC)=n(bitsADC)+4(samplingtime).TheconversionforeachbitneedsoneADCclock(tAD).

Rev. 1.10 16 ne 0 01 Rev. 1.10 17 ne 0 01



Power-on Reset CharacteristicsTa=25°C



IPOR DC Operating Crrent 2.2V~5.5V Ta=25°C — — 0.7 µAVPOR VDD Start Voltage to Ensre Power-on Reset — — — — 100 mVRRVDD VDD raising rate to Ensre Power-on Reset — — 0.035 — — V/ms

tPORMinimm Time for VDD Stays at VPOR to Ensre Power-on Reset — — 1 — — ms

DC/DC Converter and LDO Electrical CharacteristicsTa=25°C



DC/DCVIN DC/DC Inpt Voltage — — .800 — 5.500 VVO1DC/DC DC/DC Otpt Voltage 1 — VIN=2.8V~5.5V, VSEL=0 -5% 3.800 +5% VVODC/DC DC/DC Otpt Voltage — VIN=2.8V~5.5V, VSEL=1 -5% 5.500 +5% V

IVDD VDD Spply Crrent — VIN=4.75V, ISC=60mA, CPU Idle — — 100 mA

5V Regulator OutputVIN DC/DC Inpt Voltage — — .8 — 5.5 VVCRDVCC Smart Card Power Spply Voltage — VO=5.5V, ISC=60mA .6 5.0 5. VISC Smart Card Spply Crrent — VO=5.5V, VCRDVCC=4.6V 60 — — mAIOCDET Crrent Overload Detection — — 70 95 10 mA

IQUI Qiescent Crrent — VO=5.5V, CLOAD=4.7µF, No load crrent — 100 150 µA

tIDET Detection Time on Crrent Overload — VO=5.5V, ISC from 60mA to 10mA 170 — 100 µs

tOFF VCRDVCC Trn Off Time — VO=5.5V, CLOAD=4.7μF,VCRDVCC from VCRDVCC to 0.V — — 750 µs

tON VCRDVCC Trn On Time — VO=5.5V, CLOAD=4.7μF,VCRDVCC from 0V to VCRDVCC (min.)

— — 750 µs

V5PWRGOOD LDO 5V Power Good Voltage — VO=5.5V, CLOAD=4.7μF .7 — — VV5RIPPLE Ripple on Card Voltage — VO=5.5V, CLOAD=4.7μF — — 00 mV

Rev. 1.10 16 ne 0 01 Rev. 1.10 17 ne 0 01





3V Regulator OutputVIN DC/DC Inpt Voltage — — .80 — 5.50 VVCRDVCC Smart Card Power Spply Voltage — VO=3.8V, ISC=55mA .76 3.00 3. VISC Smart Card Spply Crrent — VO=3.8V, VCRDVCC=2.76V 55 — — mAIOCDET Crrent Overload Detection — — 70 95 10 mA

tIDET Detection Time on Crrent Overload — VO=3.8V,ISC from 55mA to 10mA 170 — 100 µs

tOFF VCRDVCC Trn Off Time — VO=3.8V, CLOAD=4.7μF,VCRDVCC from VCRDVCC to 0.V — — 750 µs

tON VCRDVCC Trn On Time — VO=3.8V, CLOAD=4.7μF,VCRDVCC from 0V to VCRDVCC (min.)

— — 750 µs

V3PWRGOOD LDO 3V Power Good Voltage — VO=3.8V, CLOAD=4.7μF .8 — — VV3RIPPLE Ripple on Card Voltage — VO=3.8V, CLOAD=4.7μF — — 00 mV1.8V Regulator Output

VIN DC/DC Inpt Voltage —DC/DC is trned off 3. — 5.5

VDC/DC mst be trned on VO=3.8V .8 — 3.

VCRDVCC Smart Card Power Spply Voltage — ISC=35mA 1.66 1.80 1.9 VISC Smart Card Spply Crrent — VCRDVCC=1.66V 35 — — mAIOVDET Crrent Overload Detection — — 70 95 10 mA

tIDETDetection Time on Crrent Overload(time for flag IOVF 0 → 1) — ISC=35mA → 120mA 170 — 100 µs

tON

VCRDVCC Trn on Time(time for Card Voltage to reach min of VCRDVCC from 0V)

— CLOAD≤4.7µF, Card voltage=0V to VCRDVCC (min.)

— — 750 µs

tOFFVCRDVCC Trn off Time(time for Card Voltage down to 0.4V) — CLOAD≤4.7µF,

Card voltage=VCRDVCC to 0.V — — 750 µs

V18PWRGOOD LDO 1.8V Power Good Voltage — CLOAD=4.7µF 1.7 1.73 — VV18RIPPLE Ripple on card Voltage(VCRDVCC) — CLOAD=4.7µF — — 100 mV

Rev. 1.10 18 ne 0 01 Rev. 1.10 19 ne 0 01



System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.TherangeofdevicestakeadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.Thepipeliningscheme is implemented insuchaway that instruction fetchingand instructionexecutionareoverlapped,hence instructionsareeffectivelyexecuted inonecycle,with theexceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitectural featuresensure thataminimumofexternalcomponents is required toprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakes thedevicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and PipeliningThemainsystemclock,derivedfromeitheraCrystal/ResonatororRCoscillatorissubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles, thepipeliningstructureof themicrocontrollersensures that instructionsareeffectivelyexecuted inone instructioncycle.Theexception to thisare instructionswhere thecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.

WhentheexternalRCoscillatorisused,OSC2isfreeforuseasanomralI/Opin.

System Clocking and Pipelining

Rev. 1.10 18 ne 0 01 Rev. 1.10 19 ne 0 01



For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

Instruction Fetching

Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionisexecutedexcept for instructions, suchas″JMP″or″CALL″ thatdemanda jump toanon-consecutiveProgramMemoryaddress.Itmustbenotedthatonlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressable.

Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall,interruptorreset,etc.,themicrocontrollersmanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

ModeProgram Counter Bits

b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0Initial Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0Smart Card Interrpt 0 0 0 0 0 0 0 0 0 0 0 1 0 0UART Interrpt 0 0 0 0 0 0 0 0 0 0 1 0 0 0External Interrpt 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0External Interrpt 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0Timer/Event Counter 0 Overflow 0 0 0 0 0 0 0 0 0 1 0 1 0 0Timer/Event Counter 1 Overflow 0 0 0 0 0 0 0 0 0 1 1 0 0 0Smart Card Insertion/Removal Interrpt 0 0 0 0 0 0 0 0 0 1 1 1 0 0

A/D Converter Interrpt 0 0 0 0 0 0 0 0 1 0 0 0 0 0Mlti-Fnction 0 Interrpt 0 0 0 0 0 0 0 0 1 0 0 1 0 0Mlti-Fnction 1 Interrpt 0 0 0 0 0 0 0 0 1 0 1 0 0 0Skip Program Counter+2 (within current bank)Loading PCL PC13 PC1 PC11 PC10 PC9 PC8 @7 @6 @5 @ @3 @ @1 @0mp Call Branch BP.5 #1 #11 #10 #9 #8 #7 #6 #5 # #3 # #1 #0Retrn from Sbrotine S13 S1 S11 S10 S9 S8 S7 S6 S5 S S3 S S1 S0

Program Counter

Note:PC13~PC8:CurrentProgramCounterbits @7~@0:PCLbits BP.5:Bankpointerbit#12~#0:Instructioncodeaddressbits S13~S0:Stackregisterbits

Rev. 1.10 0 ne 0 01 Rev. 1.10 1 ne 0 01



Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwritableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly,however,asonlythis lowbyteisavailableformanipulation, the jumpsare limited to thepresentpageofmemory, that is256locations.Whensuchprogramjumpsareexecuteditshouldalsobenotedthatadummycyclewillbeinserted.

ThelowerbyteoftheProgramCounterisfullyaccessibleunderprogramcontrol.ManipulatingthePCLmightcauseprogrambranching,soanextracycleisneededtopre-fetch.FurtherinformationonthePCLregistercanbefoundintheSpecialFunctionRegistersection.

StackThisisaspecialpartofthememorywhichisusedtosavethecontentsoftheProgramCounteronly.Andisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.TheactivatedlevelisindexedbytheStackPointer,SP,andisneitherreadablenorwriteable.Atasubroutinecallor interruptacknowledgesignal, thecontentsof theProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointerisdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresultinastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.

Rev. 1.10 0 ne 0 01 Rev. 1.10 1 ne 0 01



Arithmetic and Logic Unit − ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollersthatcarriesoutarithmeticandlogicoperationsof theinstructionset.Connectedto themainmicrocontrollersdatabus, theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticorlogicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresult incarry,borroworotherstatuschanges, thestatus registerwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA

• RotationRRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC

• IncrementandDecrementINCA,INC,DECA,DEC

• Branchdecision,JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI

Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthedevicetheProgramMemoryisanOTPtype,whichmeansitcanbeprogrammedonlyonetime.Byusingtheappropriateprogrammingtools,thisOTPmemorydeviceofferuserstheflexibilitytoconvenientlydebuganddeveloptheirapplicationswhilealsoofferingameansoffieldprogramming.

StructureTheProgramMemoryhasacapacityof16K×16bits.TheProgramMemoryisaddressedbytheProgramCounterandalsocontainsdata,tableinformationandinterrupt-entries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyaseparatetablepointerregister.

0000H

000H

008H

Reset

Interrpt Vector

16 bits1FFFH

Bank 1

000H

3FFFH

Program Memory Structure

Rev. 1.10 ne 0 01 Rev. 1.10 3 ne 0 01



Special VectorsWithin theProgramMemory,certain locationsarereservedforspecialusagesuchas resetandinterrupts.

Location 000HThisvectorisreservedforusebythedeviceresetforprograminitialisation.Afteradeviceresetisinitiated,theprogramwilljumptothislocationandbeginexecution.

Location 004HThisvectorisusedbytheSmartCardinterrupt.IfarelatedSmartCardinterrupteventoccurs,theprogramwilljumptothislocationandbeginexecutioniftheexternalinterruptisenabledandthestackisnotfull.

Location 008HThisvectorisusedbytheUARTinterrupt.IftherelatedUARTinterrupteventoccurs,theprogramwilljumptothislocationandbeginexecutioniftheexternalinterruptisenabledandthestackisnotfull.

Location 00CHThisvectorisusedbytheexternalinterrupt0.Iftherelatedexternalinterruptpinreceivesanactiveedge,theprogramwilljumptothislocationandbeginexecutioniftheexternalinterruptisenabledandthestackisnotfull.

Location 010HThisvectorisusedbytheexternalinterrupt1.Iftherelatedexternalinterruptpinreceivesanactiveedge,theprogramwilljumptothislocationandbeginexecutioniftheexternalinterruptisenabledandthestackisnotfull.

Location 014HThis internalvector isusedbytheTimer/EventCounter0.IfaTimer/EventCounter0overflowoccurs, theprogramwill jump to this locationandbeginexecution if the timer/eventcounterinterruptisenabledandthestackisnotfull.

Location 018HThis internalvector isusedbytheTimer/EventCounter1.IfaTimer/EventCounter1overflowoccurs, theprogramwill jump to this locationandbeginexecution if the timer/eventcounterinterruptisenabledandthestackisnotfull.

Location 01CHThisvector isusedbytheSmartCardInsertion/Removal interrupt. IfaSmartCardInsertionorRemovaleventoccurs, theprogramwill jumptothislocationandbeginexecutionif theexternalinterruptisenabledandthestackisnotfull.

Location 020HThisvector isreservedfor theA/DConverter interrupt. If thecompletionofanA/Dconversionoccurs,theprogramwilljumptothislocationandbeginexecutioniftheexternalinterruptisenabledandthestackisnotfull.

Rev. 1.10 ne 0 01 Rev. 1.10 3 ne 0 01



Location 024HThisinternalvectorisusedbytheMulti-function0Interrupt.TheMulti-function0InterruptvectorissharedbyseveralinternalfunctionssuchasaSerialInterfaceModule0interrupt,anactiveedgeappearingontheExternalPeripheral interruptpin,aTimeBaseoverfloworaRealTimeClockoverflow.Theprogramwill jumpto this locationandbeginexecutionif therelevant interrupt isenabledandthestackisnotfull.

Location 028HThisinternalvectorisusedbytheMulti-function1Interrupt.TheMulti-function1InterruptvectorissharedbyseveralinternalfunctionssuchasaSerialInterfaceModule1interrupt,aTimer/EventCounter2oraTimer/EventCounter3overflow.Theprogramwilljumptothislocationandbeginexecutioniftherelevantinterruptisenabledandthestackisnotfull.

Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointerpairmustfirstbesetupbyplacingtheaddressofthelookupdatatoberetrievedinthetablepointerregisterpair,TBLPandTBHP.Thisregisterpairdefinestheaddressofthelook-uptable.

Aftersettingupthe tablepointerpair, the tabledatacanberetrievedfromthespecificProgramMemory page or last ProgramMemory page using the ″TABRD [m]″ or ″TABRDL [m]″instructions,respectively.Whentheseinstructionsareexecuted,thelowerordertablebytefromtheProgramMemorywillbetransferredtotheuserdefinedDataMemoryregister[m]asspecifiedintheinstruction.ThehigherordertabledatabytefromtheProgramMemorywillbetransferredtotheTBLHspecialregister.

Thefollowingdiagramillustratestheaddressing/dataflowofthelook-uptable:

Rev. 1.10 ne 0 01 Rev. 1.10 5 ne 0 01



Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromtheHT56RU25.Thisexampleusesrawtabledatalocatedinthelastpage.Thevalueat″1F00H″whichreferstothestartaddressofthelastpagewithinthe16KProgramMemoryoftheHT56RU25device.Thetablepointerissetupheretohaveaninitialvalueof″06H″.ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress″1F06H″or6locationsafter thestartofthelastpage.Notethat thevalueforthetablepointer isreferencedtotheTBLPandTBHPregistersifthe″TABRD[m]″instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe″TABRDL[m]″instructionisexecuted.

Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

Table Read Program Example:Rombank 1 code1ds .section 'data'Tempreg1 db ? ; temporaryregister#1tempreg2 db ? ; temporaryregister#2::code0 .section 'code'mov a,06h ; initialise table pointer - note that this address is referencedmov tblp,a ; to the last page or the page that tbhp pointedmov a,03fh ; initialise high table pointermov tbhp,a ; it is not necessary to set tbhp if executing tabrdl::tabrd tempreg1tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempregl ; data at prog.memory address 1F06H transferred to tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrd tempreg2tabrdl tempreg2 ; transfers value in table referenced by table pointer to tempreg2 ; data at prog.memory address 1F05H transferred to tempreg2 and TBLH ; in this example the data 1AH is transferred to tempreg1 and data 0FH ; to tempreg2 ; the value 00H will be transferred to the high byte register TBLH : :code1 .section 'code'org 1F00h ; sets initial address of lastpagedc 00Ah,00Bh,00Ch,00Dh,00Eh,00Fh,01Ah,01Bh

Rev. 1.10 ne 0 01 Rev. 1.10 5 ne 0 01



Data MemoryTheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretemporaryinformationisstored.Dividedintotwoparts,thefirstoftheseisanareaofRAMwherespecialfunctionregistersare located.Theseregistershavefixedlocationsandarenecessaryforcorrectoperationof thedevice.Manyof theseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.ThegeneralpurposedatamemoryisdividedintoseveralbanksandswitchingbetweenthedifferentDataMemorybanksisachievedbysettingtheBankPointertothecorrectvalue.

StructureTheDataMemoryissubdividedintoseveralbanks,allofwhichare implemented in8-bitwideRAM.TheDataMemorylocatedinBank0issubdividedintotwosections, theSpecialPurposeDataMemoryandtheGeneralPurposeDataMemory.

TheaddressoftheSpecialDataMemoryforthedeviceisfromaddress“00H”to“7FH”.RegistersinSpecialDataMemoryarecommontothemicrocontroller,suchasACC,PCL,etc.Banks3to11containonlyGeneralPurposeDataMemoryforthedevicewithlargerDataMemorycapacities.AstheSpecialPurposeDataMemoryregistersaremappedintoallbankareas,theycansubsequentlybeaccessedfromanybanklocation.

Data Memory Capacity BanksSpecial Prpose 128×8 Common to Bank 0~11: 00H~7FH

General Prpose 1280×8

0: 80H~FFH1~2: Unimplemented3: 80H~FFH : :11: 80H~FFH

Data Memory Structure

Rev. 1.10 6 ne 0 01 Rev. 1.10 7 ne 0 01



General Purpose Data MemoryAllmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserprogramingforbothreadingandwritingoperations.Byusingthebitoperationinstructions individualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipulationintheDataMemory.ForthedevicewithlargerDataMemorycapacities,theGeneralPurposeDataMemory,inadditiontobeinglocatedinBank0,isalsostoredinBanks3toBank11.

Special Purpose Data MemoryThis area ofDataMemory iswhere registers, necessary for the correct operation of themicrocontroller,arestored.Mostoftheregistersarebothreadandwritetypebutsomeareprotectedandarereadonly, thedetailsofwhichare locatedunder therelevantSpecialFunctionRegistersection.Notethatforlocationsthatareunused,anyreadinstructiontotheseaddresseswillreturntheunknowvalue.TheSpecialFunctionregistersaremappedintoallbanksandcanthereforebeaccessedfromanybanklocation.

00H IAR001H MP00H IAR103H MP10H05H ACC06H PCL07H TBLP08H TBLH09H

TBHP0AH STATUS0BH0CH0DH0EH0FH10H INTC011H INTC11H

19H18H

1BH1AH

1DH1CH

1FH1EH

RTCC

13H1H MFIC015H MFIC116H17H

TMR0

Unsed

PCPUPC

PCC

USR

TXR_RXR

0H1HH

9H8H

BHAH

DHCH

FHEH

3HH5H6H7H

30H31H3H

39H38H

3BH3AH

3DH3CH

3FH3EH

33H3H35H36H37H

0H1HH3H

7H8H9HAHBHCHDHEHFH50H51H5H

58H

53H5H55H56H57H

60H

BP

MISC0MISC1

CLKMOD

Unsed

Unsed

Unsed

Unsed

INTC

PWM0L

TMR1C

H5H6H

59H5AH5BH5CH5DH5EH5FH

7FH

DCDC

PAPUPAWU

PAPAC

PBPUPB

PBC

Unsed

UnsedUnsed

UCR1UCRBRG

PWM0HPWM1LPWM1HPWMLPWMHPWM3LPWM3H

TMR0CTMR1HTMR1L

TMRTMRCTMR3

TMR3C

UnsedUnsedRCFLTADRLADRHADCRACSR

ADPCRSIM0CTL0SIM0CTL1SIM0DR

SIM0AR/SIM0CTLSIM1CTL0SIM1CTL1SIM1DR

SIM1AR/SIM1CTLDALDAH

DACTRLCCRCSR

CCCRCETU1CETU0CGT1CGT0CWTCWT1CWT0CIERCIPRCTXBCRXB

UnsedUnsed

:::

Unsed

: Unsed read as “xx”

Special Purpose Data Memory

Rev. 1.10 6 ne 0 01 Rev. 1.10 7 ne 0 01



Special Function Registers DescriptionToensuresuccessfuloperationofthemicrocontroller,certaininternalregistersareimplementedintheDataMemoryarea.Theseregistersensurecorrectoperationofinternalfunctionssuchastimers,interrupts,etc.,aswellasexternalfunctionssuchasI/OdatacontrolandA/Dconverteroperation.ThelocationoftheseregisterswithintheDataMemorybeginsattheaddress″00H″.AnyunusedDataMemorylocationsbetweenthesespecialfunctionregistersandthepointwheretheGeneralPurposeMemorybegins isreservedforfutureexpansionpurposes,attemptingtoreaddatafromtheselocationswillreturnaunknowvalue.

Indirect Addressing Registers − IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.ThemethodofindirectaddressingforRAMdatamanipulationuses theseIndirectAddressingRegistersandMemoryPointers, incontrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair,IAR0andMP0cantogetheraccessdatafromBank0whiletheIAR1andMP1registerpaircanaccessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof″00H″andwritingtotheregistersindirectlywillresultinnooperation.

Memory Pointers − MP0, MP1TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedto,istheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedtoaccessdatafromallbanks.

ThefollowingexampleshowshowtoclearasectionoffourRAMlocationsalreadydefinedaslocationsadres1toadres4.data .section ′data′adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ?code .section at 0 ′code′org 00hstart: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM addressloop: clr IAR0 ; clear the data at address defined by MP0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificRAMaddresses.

Rev. 1.10 8 ne 0 01 Rev. 1.10 9 ne 0 01



Bank Pointer − BPTheDataMemoryisdividedintoatotalof10banks.SelectingtherequiredDataMemoryareaisachievedusingtheBankPointer.IfdatainBank0istobeaccessed,thentheBPregistermustbeloadedwiththevalue00H,whileifdatainBank3istobeaccessed,thentheBPregistermustbeloadedwiththevalue03H,andsoon.

TheDataMemoryis initialisedtoBank0afterareset,exceptfortheWDTtime-outreset inthePowerDownMode,inwhichcase,theDataMemorybankremainsunaffected.ItshouldbenotedthattheSpecialFunctionDataMemoryisnotaffectedbythebankselection,whichmeansthattheSpecialFunctionRegisterscanbeaccessedfromwithinanybank.Directlyaddressing theDataMemorywillalwaysresultinBank0beingaccessedirrespectiveofthevalueoftheBankPointer.AccessingdatafrombanksotherthanBank0mustbeimplementedusingIndirectaddressing.

Bit 7 6 5 4 3 2 1 0Name — — BP5 — BP3 BP BP1 BP0R/W — — R/W — R/W R/W R/W R/WPOR — — 0 — 0 0 0 0

Bit7~6 Unimplemented,readas″0″Bit5 BP5:Programmemorybankpoint

0:ProgramMemoryBank01:ProgramMemoryBank1

TheProgramMemoryhasthecapacityof16Kwordsimplementedas8Kwords×2Banks.Bit4 Unimplemented,readas″0″Bit3~0 BP3~BP0:Datamemorybankpoint

0000:GeneralPurposeDataMemoryBank00001~0010:Notexist0011:GeneralPurposeDataMemoryBank30100:GeneralPurposeDataMemoryBank40101:GeneralPurposeDataMemoryBank50110:GeneralPurposeDataMemoryBank60111:GeneralPurposeDataMemoryBank71000:GeneralPurposeDataMemoryBank81001:GeneralPurposeDataMemoryBank91010:GeneralPurposeDataMemoryBank101011:GeneralPurposeDataMemoryBank11

Rev. 1.10 8 ne 0 01 Rev. 1.10 9 ne 0 01



Accumulator − ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuserdefinedregisterandanother, it isnecessary todo thisbypassingthedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register − PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

Look-up Table Registers − TBLP, TBHP, TBLHThesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHPregistersarethelowerorderbyteandhighorderbytetablepointersandindicatesthelocationwherethetabledataislocated.Theirvaluemustbesetupbeforeanytablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe″INC″or″DEC″instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.

Rev. 1.10 30 ne 0 01 Rev. 1.10 31 ne 0 01



Status Register − STATUSThis8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationof themicrocontroller.WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostother registers.Anydatawritten into the status registerwillnotchange theTOorPDFflag. Inaddition,operations related to the status registermaygivedifferent resultsdueto thedifferent instructionoperations.TheTOflagcanbeaffectedonlybya systempower-up,aWDTtime-outorbyexecuting the″CLRWDT″or″HALT″instruction.ThePDFflag isaffectedonlybyexecutingthe″HALT″or″CLRWDT″instructionorduringasystempower-up.The Z, OV,AC and C f lags general ly ref lect the s ta tus of the la tes t operat ions.Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

Bit 7 6 5 4 3 2 1 0Name — — TO PDF OV Z AC CR/W — — R R R/W R/W R/W R/WPOR — — 0 0 x x x x

″x″ unknownBit7,6 Unimplemented,readas″0″Bit5 TO:WatchdogTime-Outflag

0:Afterpoweruporexecutingthe″CLRWDT″or″HALT″instruction1:Awatchdogtime-outoccurred.

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe″CLRWDT″instruction1:Byexecutingthe″HALT″instruction

Bit3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:Carryflag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation.

Cisalsoaffectedbyarotatethroughcarryinstruction.

Rev. 1.10 30 ne 0 01 Rev. 1.10 31 ne 0 01



Interrupt Control RegistersThese8-bitregisters,knownasINTC0,INTC1,INTC2,MFIC0,MFIC1andMISC0,controltheoveralloperationsof thedeviceinterruptfunctions.Bysettingvariousbitswithintheseregistersusingstandardbitmanipulationinstructions, theenable/disablefunctionofeachinterruptcanbeindependentlycontrolled.AmasterinterruptbitwithintheINTC0register,theEMIbit,actslikeaglobalenable/disablecontrolandisusedtosetalloftheinterruptenablebitsonoroff.Thisbitisclearedwhenaninterruptsubroutineisenteredtodisablefurtherinterruptandissetbyexecutingthe″RETI″instruction.TheMISC0registerisusedtoselecttheactiveedgesforthetwoexternalinterruptpinsINT0andINT1.

Timer/Event Counter RegistersThedevicecontainsseveral internal8-bitand16-bitTimer/EventCounters.TheregistersTMR0,TMR2,TMR3andtheregisterpairTMR1L/TMR1Harethelocationswherethetimervaluesarelocated.Theseregisterscanalsobepreloadedwithfixeddatatoallowdifferenttimeintervalstobesetup.Theassociatedcontrolregisters,TMR0C,TMR1C,TMR2CandTMR3Ccontainthesetupinformationfor these timers,whichdetermines inwhatmodethe timer is tobeusedaswellascontainingthetimeron/offcontrolfunction.

Input/Output Ports and Control RegistersWithintheareaofSpecialFunctionRegisters, theI/Odataregistersandtheirassociatedcontrolregistersplayaprominentrole.AllI/OportshaveadesignatedregistercorrespondinglylabeledasPA,PBandPC.TheselabeledI/OregistersaremappedtospecificaddresseswithintheDataMemoryasshownintheDataMemorytable,whichareusedtotransfertheappropriateoutputorinputdataonthatport.WitheachI/OportthereisanassociatedcontrolregisterlabeledPAC,PBCandPCCalsomappedtospecificaddresseswithintheDataMemory.Thecontrolregisterspecifieswhichpinsofthatportaresetasinputsandwhicharesetasoutputs.Tosetupapinasaninput,thecorrespondingbitofthecontrolregistermustbesethighwhileforanoutputitmustbesetlow.Duringprograminitialization, it is important tofirstsetupthecontrolregisters tospecifywhichpinsareoutputsandwhichareinputsbeforereadingdatafromorwritingdatatotheI/Oports.Oneflexiblefeatureoftheseregistersistheabilitytodirectlyprogramsinglebitsusingthe″SET[m].i″and″CLR[m].i″instructions.TheabilitytochangeI/OpinsfromoutputtoinputandviceversabymanipulatingspecificbitsoftheI/Ocontrolregistersduringnormalprogramoperationisausefulfeatureofthesedevices.

Pulse Width Modulator RegistersThedevice containsmultiplePulseWidthModulator outputs eachwith their own relatedindependentcontrol registerpair,knownasPWM0L/PWM0H,PWM1L/PWM1H,PWM2L/PWM2HandPWM3L/PWM3H.The12-bitcontentsofeachregisterpair,whichdefinesthedutycyclevaluefor themodulationcycleof thePulseWidthModulator,alongwithanenablebitarecontainedintheseregisterpairs.

Rev. 1.10 3 ne 0 01 Rev. 1.10 33 ne 0 01



A/D Converter Registers − ADRL, ADRH, ADCR, ACSRThedevicecontainsamultiplechannel12-bitA/Dconverter.Thecorrectoperationof theA/Drequirestheuseof twodataregistersandtwocontrolregisters.Thetwodataregisters,ahighbytedataregisterknownasADRH,andalowbytedataregisterknownasADRL,aretheregisterlocationswherethedigitalvalueisplacedafterthecompletionofananalogtodigitalconversioncycle.FunctionssuchastheA/Denable/disable,A/DchannelselectionandA/Dclockfrequencyaredeterminedusingthetwocontrolregisters,ADCRandACSR.

Serial Interface Module RegistersThedevicecontainstwoSerialInterfaceModulesnamedSIM0andSIM1andeachSIMcontainsanSPIandanI2Cinterface.TheSIMxCTL0,SIMxCTL1,SIMxCTL2andSIMxARarethecontrolregisters for theSerial Interface functionwhile theSIMxDRis thedata register for theSerialInterfaceDatawherexmeans0and1.

Port A Wake-up Register − PAWUAllpinsonPortAhaveawake-upfunctionenablea lowgoingedgeon thesepins towake-upthedevicewhenitisinapowerdownmode.ThepinsonPortAthatareusedtohaveawake-upfunctionareselectedusingthisresister.

Pull-High Registers − PAPU, PBPU, PCPUAll I/OpinsonPortsPA,PBandPC if setupas inputs,canbeconnected toan internalpull-highresistor.Thepinswhichrequireapull-highresistortobeconnectedareselectedusingtheseregisters.

Clock Control Register − CLKMODThedeviceoperatesusingadualclocksystemwhosemodeiscontrolledusingthisregister.Theregistercontrolsfunctionssuchastheclocksource,theidlemodeenableandthedivisionratiofortheslowclock.

Miscellaneous Register − MISC0, MISC1TheseregistersnameMISC0andMISC1areusedtocontrol themiscellaneousfunctionssuchastheactiveedgeselectionoftheexternalinterruptpins,theclockdividedratioselectionoftheSmartCardandtheWatchdogTimerenablecontrolbits.TherearealsofourbitsusedtodetermineiftheoutputtypeisopendrainorCMOSoutputforPA0~PA3.

Rev. 1.10 3 ne 0 01 Rev. 1.10 33 ne 0 01



Input/Output PortsHoltekmicrocontrollerofferconsiderableflexibilityontheirI/Oports.With the inputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thedeviceprovidesupto24bidirectionalinput/outputlineslabeledwithportnamesPA,PBandPC.TheseI/Oportsaremappedto theRAMDataMemorywithspecificaddressesasshownintheSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedfor inputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyat theT2risingedgeof instruction″MOVA,[m]″,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternal resistor.Toeliminate theneedfor theseexternal resistors,all I/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregistersPAPU,PBPUandPCPUareimplementedusingweakPMOStransistors.

PAWU, PAPU, PA, PAC, PBPU, PB, PBC, PCPU, PC and PCC Registers

Register Name POR

Bit

7 6 5 4 3 2 1 0PAWU 00H PAWU7 PAWU6 PAWU5 PAWU PAWU3 PAWU PAWU1 PAWU0PAPU 00H PAPU7 PAPU6 PAPU5 PAPU PAPU3 PAPU PAPU1 PAPU0

PA FFH PA7 PA6 PA5 PA PA3 PA PA1 PA0PAC FFH PAC7 PAC6 PAC5 PAC PAC3 PAC PAC1 PAC0

PBPU 00H PBPU7 PBPU6 PBPU5 PBPU PBPU3 PBPU PBPU1 PBPU0PB FFH PB7 PB6 PB5 PB PB3 PB PB1 PB0

PBC FFH PBC7 PBC6 PBC5 PBC PBC3 PBC PBC1 PBC0PCPU 00H PCPU7 PCPU6 PCPU5 PCPU PCPU3 PCPU PCPU1 PCPU0

PC FFH PC7 PC6 PC5 PC PC3 PC PC1 PC0PCC FFH PCC7 PCC6 PCC5 PCC PCC3 PCC PCC1 PCC0

PAWUn:PAwake-upfunctionenable0:Disable1:Enable

PAPUn/PBPUn/PCPUn:Pull-highfunctionenable0:Disable1:Enable

PAn/PBn/PCn:I/OportdatabitPACn/PBCn/PCCn:I/Oporttypeselectionbit

0:Output1:Input

Rev. 1.10 3 ne 0 01 Rev. 1.10 35 ne 0 01



Port A Wake-upTheHALTinstructionforces themicrocontroller intoaPowerDownconditionwhichpreservespower,afeaturethatisimportantforbatteryandotuherlow-powerapplications.Variousmethodsexist towake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.AfteraHALTinstructionforcesthemicrocontrollerintoenteringaPowerDowncondition,theprocessorwillremaininalow-powerstateuntilthelogicconditionoftheselectedwake-uppinonPortAchangesfromhightolow.Thisfunctionisespeciallysuitableforapplications thatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.

Port A Open Drain FunctionAllI/OpinsinthedevicehaveCMOSstructures,howeverPortApinsPA0~PA3canalsobesetupasopendrainstructures.ThisisimplementedusingtheODE0~ODE3bitsintheMISC1register.

MISC1 Register

Bit 7 6 5 4 3 2 1 0Name ODE3 ODE ODE1 ODE0 WDTEN3 WDTEN WDTEN1 WDTEN0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 1 0 1 0

Bit7 ODE3:PA3OpenDraincontrol0:Disable1:Enable




Bit3~0 WDTEN3, WDTEN2, WDTEN1, WDTEN0:WDTfunctionenableDescribedinWatchdogTimersection.

I/O Port Control RegistersEachI/Oporthas itsowncontrolregisterknownasPAC,PBC,etc., tocontrol the input/outputconfiguration.With thiscontrol register,eachCMOSoutputor inputwithorwithoutpull-highresistorstructurescanbereconfigureddynamicallyundersoftwarecontrol.Eachpinof theI/Oportsisdirectlymappedtoabitinitsassociatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthecontrolregistermustbewrittenasa″1″.Thiswillthenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa″0″,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwill infactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

Rev. 1.10 3 ne 0 01 Rev. 1.10 35 ne 0 01



Pin-shared FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeovercome.Forsomepins,thechosenfunctionofthemulti-functionI/Opinsissetbyconfigurationoptionswhileforothersthefunctionissetbyapplicationprogramcontrol.

External Interrupt InputsTheexternal interruptpinsINT0andINT1arepin-sharedwith theI/OpinsPA0andPA1.Forapplicationsnotrequiringanexternal interruptinput, thepin-sharedexternal interruptpincanbeusedasanormalI/Opin,howevertodothis,theexternalinterruptenablebitsintheINTC0registermustbedisabled.

External Timer Clock InputTheexternaltimerpinsTMR0,TMR1,TMR2andTMR3arepin-sharedwithI/Opins.Toconfigurethemtooperateas timer inputs, thecorrespondingcontrolbits in thetimercontrolregistermustbecorrectlysetandthepinmustalsobesetupasaninput.NotethattheoriginalI/Ofunctionwillremainevenifthepinissetuptobeusedasanexternaltimerinput.

PFD OutputThedevicecontainsaPFDfunctionwhosesingleoutputispin-sharedwithanI/Opin.Theoutputfunctionof thispin ischosenviaaconfigurationoptionandremains fixedafter thedevice isprogrammed.Note that thecorrespondingbitof theportcontrol registermustsetup thepinasanoutputtoenablethePFDoutput.If theportcontrolregisterhassetupthepinasaninput, thenthepinwillfunctionasanormal logic inputwiththeusualpull-highselection,evenif thePFDconfigurationoptionhasbeenselected.NotethatthePFDoutputfnctionisonlyavailableforthe44-LQFPpackagetype.

PWM OutputsThedevicecontainsseveralPWMoutputsnamePWM0~PWM3sharedwithI/Opins.ThePWMoutputfunctionsarechosenviaregisters.NotethatthecorrespondingbitoftheportcontrolregisterbitmustsetupthepinasanoutputtoenablethePWMoutput.If theportcontrolregisterbithassetupthepinasaninput,thenthepinwillfunctionasanormallogicinputwiththeusualpull-highselection,evenif thePWMregistershaveenabledthePWMfunction.NotethatthePWMoutputfnctionisonlyavailableforthe44-LQFPpackagetype.

A/D InputsThedevicecontainsmulti-channelA/Dconverterinputs.Alloftheseanaloginputsarepin-sharedwithI/OpinsonPortAandPortCrespectively.IfthesepinsaretobeusedasA/DinputsandnotasnormalI/OpinsthenthecorrespondingbitsintheA/DConverterControlRegister,ADCR,mustbeproperlyset.TherearenoconfigurationoptionsassociatedwiththeA/Dfunction.IfusedasI/Opins,thenfullpull-highresistorregisterremain,howeverifusedasA/Dinputsthenanypull-highresistorselectionsassociatedwiththesepinswillbeautomaticallydisconnected.NotethattheA/Dinputfnctionisonlyavailableforthe44-LQFPpackagetype.

Rev. 1.10 36 ne 0 01 Rev. 1.10 37 ne 0 01



I/O Pin StructuresTheaccompanyingdiagramsillustrate theinternalstructuresofsomeI/Opintypes.AstheexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

Generic Input/Output Structure

A/D Input/Output Structure

Rev. 1.10 36 ne 0 01 Rev. 1.10 37 ne 0 01



Programming ConsiderationsWithintheuserprogram,oneofthefirstthingstoconsiderisportinitialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoaninputstate, thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.If theportcontrolregisters,PAC,PBC,etc.,are thenprogrammedtosetupsomepinsasoutputs, theseoutputpinswillhaveaninitialhighoutputvalueunless theassociatedportdataregisters,PA,PB,etc.,arefirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvaluesintotheappropriateportcontrol registerorbyprogramming individualbits in theportcontrol registerusing the″SET[m].i″and″CLR[m].i″ instructions.Note thatwhenusingthesebitcontrol instructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

Read/Write Timing

PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in thePowerDownMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.

Rev. 1.10 38 ne 0 01 Rev. 1.10 39 ne 0 01



Timer/Event CountersTheprovisionof timers forman importantpartofanymicrocontroller,giving thedesignerameansofcarryingouttimerelatedfunctions.Thedevicecontainsseveral8-bitand16-bitcount-uptimers.Aseachtimerhasthreedifferentoperatingmodes, theycanbeconfiguredtooperateasageneraltimer,anexternaleventcounterorasapulsewidthmeasurementdevice.Theprovisionofaprescalertotheclockcircuitryofthe8-bitTimer/EventCounteralsogivesaddedrangetothistimer.

TherearetwotypesofregistersrelatedtotheTimer/EventCounters.ThefirstaretheregistersthatcontaintheactualvalueoftheTimer/EventCounterandintowhichaninitialvaluecanbepreloaded.ReadingfromtheseregistersretrievesthecontentsoftheTimer/EventCounter.ThesecondtypeofassociatedregisteristheTimerControlRegisterwhichdefinesthetimeroptionsanddetermineshowtheTimer/EventCounteristobeused.TheTimer/EventCounterscanhavetheirclockconfiguredtocomefromaninternalclocksource.Inaddition,theirclocksourcecanalsobeconfiguredtocomefromanexternaltimerpin.

Configuring the Timer/Event Counter Input Clock SourceTheinternal timer′sclockcanoriginatefromvarioussources.Thesystemclocksource isusedwhentheTimer/EventCounterisinthetimermodeorinthepulsewidthmeasurementmode.Forthe8-bitTimer/EventCounterthisinternalclocksourceisfSYSwhichisalsodividedbyaprescaler,thedivisionratioofwhichisconditionedbytheTimerControlRegister,TMRnC,bitsTnPSC0~TnPSC2.For the16-bitTimer/EventCounter this internalclocksourcecanbechosen fromacombinationofinternalclocksusingaconfigurationoptionandtheTnSbitintheTMRnCregister.

Anexternalclocksourceisusedwhenthetimeris intheeventcountingmode, theclocksourcebeingprovidedonanexternal timerpinTMR0,TMR1,TMR2orTMR3dependinguponwhichtimer isused.Dependingupon theconditionof theTnEbit,eachhigh to low,or low tohightransitionontheexternaltimerpinwillincrementthecounterbyone.

Name Bits Data Register Control RegisterTimer/Event Conter 0 8 TMR0 TMR0CTimer/Event Conter 1 16 TMR1H/TMR1L TMR1CTimer/Event Conter 8 TMR TMRCTimer/Event Conter 3 8 TMR3 TMR3C

8-bit Timer/Event Counter Structure

Rev. 1.10 38 ne 0 01 Rev. 1.10 39 ne 0 01



16-bit Timer/Event Counter Structure

Timer/Event Counter Control Register − TMRnC (n=0, 2, 3)

Bit 7 6 5 4 3 2 1 0Name TnM1 TnM0 — TnON TnE TnPSC TnPSC1 TnPSC0R/W R/W R/W — R/W R/W R/W R/W R/WPOR 0 0 — 0 1 0 0 0

Bit7~6 TnM1~TnM0:Timer/EventCounterOperatingmodeselectionbit00:Nomodeavailable01:EventCountermode10:Timermode11:Pulsewidthmeasurementmode

Bit5 Unimplemented,readas″0″Bit4 TnON:Timer/EventCountercountingenablecontrol

0:Disable1:Enable

Bit3 TnE:Timer/EventCounteractiveedgeselectionbitsForEventcountermode:0:Countonrisingedge1:Countonfallingedge

ForPulsewidthmeasurementmode:0:Startcountingonfallingedge1:Startcountingonrisingedge

Bit2~0 TnPSC2~TnPSC0:Timer/EventCounterprescalerrateselectionbits000:1/1001:1/2010:1/4011:1/8100:1/16101:1/32110:1/64111:1/128

Rev. 1.10 0 ne 0 01 Rev. 1.10 1 ne 0 01



Timer/Event Counter Control Register − TMRnC (n=1)

Bit 7 6 5 4 3 2 1 0Name TnM1 TnM0 TnS TnON TnE — — —R/W R/W R/W R/W R/W R/W — — —POR 0 0 0 0 1 — — —

Bit7~6 TnM1~TnM0:Timer/EventCounterOperatingmodeselectionbit00:Nomodeavailable01:EventCountermode10:Timermode11:Pulsewidthmeasurementmode

Bit5 TnS:Timer/EventCounterclocksourceselectionbit0:fSYS/41:fSUB

Bit4 TnON:Timer/EventCountercountingenablecontrol0:Disable1:Enable

Bit3 TnE:Timer/EventCounteractiveedgeselectionbitsForEventcountermode:0:Countonrisingedge1:Countonfallingedge

ForPulsewidthmeasurementmode:0:Startcountingonfallingedge1:Startcountingonrisingedge

Bit2~0 Unimplemented,readas″0″

Timer Registers − TMR0C, TMR1C, TMR2C, TMR3CTochoosewhichofthethreemodesthetimeristooperatein,eitherinthetimermode,theeventcountingmodeor thepulsewidthmeasurementmode,bits7and6of thecorrespondingTimerControlRegister,whichareknownas thebitpairTnM1/TnM0,mustbe set to the requiredlogiclevels.Thetimer-onbit,whichisbit4oftheTimerControlRegisterandknownasTnON,dependinguponwhich timer isused,provides thebasicon/offcontrolof the respective timer.Settingthebithighallowsthecountertorun,clearingthebitstopsthecounter.Fortimersthathaveprescalers,bits0~2of theTimerControlRegisterdeterminethedivisionratioof theinputclockprescaler.Theprescalerbitsettingshavenoeffectifanexternalclocksourceisused.Ifthetimerisintheeventcountorpulsewidthmeasurementmode,theactivetransitionedgeleveltypeisselectedbythelogiclevelofbit3oftheTimerControlRegisterwhichisknownasTnE.AnadditionalTnSbitinthe16-bitTimer/EventCountercontrolregisterisusedtodeterminetheclocksourcefortheTimer/EventCounter.

Rev. 1.10 0 ne 0 01 Rev. 1.10 1 ne 0 01



Configuring the Timer ModeInthismode, theTimer/EventCountercanbeutilisedtomeasurefixedtimeintervals,providinganinternalinterruptsignaleachtimetheTimer/EventCounteroverflows.Tooperateinthismode,theOperatingModeSelectbitpair,TnM1/TnM0,intheTimerControlRegistermustbesettothecorrectvalueasshown.

Bit6 Bit70 1

Control Register Operating Mode Select Bits for the Timer Mode

Timer Mode Timing Chart

Inthismodetheinternalclock,fSYS, isusedastheinternalclockfor8-bitTimer/EventCountersandfSUBorfSYS/4isusedastheinternalclockfor16-bitTimer/EventCounter.However,theclocksource,fSYS,forthe8-bittimerisfurtherdividedbyaprescaler,thevalueofwhichisdeterminedbythePrescalerRateSelectbitsTnPSC2~TnPSC0,whicharebits2~0intheTimerControlRegister.AftertheotherbitsintheTimerControlRegisterhavebeensetup,theenablebitTnON,whichisbit4oftheTimerControlRegister,canbesethightoenabletheTimer/EventCountertorun.Eachtimeaninternalclockcycleoccurs,theTimer/EventCounterincrementsbyone.Whenitisfullandoverflows,aninterruptsignalisgeneratedandtheTimer/EventCounterwillreloadthevaluealreadyloadedintothepreloadregisterandcontinuecounting.TheinterruptcanbedisabledbyensuringthattheTimer/EventCounterInterruptEnablebitinthecorrespondingInterruptControlRegister,isresettozero.

Rev. 1.10 ne 0 01 Rev. 1.10 3 ne 0 01



Configuring the Event Counter ModeInthismode,anumberofexternallychanginglogicevents,occurringontheexternaltimerpin,canberecordedbytheTimer/EventCounter.Tooperateinthismode, theOperatingModeSelectbitpair,TnM1/TnM0,intheTimerControlRegistermustbesettothecorrectvalueasshown.

Bit6 Bit71 0

Control Register Operating Mode Select Bits for the Event Counter Mode

Event Counter Mode Timing Chart

Inthismode,theexternaltimerpin,isusedastheTimer/EventCounterclocksource,howeveritisnotdividedbytheinternalprescaler.AftertheotherbitsintheTimerControlRegisterhavebeensetup,theenablebitTnON,whichisbit4oftheTimerControlRegister,canbesethightoenabletheTimer/EventCountertorun.IftheActiveEdgeSelectbit,TnE,whichisbit3oftheTimerControlRegister, islow,theTimer/EventCounterwillincrementeachtimetheexternaltimerpinreceivesalowtohightransition.IftheActiveEdgeSelectbitishigh,thecounterwillincrementeachtimetheexternaltimerpinreceivesahightolowtransition.Whenitisfullandoverflows,aninterruptsignalisgeneratedandtheTimer/EventCounterwillreloadthevaluealreadyloadedintothepreloadregisterandcontinuecounting.The interruptcanbedisabledbyensuring that theTimer/EventCounterInterruptEnablebitinthecorrespondingInterruptControlRegister,isresettozero.

AstheexternaltimerpinissharedwithanI/Opin,toensurethatthepinisconfiguredtooperateasaneventcounterinputpin,twothingshavetohappen.ThefirstistoensurethattheOperatingModeSelectbits in theTimerControlRegisterplace theTimer/EventCounter in theEventCountingMode,thesecondistoensurethattheportcontrolregisterconfiguresthepinasaninput.Itshouldbenotedthatintheeventcountingmode,evenifthemicrocontrollerisinthePowerDownMode,theTimer/EventCounterwillcontinuetorecordexternallychanginglogiceventsonthetimerinputpin.Asaresultwhenthetimeroverflowsitwillgenerateatimerinterruptandcorrespondingwake-upsource.

Rev. 1.10 ne 0 01 Rev. 1.10 3 ne 0 01



Configuring the Pulse Width Measurement ModeIn thismode, theTimer/EventCountercanbeutilised tomeasure thewidthofexternalpulsesappliedtotheexternaltimerpin.Tooperateinthismode,theOperatingModeSelectbitpair,TnM1/TnM0,intheTimerControlRegistermustbesettothecorrectvalueasshown.

Bit6 Bit71 1

Control Register Operating Mode Select Bits for the Pulse Width Measurement Mode

Pulse Width Measure Mode Timing Chart

Inthismodetheinternalclock,fSYS,isusedastheinternalclockforthe8-bitTimer/EventCounterandfSUBorfSYS/4isusedastheinternalclockforthe16-bitTimer/EventCounter.However,theclocksource,fSYS,forthe8-bittimerisfurtherdividedbyaprescaler,thevalueofwhichisdeterminedbythePrescalerRateSelectbitsTnPSC2~TnPSC0,whicharebits2~0intheTimerControlRegister.AftertheotherbitsintheTimerControlRegisterhavebeensetup,theenablebitTnON,whichisbit4oftheTimerControlRegister,canbesethightoenabletheTimer/EventCounter,howeveritwillnotactuallystartcountinguntilanactiveedgeisreceivedontheexternaltimerpin.IftheActiveEdgeSelectbitTnE,whichisbit3oftheTimerControlRegister,islow,onceahightolowtransitionhasbeenreceivedontheexternal timerpin, theTimer/EventCounterwillstartcountinguntiltheexternaltimerpinreturnstoitsoriginalhighlevel.AtthispointtheenablebitwillbeautomaticallyresettozeroandtheTimer/EventCounterwillstopcounting.IftheActiveEdgeSelectbit ishigh,theTimer/EventCounterwillbegincountingoncealowtohightransitionhasbeenreceivedontheexternaltimerpinandstopcountingwhentheexternaltimerpinreturnstoitsoriginallowlevel.Asbefore,theenablebitwillbeautomaticallyresettozeroandtheTimer/EventCounterwillstopcounting.ItisimportanttonotethatinthePulseWidthMeasurementMode,theenablebit isautomaticallyresettozerowhentheexternalcontrolsignalontheexternaltimerpinreturnstoitsoriginallevel,whereasintheothertwomodestheenablebitcanonlyberesettozerounderprogramcontrol.TheresidualvalueintheTimer/EventCounter,whichcannowbereadbytheprogram,thereforerepresentsthelengthofthepulsereceivedontheexternaltimerpin.Astheenablebithasnowbeenreset,anyfurther transitionsontheexternal timerpinwillbeignored.Notuntil theenablebit isagainsethighbytheprogramcanthetimerbeginfurtherpulsewidthmeasurements.Inthisway,singleshotpulsemeasurementscanbeeasilyMade.Itshouldbenotedthat in thismodetheTimer/EventCounter iscontrolledbylogical transitionson theexternal timerpinandnotby the logic level.WhentheTimer/EventCounter is fullandoverflows,aninterruptsignalisgeneratedandtheTimer/EventCounterwillreloadthevaluealreadyloadedintothepreloadregisterandcontinuecounting.TheinterruptcanbedisabledbyensuringthattheTimer/EventCounterInterruptEnablebitinthecorrespondingInterruptControlRegister,isresettozero.AstheexternaltimerpinissharedwithanI/Opin,toensurethatthepinisconfiguredtooperateasapulsewidthmeasurementpin,twothingshavetohappen.ThefirstistoensurethattheOperatingModeSelectbitsintheTimerControlRegisterplacetheTimer/EventCounterinthePulseWidthMeasurementMode,thesecondistoensurethattheportcontrolregisterconfiguresthepinasaninput.

Rev. 1.10 ne 0 01 Rev. 1.10 5 ne 0 01



Programmable Frequency Divider − PFDTheProgrammableFrequencyDividerprovidesameansofproducingavariablefrequencyoutputsuitableforapplicationsrequiringaprecisefrequencygenerator.

ThePFDoutputispin-sharedwiththeI/OpinPC1.ThePFDfunctionisselectedviaconfigurationoption,however,ifnotselected,thepincanoperateasanormalI/Opin.

Theclocksourcefor thePFDcircuitcanoriginatefromeitherTimer/EventCounter0orTimer/EventCounter1overflowsignal selectedviaconfigurationoption.Theoutput frequency iscontrolledbyloadingtherequiredvaluesintothetimerregistersandprescalerregisterstogivetherequireddivisionratio.Thetimerwillbegintocount-upfromthispreloadregistervalueuntilfull,atwhichpointanoverflowsignalisgenerated,causingthePFDoutputtochangestate.Thetimerwillthenbeautomaticallyreloadedwiththepreloadregistervalueandcontinuecounting-up.

ForthePFDoutputtofunction,itisessentialthatthecorrespondingbitofthePortCcontrolregisterPCCbit1issetupasanoutput.IfsetupasaninputthePFDoutputwillnotfunction,however,thepincanstillbeusedasanormalinputpin.ThePFDoutputwillonlybeactivatedifbitPC1issetto″1″.Thisoutputdatabitisusedastheon/offcontrolbitforthePFDoutput.NotethatthePFDoutputwillbelowifthePC1outputdatabitisclearedto″0″.

Usingthismethodoffrequencygeneration,andifacrystaloscillatorisusedforthesystemclock,veryprecisevaluesoffrequencycanbegenerated.NotethatthePFDfunctionisonlyavailablefor44-LQFPpackagetype.

PFD Output Control

PrescalerBitsTnPSC0~TnPSC2of thecontrolregistercanbeusedtodefinethepre-scalingstagesof theinternalclocksourceoftheTimer/EventCounter.TheTimer/EventCounteroverflowsignalcanbeusedtogeneratesignalsforthePFDandTimerInterrupt.

Rev. 1.10 ne 0 01 Rev. 1.10 5 ne 0 01



I/O InterfacingTheTimer/EventCounter,whenconfiguredtorunintheeventcounterorpulsewidthmeasurementmode,requiretheuseofexternalpinsforcorrectoperation.AsthesepinsaresharedpinstheymustbeconfiguredcorrectlytoensuretheyaresetupforuseasTimer/EventCounterinputsandnotasanormalI/Opins.This is implementedbyensuringthat themodeselectbits intheTimer/EventCounter control register, select either the event counterorpulsewidthmeasurementmode.AdditionallythePortControlRegistermustbesethightoensurethatthepinissetupasaninput.Anypull-highresistoron thesepinswill remainvalideven if thepin isusedasaTimer/EventCounterinput.

Timer/Event Counter Pins Internal FilterTheexternalTimer/EventCounterpinsareconnectedtoaninternalfiltertoreducethepossibilityofunwantedeventcountingeventsorinaccuratepulsewidthmeasurementsduetoadversenoiseorspikesontheexternalTimer/EventCounterinputsignal.Asthisinternalfiltercircuitwillconsumealimitedamountofpower,severalcontrolbitsnamedTMnFLTintheRCFLTregisterareprovidedtoswitchoffthefilterfunction,achoicewhichmaybebeneficialinpowersensitiveapplications,butinwhichtheintegrityoftheinputsignalishigh.

RC Filter Control Register − RCFLT

Bit 7 6 5 4 3 2 1 0Name — — INT1FLT INT0FLT TM3FLT TMFLT TM1FLT TM0FLTR/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas″0″Bit5 INT1FLT:ExternalInterrupt1inputRCFilterenablecontrol

Describedelsewhere.Bit4 INT0FLT:ExternalInterrupt0inputRCFilterenablecontrol

Describedelsewhere.Bit3 TM3FLT:Timer/EventCounter3inputRCFilterenablecontrol

0:Disable1:Enable

Bit2 TM2FLT:Timer/EventCounter2inputRCFilterenablecontrol0:Disable1:Enable



Rev. 1.10 6 ne 0 01 Rev. 1.10 7 ne 0 01



Programming ConsiderationsWhenconfiguredtorun in the timermode, the internalsystemclockisusedas the timerclocksourceandisthereforesynchronisedwiththeoveralloperationofthemicrocontroller.Inthismodewhentheappropriatetimerregister isfull, themicrocontrollerwillgenerateaninternal interruptsignaldirecting theprogramflowto therespective internal interruptvector.For thepulsewidthmeasurementmode,theinternalsystemclockisalsousedasthetimerclocksourcebutthetimerwillonlyrunwhenthecorrect logicconditionappearsontheexternal timerinputpin.Asthis isanexternaleventandnotsynchronizedwiththeinternaltimerclock,themicrocontrollerwillonlysee thisexternaleventwhenthenext timerclockpulsearrives.Asaresult, theremaybesmalldifferencesinmeasuredvaluesrequiringprogrammerstotakethisintoaccountduringprogramming.Thesameapplies if thetimerisconfiguredtobein theeventcountingmode,whichagainisanexternaleventandnotsynchronisedwiththeinternalsystemortimerclock.

WhentheTimer/EventCounter is read,or ifdata iswritten to thepreloadregister, theclock isinhibitedtoavoiderrors,howeverasthismayresultinacountingerror,thisshouldbetakenintoaccountbytheprogrammer.Caremustbetakentoensurethat thetimersareproperlyinitialisedbeforeusingthemforthefirsttime.Theassociatedtimerinterruptenablebitsintheinterruptcontrolregistermustbeproperlysetotherwisetheinternalinterruptassociatedwiththetimerwillremaininactive.Theedgeselect, timermodeandclocksourcecontrolbits intimercontrolregistermustalsobecorrectlyset toensure thetimer isproperlyconfiguredfor therequiredapplication.It isalsoimportanttoensurethataninitialvalueisfirstloadedintothetimerregistersbeforethetimerisswitchedon;thisisbecauseafterpower-ontheinitialvaluesofthetimerregistersareunknown.Afterthetimerhasbeeninitialisedthetimercanbeturnedonandoffbycontrollingtheenablebitinthetimercontrolregister.Notethatsettingthetimerenablebithightoturnthetimeron,shouldonlybeexecutedafter thetimermodebitshavebeenproperlysetup.Settingthetimerenablebithightogetherwithamodebitmodification,mayleadtoimpropertimeroperationifexecutedasasingletimercontrolregisterbytewriteinstruction.

WhentheTimer/Eventcounteroverflows,itscorrespondinginterruptrequestflagintheinterruptcontrolregisterwillbeset.If thetimerinterruptisenabledthiswill inturngenerateaninterruptsignal.Howeverirrespectiveofwhethertheinterruptsareenabledornot,aTimer/Eventcounteroverflowwillalsogenerateawake-upsignal if thedevice is inaPower-downcondition.ThissituationmayoccuriftheTimer/EventCounterisintheEventCountingModeandiftheexternalsignalcontinues tochangestate.Insuchacase, theTimer/EventCounterwillcontinuetocounttheseexternaleventsandifanoverflowoccursthedevicewillbewokenupfromitsPower-downcondition.Topreventsuchawake-upfromoccurring,thetimerinterruptrequestflagshouldfirstbesethighbeforeissuingtheHALTinstructiontoenterthePowerDownMode.

Rev. 1.10 6 ne 0 01 Rev. 1.10 7 ne 0 01



Timer Program ExampleThisprogramexampleshowshowtheTimer/EventCounterregistersaresetup,alongwithhowtheinterruptsareenabledandmanaged.NotehowtheTimer/EventCounteristurnedon,bysettingbit4of theTimerControlRegister.TheTimer/EventCountercanbeturnedoff inasimilarwaybyclearingthesamebit.ThisexampleprogramsetstheTimer/EventCountertobeinthetimermode,whichusestheinternalsystemclockastheclocksource.org 04h ; Smart Card interrupt vector retiorg 08h ; UART interrupt vector retiorg 0ch ; External interrupt 0 vector retiorg 10h ; External interrupt 1 vector retiorg 14h ; Timer/Event Counter 0 interrupt vectorjmp tmr0int ; jump here when the Timer/Event Counter 0 overflows :org 2Ch ; internal Timer/Event Counter 0 interrupt routinetmr0int: : ; Timer/Event Counter 0 main program placed here reti : :begin: ; setup Timer 0 registersmov a,09bh ; setup Timer 0 preload valuemov tmr0,a;mov a,081h ; setup Timer 0 control registermov tmr0c,a ; timer mode and prescaler set to /2 ; setup interrupt registermov a,002h ; timer 0 interruptmov int1c,aset int0c.0 ; enable master interruptset tmr0c.4 ; start Timer/Event Counter 0 - note mode bits must be previously setup

Rev. 1.10 8 ne 0 01 Rev. 1.10 9 ne 0 01



Pulse Width ModulatorThedevicecontainsaseriesofPulseWidthModulation,PWM,outputs.Usefulfortheapplicationssuchasmotorspeedcontrol,thePWMfunctionprovidesanoutputwithafixedfrequencybutwithadutycyclethatcanbevariedbysettingparticularvaluesintothecorrespondingPWMregister.

PWM Mode PWM Channels Output Pin Register Names

8+

PWM0 PC PWM0H/PWM0LPWM1 PC5 PWM1H/PWM1LPWM PC6 PWM2H/PWM2LPWM3 PA5 PWM3H/PWM3L

PWM OverviewAregisterpair,locatedintheDataMemoryisassignedtoeachPulseWidthModulatoroutputandareknownasthePWMregisters.It isineachregisterpairthatthe12-bitvalue,whichrepresentstheoveralldutycycleofonemodulationcycleof theoutputwaveform,shouldbeplaced.ThePWMregistersalsocontain theenable/disablecontrolbit for thePWMoutputs.To increasethePWMmodulation frequency,eachmodulationcycle ismodulated into sixteen individualmodulationsub-sections,knownasthe8+4mode.Notethatitisonlynecessarytowritetherequiredmodulationvalue into thecorrespondingPWMregisteras thesubdivisionof thewaveformintoitssub-modulationcyclesis implementedautomaticallywithinthemicrocontrollerhardware.ThePWMclocksourceisthesystemclockfSYS.

Thismethodofdividing theoriginalmodulationcycle intoa further16sub-cyclesenables thegenerationofhigherPWMfrequencies,whichallowawiderrangeofapplicationstobeserved.AslongastheperiodsofthegeneratedPWMpulsesarelessthanthetimeconstantsoftheload,thePWMoutputwillbesuitableassuchlongtimeconstant loadswillaverageout thepulsesof thePWMoutput.ThedifferencebetweenwhatisknownasthePWMcyclefrequencyandthePWMmodulationfrequencyshouldbeunderstood.AsthePWMclockisthesystemclock,fSYS,andasthePWMvalueis12-bitswide,theoverallPWMcyclefrequencyisfSYS/4096.However,wheninthe8+4modeofoperation,thePWMmodulationfrequencywillbefSYS/256.

PWM Modulation Frequency PWM Cycle Frequency PWM Cycle DutyfSYS/56 fSYS/096 (PWM register value)/4096

Rev. 1.10 8 ne 0 01 Rev. 1.10 9 ne 0 01



8+4 PWM Mode ModulationEachfullPWMcycle,as it is12-bitswide,has4096clockperiods.However, in the8+4PWMmode,eachPWMcycleissubdividedintosixteenindividualsub-cyclesknownasmodulationcycle0~modulationcycle15,denotedas″i″inthetable.Eachoneofthesesixteensub-cyclescontains256clockcycles.Inthismode,amodulationfrequencyincreaseofsixteenisachieved.The12-bitPWMregistervalue,whichrepresents theoveralldutycycleof thePWMwaveform, isdividedintotwogroups.Thefirstgroupwhichconsistsofbit4~bit11isdenotedhereastheDCvalue.Thesecondgroupwhichconsistsofbit0~bit3isknownastheACvalue.Inthe8+4PWMmode,thedutycyclevalueofeachofthetwomodulationsub-cyclesisshowninthefollowingtable.

Parameter AC (0~15) DC (Duty Cycle)

Modlation cycle i (i=0~15)

i<AC (DC+1)/256i≥AC DC/56

8+4 Mode Modulation Cycle Values

Theaccompanyingdiagram illustrates thewaveformsassociatedwith the8+4modeofPWMoperation. It is important tonotehow thesinglePWMcycle is subdivided into16 individualmodulationcycles,numbered0~15andhowtheACvalueisrelatedtothePWMvalue.

PWM Output ControlThefourPWM0~PWM3outputsaresharedwithI/Opins.TooperateasaPWMoutputandnotasanI/Opin, therelevantPWMenablecontrolbit inPWMnLregistermustbesethighwherendenotes0from3.Azeromustalsobewrittentothecorrespondingbitintherelevantportcontrolregister,toensurethatthePWMoutputpinissetupasanoutput.Afterthesetwoinitialstepshavebeencarriedout,andofcourseaftertherequiredPWM12-bitvaluehasbeenwrittenintothePWMregisterpairregister,writinga″1″tothecorrespondingportdataregisterwillenablethePWMdatatoappearonthepin.Writinga″0″tothebitwilldisablethePWMoutputfunctionandforcetheoutputlow.Inthisway,thePortdataregisterbits,canalsobeusedasanon/offcontrolforthePWMfunction.NotethatiftheenablebitinthePWMnLregisterissethightoenablethePWMfunction,buta″1″hasbeenwrittentoitscorrespondingbitintheportcontrolregistertoconfigurethepinasaninput,thenthepincanstillfunctionasanormalinputline,withpull-highresistorselections.

8+4 PWM Mode

Rev. 1.10 50 ne 0 01 Rev. 1.10 51 ne 0 01



PWM Register Pairs − PWMnH/PWMnL (n=0~3)

PWMnH Register

Bit 7 6 5 4 3 2 1 0Name D11 D10 D9 D8 D7 D6 D5 DR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

PWMnL Register

Bit 7 6 5 4 3 2 1 0Name D3 D D1 D0 — — — PWMnENR/W R/W R/W R/W R/W — — — R/WPOR 0 0 0 0 — — — 0

″—″Unimplemented,readas″0″D11~D4: PWMndutyDCvalueD3~D0:PWMndutyACvaluePWMnEN:PWMnoutputenablecontrol

0:I/Opinenable1:PWMoutputpinenable

PWM Programming ExampleThefollowingsampleprogramshowshowthePWMoutputissetupandcontrolled.mov a,64h ; setup PWM0 value to 1600 decimal which is 640Hmov pwm0h,a ; setup PWM0H register valueclr pwm0l ; setup PWM0L register valueclr pcc.4 ; setup pin PC4 as an outputset pwm0en ; set the PWM0 enable bitset pc.4 ; Enable the PWM0 output : : : :clr pc.4 ; PWM0 output disabled - PC4 will remain low

Rev. 1.10 50 ne 0 01 Rev. 1.10 51 ne 0 01



Analog to Digital ConverterTheneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigital signalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.

A/D Converter Structure

A/D OverviewThedevicecontainsan8-channelanalogtodigitalconverterwhichcandirectlyinterfacetoexternalanalogsignals,suchasthatfromsensorsorothercontrolsignalsandconvertthesesignalsdirectlyintoeithera12-bitdigitalvalue.

Input Channels Conversion Bits Input Pins8 1 PA0~PA1, PC0~PC1, PA4~PA7

TheaccompanyingblockdiagramshowstheoverallinternalstructureoftheA/Dconverter,togetherwithitsassociatedregisters.

A/D Converter Data Registers − ADRL, ADRHThedevice,whichhasan internal12-bitA/Dconverter, requires twodataregisters,ahighbyteregister,knownasADRH,andalowbyteregister,knownasADRL.Aftertheconversionprocesstakesplace, these registerscanbedirectly readby themicrocontroller toobtain thedigitisedconversionvalue.Only thehighbyte register,ADRH,utilises its full8-bitcontents.The lowbyteregisterutilisesonly4bitofits8-bitcontentsasitcontainsonlythelowestbitsofthe12-bitconvertedvalue.

Inthefollowingtable,D0~D11istheA/Dconversiondataresultbits.

Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0ADRL D3 D D1 D0 — — — —ADRH D11 D10 D9 D8 D7 D6 D5 D

A/D Data Registers

Rev. 1.10 5 ne 0 01 Rev. 1.10 53 ne 0 01



A/D Converter Control Registers − ADCR, ADPCR, ACSRTocontrolthefunctionandoperationoftheA/Dconverter,threecontrolregistersknownasADCR,ADPCRandACSRareprovided.These8-bit registersdefinefunctionssuchas theselectionofwhichanalogchannel isconnectedto the internalA/Dconverter,whichpinsareusedasanaloginputsandwhichareusedasnormalI/Os, theA/Dclocksourceaswellascontrolling thestartfunctionandmonitoringtheA/Dconverterendofconversionstatus.

TheACS2~ACS0bitsintheADCRregisterdefinethechannelnumber.Asthedevicecontainsonlyoneactualanalogtodigitalconvertercircuit,eachoftheindividual8analoginputsmustberoutedtotheconverter.ItisthefunctionoftheACS2~ACS0bitsintheADCRregistertodeterminewhichanalogchannelisactuallyconnectedtotheinternalA/Dconverter.

TheADPCRcontrolregistercontainsthePCR7~PCR0bitswhichdeterminewhichpinsonI/OPortsareusedasanaloginputsfortheA/DconverterandwhichpinsaretobeusedasnormalI/Opins.IfthePCRnbithasavalueof1,therelatedI/Opinwillbesetasananaloginput.IfthePCRnbitissettozero,thentherelatedI/OpinwillbesetupasanormalI/Oorotherpin-sharedfunctionalpin.

ACSR Register

Bit 7 6 5 4 3 2 1 0Name TEST ADONB ACS VBGEN VREFS ADCS ADCS1 ADCS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 0 0 0 0 0 0

Bit7 TEST:Fortestonly,readas1Bit6 ADONB:A/DConverterenablecontrol

0:A/Dconverteristurnedon1:A/Dconverteristurnedoff

Bit5 ACS4:InternalBand-gapreferencevoltagechannelinputselection0:A/DconverteranalogchannelisconnectedtotheanaloginputfromAN0toAN/71:A/DconverteranalogchannelisconnectedtotheinternalBand-gapvoltageVBG

Bit4 VBGEN:Band-gapreferencevoltageenablecontrol0:Band-gapvoltageVBGisdisabledandconnectedtotheground1:Band-gapvoltageVBGisenabled

Theband-gapreferencevoltageVBG isusedfor theA/DconverterandLVD/LVRfunction,whichiscontrolledbytheband-gapreferencevoltageenablebitVBGENintheACSRregister.IftheVBGisnotusedfortheA/DconverterandtheLVD/LVRfunction isdisabled, themicrocontrollerhardwarewill automatically turnedofftheband-gapreferencevoltagetoconservepower.CaremustbetakenaswhentheVREFSbit issethighfor theA/Dconverter, thenaVBG turnon timetBGmustbeallowedbeforeanyA/Dconversionsareimplemented.

Bit3 VREFS:A/Dconverterreferencevoltageselectionbit0:FromtheinternalvoltageAVDD

1:FromtheexternalpinVREFTheA/Dreferencevoltagecancomefromeither theinternalvoltageAVDDor theexternalvoltageVREF,whichisselectedbytheVREFSbitintheACSRregister.WhentheVREFSbitisclearedto0,thereferencevoltageoftheA/DconvertercomesfromtheinternalA/DpowersupplyAVDDandtheexternalVREFpincanbeusedasanI/Opinorotherpin-sharedfunction.WhentheVREFSbit isset to1, thereferencevoltageoftheA/DconvertercomesfromtheexternalVREFpinandtheI/Oorotherpin-sharedfunctionsaredisabled.

Rev. 1.10 5 ne 0 01 Rev. 1.10 53 ne 0 01



Bit2~0 ADCS2~ADCS0:SelectA/Dconverterclocksource000:fSYS/2001:fSYS/8010:fSYS/32011:Undefined100:fSYS

101:fSYS/4110:fSYS/16111:Undefined

ADCR Register

Bit 7 6 5 4 3 2 1 0Name START EOCB — — — ACS ACS1 ACS0R/W R/W R — — — R/W R/W R/WPOR 0 1 — — — 0 0 0

Bit7 START:StarttheA/Dconversion0→1→0:start0→1:resettheA/DconverterandsetEOCBto″1″

Bit6 EOCB:EndofA/DConversionflag0:A/Dconversionended1:A/Dconversionwaitingorinprogress

Bit5~3 Unimplemented,readas″0″Bit2~0 ACS2~ACS0:A/Dconverterchannelselectionbits

000:AN0isselected001:AN1isselected010:AN2isselected011:AN3isselected100:AN4isselected101:AN5isselected110:AN6isselected111:AN7isselected

ADPCR Register

Bit 7 6 5 4 3 2 1 0Name PCR7 PCR6 PCR5 PCR PCR3 PCR PCR1 PCR0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 PCR7~PCR0:A/Dconverteranalogchannelconfiguration0:I/Opinorotherpin-sharedfunction1:A/Danalogchannel

Whentherelatedbitissetto1,thecorrespondingpinisusedasananaloginputandallotherpin-sharedfunctionsaredisabledautomatically.

Rev. 1.10 5 ne 0 01 Rev. 1.10 55 ne 0 01



A/D OperationTheSTARTbitintheregisterisusedtostartandresettheA/Dconverter.Whenthemicrocontrollersets thisbit fromlowtohighandthen lowagain,ananalog todigitalconversioncyclewillbeinitiated.WhentheSTARTbitisbroughtfromlowtohighbutnotlowagain,theEOCBbitintheADCRregisterwillbesettoa″1″andtheanalogtodigitalconverterwillbereset.ItistheSTARTbitthatisusedtocontroltheoverallon/offoperationoftheinternalanalogtodigitalconverter.

TheEOCBbitintheADCRregisterisusedtoindicatewhentheanalogtodigitalconversionprocessiscomplete.Thisbitwillbeautomaticallysetto″0″bythemicrocontrollerafteraconversioncyclehasended.Inaddition, thecorrespondingA/Dinterruptrequestflagwillbeset in the interruptcontrolregister,andif the interruptsareenabled,anappropriate internal interruptsignalwillbegenerated.ThisA/Dinternal interruptsignalwilldirect theprogramflowto theassociatedA/Dinternalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,themicrocontrollercanbeusedtopolltheEOCBbitintheADCRregistertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.

TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,isfirstdividedbyadivisionratio,thevalueofwhichisdeterminedbytheADCS2,ADCS1andADCS0bitsintheACSRregister.

Controllingtheon/offfunctionoftheA/DconvertercircuitryisimplementedusingtheADONBbitintheACSRregister.WhentheADONBbitisclearedto0,theA/Dconverterisenabled.

AlthoughtheA/DclocksourceisdeterminedbythesystemclockfSYS,andbybitsADCS2~ADCS0,thereare some limitationson theA/Dclocksource speed range thatcanbe selected.As therecommendedrangeofpermissibleA/Dclockperiod,tAD,isfrom0.5μsto10μs,caremustbetakenforselectedsystemclockfrequencies.Forexample,ifthesystemclockoperatesatafrequencyof4MHzor2MHz,theADCS2~ADCS0bitsshouldnotbesetto100Bor010Brespectively.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/DclockperiodorgreaterthanthemaximumA/Dclockperiodwhichmayresult in inaccurateA/Dconversionvalues.Refer to thefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybelessthanthespecifiedminimumA/DClockPeriod.

fSYS

A/D Clock Period (tAD)ADCS=000 (tAD=2/fSYS)

ADCS=001 (tAD=8/fSYS)


ADCS=011 (undefined)




ADCS=111 (undefined)

1MHz µs 8µs 32µs* Undefined 1µs µs 16µs* Undefined2MHz 1µs µs 16µs* Undefined 500ns µs 8µs Undefined4MHz 500ns µs 8µs Undefined 250ns* 1µs µs Undefined8MHz 250ns* 1µs µs Undefined 125ns* 500ns µs Undefined12MHz 167ns* 667ns .67µs Undefined 83ns* 333ns* 1.33µs Undefined

A/D Clock Period Examples

Rev. 1.10 5 ne 0 01 Rev. 1.10 55 ne 0 01



A/D Input PinsAllof theA/Danalog inputpinsarepin-sharedwith the I/OpinsonPortAandPortC in theADPCRregister,determinewhethertheinputpinsaresetupasnormalinput/outputpinsorwhethertheyaresetupasanaloginputs.Inthisway,pinscanbechangedunderprogramcontroltochangetheirfunctionfromnormalI/Ooperationtoanaloginputsandviceversa.Pull-highresistors,whicharesetupthroughregisterprogramming,applytotheinputpinsonlywhentheyareusedasnormalI/Opins,ifsetupasA/Dinputsthepull-highresistorswillbeautomaticallydisconnected.NotethatitisnotnecessarytofirstsetuptheA/DpinasaninputintheportcontrolregistertoenabletheA/DinputaswhenthePCR7~PCR0bitsenableanA/Dinput,thestatusoftheportcontrolregisterwillbeoverridden.TheA/DconverterhasitsownpowersupplypinsAVDDandAVSSandaVREFreferencepin.TheanaloginputvaluesmustnotbeallowedtoexceedthevalueofVREF.

Initialising the A/D ConverterTheinternalA/Dconvertermustbeinitialisedinaspecialway.EachtimetheA/Dchannelselectionbitsaremodifiedbytheprogram,theA/Dconvertermustbere-initialised.IftheA/Dconverterisnotinitialisedafterthechannelselectionbitsarechanged, theEOCBflagmayhaveanundefinedvalue,whichmayproduceafalseendofconversionsignal.ToinitialisetheA/Dconverterafterthechannelselectionbitshavechanged,thentheSTARTbitintheADCRregistermustfirstbesethighandthenimmediatelyclearedtozero.ThiswillensurethattheEOCBflagiscorrectlysettoahighcondition.

Summary of A/D Conversion StepsThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.

• Step1Select therequiredA/DconversionclockbycorrectlyprogrammingbitsADCS2,ADCS1andADCS0intheregister.

• Step2EnabletheA/DbyclearingtheADONBbitintheACSRregistertozero.

• Step3SelectwhichchannelistobeconnectedtotheinternalA/DconverterbycorrectlyprogrammingtheACS2~ACS0bitswhicharealsocontainedintheregister.

• Step4SelectwhichpinsontheI/OportaretobeusedasA/DinputsandconfigurethemasA/DinputpinsbycorrectlyprogrammingthePCR7~PCR0bitsintheADPCRregister.

• Step5If theinterruptsare tobeused, theinterruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dconverterinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,intheINTC0interruptcontrolregistermustbesetto″1″andtheA/Dconverterinterruptenablebit,EADI,intheINTC2registermustalsobesetto″1″.

• Step6Theanalog todigitalconversionprocesscannowbe initialisedbysetting theSTARTbit intheADCRregisterfrom″0″to″1″andthento″0″again.Notethat thisbitshouldhavebeenoriginallysetto″0″.

Rev. 1.10 56 ne 0 01 Rev. 1.10 57 ne 0 01



• Step7Tocheckwhentheanalogtodigitalconversionprocessiscomplete,theEOCBbitintheADCRregistercanbepolled.Theconversionprocessiscompletewhenthisbitgoeslow.WhenthisoccurstheA/DdataregistersADRLandADRHcanbereadtoobtaintheconversionvalue.Asanalternativemethodiftheinterruptsareenabledandthestackisnotfull,theprogramcanwaitforanA/Dinterrupttooccur.

Note:Whencheckingfortheendoftheconversionprocess,ifthemethodofpollingthebitintheADCRregisterisused,theinterruptenablestepabovecanbeomitted.

Theaccompanyingdiagramshowsgraphicallythevariousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.

The settingupandoperationof theA/Dconverter function is fullyunder thecontrolof theapplicationprogramastherearenoconfigurationoptionsassociatedwiththeA/Dconverter.AfteranA/Dconversionprocesshasbeeninitiatedbytheapplicationprogram,themicrocontrollerinternalhardwarewillbegintocarryouttheconversion,duringwhichtimetheprogramcancontinuewithotherfunctions.ThetimetakenfortheA/Dconversionis16tADwheretADisequaltotheA/Dclockperiod.

A/D Conversion Timing

Rev. 1.10 56 ne 0 01 Rev. 1.10 57 ne 0 01



Programming ConsiderationsTheA/DconvertercanbepowereddownbysettingtheADONBbit inACSRregister toreducepowerconsumption. It isan importantabilityforsomeapplicationssuchasbatterypoweredorhandheldappliance.

AnotherimportantprogrammingconsiderationisthatwhentheA/Dchannelselectionbitschangevalue, theA/Dconvertermustbere-initialised.ThisisachievedbypulsingtheSTARTbit intheADCRregisterimmediatelyafterthechannelselectionbitshavechangedstate.Theexceptiontothisiswherethechannelselectionbitsareallcleared,inwhichcasetheA/Dconverterisnotrequiredtobere-initialised.

A/D Programming ExampleThe following twoprogramming examples illustrate how to setup and implement anA/Dconversion.Inthefirstexample,themethodofpollingtheEOCBbitintheADCRregisterisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.

Example: using an EOCB polling method to detect the end of conversionclr EADI ; disable ADC interruptmov a,00000001Bmov ACSR,a ; select fSYS/8 as A/D clock and turn on ADONB bitmov a,0FH ; setup ADPCR register to configure I/O pins PA0~PA1 andmov ADPCR,a, ; PC0~PC1 as A/D inputsmov a,00H ; and select AN0 to be connected to the A/D convertermov ADCR,a ; As the analog channel configuration bits have changed : ; the following START signal (0-1-0) must be issued : : ; instruction cycles :Start_conversion: clr START set START ; reset A/D clr START ; start A/DPolling_: sz EOCB ; poll the ADCR register EOCB bit to detect end of A/D conversion jmp polling_EOC ; continue polling mov a,ADRL ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : jmp start_conversion ; start next A/D conversion

Rev. 1.10 58 ne 0 01 Rev. 1.10 59 ne 0 01



Example: using the interrupt method to detect the end of conversionclr EADI ; disable ADC interruptmov a,00000001Bmov ACSR,a ; select fSYS/8 as A/D clock and turn on ADONB bitmov a,0FH ; setup ADPCR register to configure I/O pins PA0~PA1 andmov ADPCR,a ; PC0~PC1 as A/D inputsmov a,00H ; and select AN0 to be connected to the A/D convertermov ADCR,a ; As the analog channel configuration bits have changed the : ; following START signal(0-1-0) must be issued instruction cycles : :Start_conversion:clr STARTset START ; reset A/Dclr START ; start A/Dclr ADF ; clear ADC interrupt request flagset EADI ; enable ADC interruptset EMI ; enable global interrupt : : : ; ADC interrupt service routineADC_:mov acc_stack,a ; save ACC to user defined memorymov a,STATUSmov status_stack,a ; save STATUS to user defined memory : :mov a,ADRL ; read low byte conversion result valuemov adrl_buffer,a ; save result to user defined registermov a,ADRH ; read high byte conversion result valuemov adrh_buffer,a ; save result to user defined register : :EXIT__ISR:mov a,status_stackmov STATUS,a ; restore STATUS from user defined memorymov a,acc_stack ; restore ACC from user defined memoryclr ADF ; clear ADC interrupt flagreti

Rev. 1.10 58 ne 0 01 Rev. 1.10 59 ne 0 01



A/D Transfer FunctionAsthedevicecontainsa12-bitA/Dconverter, itsfull-scaleconverteddigitisedvalueisequal toFFFH.Sincethefull-scaleanaloginputvalueisequaltotheVDDorVREFvoltage,thisgivesasinglebitanaloginputvalueof(VDDorVREF)÷4096).Thediagramshowsthe ideal transferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefortheA/Dconverter.

Notethat toreducethequantisationerror,a0.5LSBoffset isaddedtotheA/DConverter input.Exceptforthedigitisedzerovalue,thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitizedvaluewillchangeatapoint1.5LSBbelowtheVDDorVREFlevel.

Ideal A/D Transfer Function

Rev. 1.10 60 ne 0 01 Rev. 1.10 61 ne 0 01



Serial Interface Function − SIMThedevicecontains twoSerial InterfaceModulesnamedSIM0andSIM1to implementSerialInterfaceFunction,whichincludesboththefourlineSPIinterfaceandthetwolineI2Cinterfacetypes, toallowaneasymethodofcommunicationwithexternalperipheralhardware.Havingrelativelysimplecommunicationprotocols, theseserial interfacetypesallowthemicrocontrollerto interface toexternalSPIorI2Cbasedhardwaresuchassensors,FlashorEEPROMmemory,etc.TheSIMinterfacepinsarepin-sharedwithotherI/OpinsthereforetheSIMinterfacefunctionmustfirstbeselectedusingaconfigurationoption.Asbothinterfacetypessharethesamepinsandregisters,thechoiceofwhethertheSPIorI2Ctypeisusedismadeusingabitinaninternalregister.

SPI InterfaceTheSPIinterfaceisoftenusedtocommunicatewithexternalperipheraldevicessuchassensors,FlashorEEPROMmemorydevicesetc.OriginallydevelopedbyMotorola, the four lineSPIinterfaceisasynchronousserialdatainterfacethathasarelativelysimplecommunicationprotocolsimplifyingtheprogrammingrequirementswhencommunicatingwithexternalhardwaredevices.

Thecommunicationisfullduplexandoperatesasaslave/mastertype,wheretheMCUcanbeeithermasterorslave.AlthoughtheSPIinterfacespecificationcancontrolmultipleslavedevicesfromasinglemaster,here,asonlyasingleselectpin,SCSn, isprovidedonlyoneslavedevicecanbeconnectedtotheSPIbus.

SPI Master/Slave Connection

SPI Block Diagram

Rev. 1.10 60 ne 0 01 Rev. 1.10 61 ne 0 01



SPI Interface OperationTheSPIinterfaceisafullduplexsynchronousserialdatalink.It isafourlineinterfacewithpinnamesSDIn,SDOn,SCKnandSCSnwherenstands for0and1 respectively.PinsSDInandSDOnare theSerialDataInputandSerialDataOutput lines,SCKnis theSerialClocklineandSCSnis theSlaveSelect line.AstheSPI interfacepinsarepin-sharedwithnormalI/Opinsandwith theI2Cfunctionpins, theSPI interfacemustfirstbeenabledbyselecting theSIMnenableconfigurationoptionsandsettingthecorrectbits intheSIMnCTL0/SIMnCTL2register.AftertheSIMnconfigurationoptionhasbeenconfigureditcanalsobeadditionallydisabledorenabledusingtheSIMnENbitintheSIMnCTL0register.CommunicationbetweendevicesconnectedtotheSPIinterfaceiscarriedoutinaslave/mastermodewithalldatatransferinitiationsbeingimplementedbythemaster.TheMasteralsocontrolstheclocksignal.AseachSIMonlycontainsasingleSCSnpin,onlyoneslavedevicecanbeutilizedforeachSIM.

TheSPIfunctioninthisdeviceoffersthefollowingfeatures:

• Fullduplexsynchronousdatatransfer

• BothMasterandSlavemodes

• LSBfirstorMSBfirstdatatransmissionmodes

• Transmissioncompleteflag

• Risingorfallingactiveclockedge

• WCOLnandCSENnbitenabledordisableselect

Thestatusof theSPI interfacepins isdeterminedbyanumberof factorssuchaswhether thedeviceisinthemasterorslavemodeandupontheconditionofcertaincontrolbitssuchasCSENn,SIMnENandSCSn. In the table I,Z representsan input floatingcondition.ThereareseveralconfigurationoptionsassociatedwiththeSPIinterface.OneoftheseistoenabletheSIMnfunctionwhichselectstheSIMnpinsratherthannormalI/Opins.NotethatiftheconfigurationoptiondoesnotselecttheSIMnfunctionthentheSIMnENbitintheSIMnCTL0registerwillhavenoeffect.AnothertwoSIMnconfigurationoptionsdetermineiftheCSENnandWCOLnbitsaretobeused.

Configuration Option FunctionSIMn Fnction SIMn interface or I/O pinsSPI CSENn bit Enable/DisableSPI WCOLn bit Enable/Disable

SPI Interface Configuration Options

Pin Master/SlaveSIMnEN=0

Master – SIMnEN=1 Slave – SIMnEN=1

CSENn=1 CSENn=0 CSENn=0 SCSn Line=0(CSENn=1)

SCSn Line=1(CSENn=1)

SCSn Z L Z Z I Z I ZSDOn Z O O O O ZSDIn Z I Z I Z I Z I Z Z

SCKn Z H: CKPOLn=0L: CKPOLn=1

H: CKPOLn=1L: CKPOLn=0 I Z I Z Z

Note:″Z″floating,″H″outputhigh,″L″outputlow,″I″Input,″O″outputlevel,″I,Z″inputfloating(nopull-high)SPI Interface Pin Status

Rev. 1.10 6 ne 0 01 Rev. 1.10 63 ne 0 01



SPI RegistersTherearethreeinternalregisterswhichcontroltheoveralloperationoftheSPIinterfaceforeachSIM.ThesearetheSIMnDRdataregisterandtwocontrolregistersSIMnCTL0andSIMnCTL2.NotethattheSIMnCTL1registerisonlyusedbytheI2Cinterface.

Thereisacontrolbit,SIMIDLE,whichisusedtoselectwhetherthemasterSPIinterfacecontinuesrunningwhenthedeviceisintheIDLEmode.SettingthebithighallowstheclocksourceofthemasterSPI interfaceor thePeripheralclockPCLK,which isselected tocomefromthedividedsystemclock,tokeepactivewhenthedeviceisintheIDLEmode.ThiswillmaintainthemasterSPIinterfaceoperationorthePeripheralclockPCLKoutputactiveifthePCKENbitissetto1inIDLEmode.ClearingthebittozerodisablesanymasterSPIinterfaceoperationsorPCLKoutputintheIDLEmode.ThisSPI/I2Cidlemodecontrolbit,SIMIDLE,islocatedatCLKMODregisterbit4.

TheSIMnDRregister isusedtostorethedatabeingtransmittedandreceived.ThesameregisterisusedbyboththeSPIandI2Cfunctions.BeforethemicrocontrollerwritesdatatotheSPIbus,theactualdatatobetransmittedmustbeplacedintheSIMnDRregister.AfterthedataisreceivedfromtheSPIbus, themicrocontrollercanreaditfromtheSIMnDRregister.AnytransmissionorreceptionofdatafromtheSPIbusmustbemadeviatheSIMnDRregister.

• SIMnDR

Bits 7 6 5 4 3 2 1 0Name SnD7 SnD6 SnD5 SnD SnD3 SnD SnD1 SnD0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR X X X X X X X X

TherearealsotwocontrolregistersfortheSPIinterface,SIMnCTL0andSIMnCTL2.NotethattheSIMnCTL2registeralsohasthenameSIMnARwhichisusedbytheI2Cfunction.TheSIMnCTL1registerisnotusedbytheSPIfunction,onlybytheI2Cfunction.RegisterSIMnCTL0isusedtocontrol theenable/disablefunctionandtoset thedatatransmissionclockfrequency.AlthoughnotconnectedwiththeSPIfunction,theSIMnCTL0registerisalsousedtocontrolthePeripheralClockprescaler.RegisterSIMnCTL2isusedforothercontrolfunctionssuchasLSB/MSBselection,writecollisionflagetc.

Rev. 1.10 6 ne 0 01 Rev. 1.10 63 ne 0 01



• SIM0 Control Register 0 − SIM0CTL0

Bit 7 6 5 4 3 2 1 0Name S0SIM S0SIM1 S0SIM0 PCKEN PCKPSC1 PCKPSC0 SIM0EN —R/W R/W R/W R/W R/W R/W R/W R/W —POR 1 1 1 0 0 0 0 —

Bit7~5 S0SIM2~S0SIM0:SIM0modeandclockselection000:SIM0inSPImastermodewithfSYS/4clocksource001:SIM0inSPImastermodewithfSYS/16clocksource010:SIM0inSPImastermodewithfSYS/64clocksource011:SIM0inSPImastermodewithfSUBclocksource100:SIM0inSPImastermodewithTimer/EventCounter0overflow/2clock(PFD0)101:SIM0inSPIslavemode110:SIM0inI2Cmode111:Reserved

Bit4 PCKEN:PeripheralClockPCKenablecontrol0:PCKoutputisdisabled1:PCKoutputisenabled

Bit3~2 PCKPSC1~PCKPSC0:PeripheralClockPCKoutputclockprescaler00:fSYS

01:fSYS/410:fSYS/811:Timer/EventCounter0overflow/2(PFD0)

Bit1 SIM0EN:SIM0enablecontrol0:SIM0isdisabled1:SIM0isenabled

Bit0 Unimplemented,readas″0″

• SIM1 Control Register 0 − SIM1CTL0

Bit 7 6 5 4 3 2 1 0Name S1SIM S1SIM1 S1SIM0 D D3 D SIM1EN —R/W R/W R/W R/W R/W R/W R/W R/W —POR 1 1 1 0 0 0 0 —


Bit4~2 UndefinedbitThesebitscanbereadorwrittenbyusersoftwareprogram.


Bit0 Unimplemented,readas″0″

Rev. 1.10 6 ne 0 01 Rev. 1.10 65 ne 0 01



• SIMn Control Register 1 − SIMnCTL1 (n=0 or 1) for I2C Mode

Bit 7 6 5 4 3 2 1 0Name HCFn HAASn HBBn HTXn TXAKn SRWn — RXAKnR/W R/W R/W R/W R/W R/W R/W — R/WPOR 1 0 0 0 0 0 — 1

Bit7 HCFn:I2CBusdatatransfercompletionflag0:Dataisbeingtransferred1:Completionofan8-bitdatatransfer

TheHCFnflag is thedata transfer flag.This flagwillbezerowhendata isbeingtransferred.Uponcompletionofan8-bitdata transfer theflagwillgohighandaninterruptwillbegenerated.

Bit6 HAASn:I2CBusaddressmatchflag0:Noaddressmatch1:Addressmatch

TheHAASnflagistheaddressmatchflag.Thisflagisusedtodetermineiftheslavedeviceaddressisthesameasthemastertransmitaddress.Iftheaddressesmatch,thenthisbitwillbehigh.Ifthereisnoaddressmatch,thentheflagwillbelow.

Bit5 HBBn:I2CBusbusyflag0:I2CBusisnotbusy1:I2CBusisbusy

TheHBBnflagistheI2Cbusyflag.Thisflagwillbe1whentheI2CbusisbusywhichwilloccurwhenaSTARTsignalisdetected.Theflagwillbesetto0whenthebusisfreewhichwilloccurwhenaSTOPsignalisdetected.

Bit4 HTXn:SelectI2Cslavedeviceistransmitterorreceiver0:Slavedeviceisthereceiver1:Slavedeviceisthetransmitter

Bit3 TXAKn:I2CBustransmitacknowledgeflag0:Slavesendsacknowledgeflag1:Slavedoesnotsendacknowledgeflag

TheTXAKnbitisthetransmitacknowledgeflag.Aftertheslavedevicereceiptof8-bitofdata,thisbitwillbetransmittedtothebusonthe9thclockfromtheslavedevice.TheslavedevicemustalwayssetTXAKnbitto0beforefurtherdataisreceived.

Bit2 SRWn:I2CSlaveRead/Writeflag0:Slavedeviceshouldbeinreceivemode1:Slavedeviceshouldbeintransmitmode

TheSRWnflagis theI2CSlaveRead/Writeflag.Thisflagdetermineswhether themasterdevicewishes to transmitorreceivedata toorfromtheI2Cbus.Whenthetransmittedaddressandslaveaddress ismatch, that iswhentheHAASnflagissethigh, theslavedevicewillchecktheSRWnflagtodeterminewhether itshouldbeintransmitmodeorreceivemode.IftheSRWnflagishigh,themasterisrequestingtoreaddatafromthebus,sotheslavedeviceshouldbeintransmitmode.WhentheSRWnflagiszero, themasterwillwritedata to thebus, thereforetheslavedeviceshouldbeinreceivemodetoreadthisdata.

Bit1 Unimplemented,readas″0″Bit0 RXAKn:I2CBusReceiveacknowledgeflag

0:Slavereceivesacknowledgeflag1:Slavedoesnotreceiveacknowledgeflag

TheRXAKnflag is thereceiveracknowledgeflag.WhentheRXAKnflag is0, itmeansthataacknowledgesignalhasbeenreceivedatthe9thclock,after8bitsofdatahavebeentransmitted.Whentheslavedeviceinthetransmitmode,theslavedevicecheckstheRXAKnflagtodetermineifthemasterreceiverwishestoreceivethenextbyte.TheslavetransmitterwillthereforecontinuesendingoutdatauntiltheRXAKnflagis1.Whenthisoccurs,theslavetransmitterwillreleasetheSDAnlinetoallowthemastertosendaSTOPsignaltoreleasetheI2CBus.

Rev. 1.10 6 ne 0 01 Rev. 1.10 65 ne 0 01



• SIMn Control Register 2 − SIMnCTL2 (n=0 or 1) for SPI Mode

Bit 7 6 5 4 3 2 1 0Name — — CKPOLn CKEGn MLSn CSENn WCOLn TRFnR/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Undefinedbit,readas"0"Bit5 CKPOLn:DeterminesthebaseconditionoftheSPIclockline

0:TheSCKnlinewillbehighwhentheSPIclockisinactive1:TheSCKnlinewillbelowwhentheSPIclockisinactive

TheCKPOLnbitdeterminesthebaseconditionoftheSPIclockline,ifthebitishigh,thentheSCKnlinewillbelowwhentheclockisinactive.WhentheCKPOLnbitislow,thentheSCKnlinewillbehighwhentheclockisinactive.

Bit4 CKEGn:DeterminesSPISCKnactiveclockedgetypeCKPOLn=00:SCKnishighbaselevelanddatacaptureatSCKnrisingedge1:SCKnishighbaselevelanddatacaptureatSCKnfallingedge

CKPOLn=10:SCKnislowbaselevelanddatacaptureatSCKnfallingedge1:SCKnislowbaselevelanddatacaptureatSCKnrisingedge

TheCKEGnandCKPOLnbitsareusedtosetupthewaythattheclocksignaloutputsandinputsdataontheSPIbus.Thesetwobitsmustbeconfiguredbeforedatatransferisexecutedotherwiseanerroneousclockedgemaybegenerated.TheCKPOLnbitdeterminesthebaseconditionoftheclockline.Ifthebitishigh,thentheSCKnlinewillbelowwhentheclockisinactive.WhentheCKPOLnbitislow,thentheSCKnlinewillbehighwhentheclockisinactive.TheCKEGnbitdeterminesactiveclockedgetypewhichdependsupontheconditionofCKPOLnbit.

Bit3 MLSn:SPIDatashiftorder0:LSBshiftfirst1:MSBshiftfirst

Thisisthedatashiftselectbitandisusedtoselecthowthedataistransferred,eitherMSBorLSBfirst.SettingthebithighwillselectMSBfirstandlowforLSBfirst.

Bit2 CSENn:SPISCSnpincontrol0:Disable1:Enable

TheCSENnbit isusedasanenable/disablefortheSCSnpin.If thisbit is low,thentheSCSnpinwillbedisabledandplacedintoafloatingcondition.IfthebitishightheSCSnpinwillbeenabledandusedasaselectpin.NotethatusingtheCSENnbitcanbedisabledorenabledviaconfigurationoption.

Bit1 WCOLn:SPIWriteCollisionflag0:Nocollision1:Collision

TheWCOLnflagisusedtodetectifadatacollisionhasoccurred.IfthisbitishighitmeansthatdatahasbeenattemptedtobewrittentotheSIMnDRregisterduringadatatransferoperation.Thiswritingoperationwillbeignoredifdataisbeingtransferred.Thebitcanbeclearedbytheapplicationprogram.NotethatusingtheWCOLnbitcanbedisabledorenabledviaconfigurationoption.

Bit0 TRFn:SPITransmit/ReceiveCompleteflag0:Dataisbeingtransferred1:SPIdatatransmissioniscompleted

TheTRFnbitistheTransmit/ReceiveCompleteflagandissetto1automaticallywhenanSPIdatatransmissioniscompleted,butmustsetto0bytheapplicationprogram.Itcanbeusedtogenerateaninterrupt.

Rev. 1.10 66 ne 0 01 Rev. 1.10 67 ne 0 01



SPI CommunicationAftertheSPIinterfaceisenabledbysettingtheSIMnENbithigh,thenintheMasterMode,whendata iswritten to theSIMnDRregister, transmission/receptionwillbeginsimultaneously.Whenthedatatransferiscomplete,theTRFnflagwillbesetautomatically,butmustbeclearedusingtheapplicationprogram.IntheSlaveMode,whentheclocksignalfromthemasterhasbeenreceived,anydataintheSIMnDRregisterwillbetransmittedandanydataontheSDInpinwillbeshiftedintotheSIMnDRregister.ThemastershouldoutputaSCSnsignaltoenabletheslavedevicebeforeaclocksignalisprovidedandslavedatatransfersshouldbeenabled/disabledbefore/afteraSCSnsignalisreceived.

TheSPIwillcontinuetofunctionevenafteraHALTinstructionhasbeenexecuted.

SPI Master Mode Timing

SPI Slave Mode Timing (CKEGn=0)

Rev. 1.10 66 ne 0 01 Rev. 1.10 67 ne 0 01



SPI Slave Mode Timing (CKEGn=1)

SPI Transfer Control Flowchart

Rev. 1.10 68 ne 0 01 Rev. 1.10 69 ne 0 01



I2C InterfaceThe I2C interface isused to communicatewith externalperipheraldevices suchas sensors,EEPROMmemoryetc.OriginallydevelopedbyPhilips,it isatwolinelowspeedserialinterfaceforsynchronousserialdatatransfer.Theadvantageofonlytwolinesforcommunication,relativelysimplecommunicationprotocolandtheabilitytoaccommodatemultipledevicesonthesamebushasmadeitanextremelypopularinterfacetypeformanyapplications.

I2C Block Diagram

I2C Interface OperationTheI2Cserialinterfaceisatwolineinterface,aserialdataline,SDAn,andserialclockline,SCLn.Asmanydevicesmaybeconnected togetheronthesamebus, theiroutputsarebothopendraintypes.Forthisreasonitisnecessarythatexternalpull-highresistorsareconnectedtotheseoutputs.Notethatnochipselectlineexists,aseachdeviceontheI2CbusisidentifiedbyauniqueaddresswhichwillbetransmittedandreceivedontheI2Cbus.

WhentwodevicescommunicatewitheachotheronthebidirectionalI2Cbus,oneisknownasthemasterdeviceandoneas theslavedevice.Bothmasterandslavecantransmitandreceivedata,however, it isthemasterdevicethathasoverallcontrolofthebus.Forthesedevices,whichonlyoperatesinslavemode,therearetwomethodsoftransferringdataontheI2Cbus,theslavetransmitmodeandtheslavereceivemode.

ThereareseveralconfigurationoptionsassociatedwiththeI2Cinterface.OneoftheseistoenablethefunctionwhichselectstheSIMnpinsratherthannormalI/Opins.NotethatiftheconfigurationoptiondoesnotselecttheSIMnfunctionthentheSIMnENbitintheSIMnCTL0registerwillhavenoeffect.AconfigurationoptionexiststoallowaclockotherthanthesystemclocktodrivetheI2Cinterface.AnotherconfigurationoptiondeterminesthedebouncetimeoftheI2Cinterface.Thisusestheinternalclocktoineffectaddadebouncetimetotheexternalclocktoreducethepossibilityofglitchesontheclocklinecausingerroneousoperation.Thedebouncetime,ifselected,canbechosentobeeither1or2systemclocks.

Configuration Option FunctionSIMn fnction SIMn interface or I/O pinsIC debonce No debonce 1 system clock; system clocks

I2C Interface Configuration Options

Rev. 1.10 68 ne 0 01 Rev. 1.10 69 ne 0 01



I2C RegistersTherearethreecontrolregistersassociatedwiththeI2Cbus,SIMnCTL0,SIMnCTL1andSIMnARandonedataregister,SIMnDR.TheSIMnDRregister,whichisshownintheaboveSPIsection,isusedtostorethedatabeingtransmittedandreceivedontheI2Cbus.BeforethemicrocontrollerwritesdatatotheI2Cbus,theactualdatatobetransmittedmustbeplacedintheSIMnDRregister.After thedata is received fromthe I2Cbus, themicrocontrollercan read it fromtheSIMnDRregister.AnytransmissionorreceptionofdatafromtheI2Cbusmustbemadevia theSIMnDRregister.Note that theSIMnARregisteralsohas thenameSIMnCTL2whichisusedbytheSPIfunction.BitsSIMIDLE,SIMnENandbitsSnSIM0~SnSIM2inregisterSIMnCTL0areusedbytheI2Cinterface.

WhenthedeviceisintheIDLEmode,theSIMIDLEbithasnoeffectiftheI2Cinterfaceisselectedtobeused.SettingthebithighonlyallowstheclocksourceofthePeripheralclockPCLK,whichisselectedtocomefromthedividedsystemclock,tokeepactivewhenthedeviceisintheIDLEmode.ItwillmaintainthePeripheralclockPCLKoutputactiveifthePCKENbitissetto1inIDLEmode.ClearingthebittozerodisablesthePCLKoutputwhenthedeviceisintheIDLEmode.ThisSPI/I2Cidlemodecontrolbit,SIMIDLE,islocatedatCLKMODregisterbit4.

• SIMnDR

Bits 7 6 5 4 3 2 1 0Name SnD7 SnD6 SnD5 SnD SnD3 SnD SnD1 SnD0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR X X X X X X X X

“x”: nknown

• SIMnAR Register

Bit 7 6 5 4 3 2 1 0Name SnA6 SnA5 SnA SnA3 SnA SnA1 SnA0 —R/W R/W R/W R/W R/W R/W R/W R/W —POR x x x x x x x —

“x”: nknownBit7~1 SnA6~SnA0:I2Cslaveaddress

SnA6~SnA0istheI2Cslaveaddressbit6~bit0.TheSIMnARregisterisalsousedbytheSPIinterfacebuthasthenameSIMnCTL2.TheSIMnARregisteristhelocationwherethe7-bitslaveaddressoftheslavedeviceisstored.Bit7~bit1oftheSIMnARregisterdefinethedeviceslaveaddress.Bit0isnotdefined.Whenamasterdevice,whichisconnectedtotheI2Cbus,sendsoutanaddress,whichmatchestheslaveaddressintheSIMnARregister, theslavedevicewillbeselected.Notethat theSIMnARregister is thesameregisteraddressasSIMnCTL2whichisusedbytheSPIinterface.

Bit0 UnimplementedbitThisbitcanbereadorwrittenbyusersoftwareprogram.

Rev. 1.10 70 ne 0 01 Rev. 1.10 71 ne 0 01



• SIM0 Control Register 0 – SIM0CTL0

Bit 7 6 5 4 3 2 1 0Name S0SIM S0SIM1 S0SIM0 PCKEN PCKPSC1 PCKPSC0 SIM0EN —R/W R/W R/W R/W R/W R/W R/W R/W —POR 1 1 1 0 0 0 0 —


Bit4 PCKEN:PeripheralClockPCKenablecontrol0:PCKoutputisdisabled1:PCKoutputisenabled

Bit3~2 PCKPSC1~PCKPSC0:PeripheralClockPCKoutputclockprescaler00:fSYS

01:fSYS/410:fSYS/811:Timer/EventCounter0overflow/2(PFD0)


Bit0 Unimplemented,readas“0”

• SIM1 Control Register 0 – SIM1CTL0

Bit 7 6 5 4 3 2 1 0Name S1SIM S1SIM1 S1SIM0 D D3 D SIM1EN —R/W R/W R/W R/W R/W R/W R/W R/W —POR 1 1 1 0 0 0 0 —


Bit4~2 UndefinedbitThesebitscanbereadorwrittenbyusersoftwareprogram.


Bit0 Unimplemented,readas“0”

Rev. 1.10 70 ne 0 01 Rev. 1.10 71 ne 0 01



• SIMn Control Register 1 – SIMnCTL1 (n=0 or 1) for I2C mode

Bit 7 6 5 4 3 2 1 0Name HCFn HAASn HBBn HTXn TXAKn SRWn — RXAKnR/W R/W R/W R/W R/W R/W R/W — R/WPOR 1 0 0 0 0 0 — 0

Bit7 HCFn:I2CBusdatatransfercompletionflag0:Dataisbeingtransferred1:Completionofan8-bitdatatransfer

TheHCFnflag is thedata transfer flag.This flagwillbezerowhendata isbeingtransferred.Uponcompletionofan8-bitdata transfer theflagwillgohighandaninterruptwillbegenerated.

Bit6 HAASn:I2CBusaddressmatchflag0:Noaddressmatch1:Addressmatch

TheHAASnflagistheaddressmatchflag.Thisflagisusedtodetermineiftheslavedeviceaddressisthesameasthemastertransmitaddress.Iftheaddressesmatch,thenthisbitwillbehigh.Ifthereisnoaddressmatch,thentheflagwillbelow.

Bit5 HBBn:I2CBusbusyflag0:I2CBusisnotbusy1:I2CBusisbusy

TheHBBnflagistheI2Cbusyflag.Thisflagwillbe1whentheI2CbusisbusywhichwilloccurwhenaSTARTsignalisdetected.Theflagwillbesetto0whenthebusisfreewhichwilloccurwhenaSTOPsignalisdetected.

Bit4 HTXn:SelectI2Cslavedeviceistransmitterorreceiver0:Slavedeviceisthereceiver1:Slavedeviceisthetransmitter

Bit3 TXAKn:I2CBustransmitacknowledgeflag0:Slavesendsacknowledgeflag1:Slavedoesnotsendacknowledgeflag

TheTXAKnbitisthetransmitacknowledgeflag.Aftertheslavedevicereceiptof8-bitofdata,thisbitwillbetransmittedtothebusonthe9thclockfromtheslavedevice.TheslavedevicemustalwayssetTXAKnbitto0beforefurtherdataisreceived.

Bit2 SRWn:I2CSlaveRead/Writeflag0:Slavedeviceshouldbeinreceivemode1:Slavedeviceshouldbeintransmitmode

TheSRWnflagis theI2CSlaveRead/Writeflag.Thisflagdetermineswhether themasterdevicewishes to transmitorreceivedata toorfromtheI2Cbus.Whenthetransmittedaddressandslaveaddress ismatch, that iswhentheHAASnflagissethigh, theslavedevicewillchecktheSRWnflagtodeterminewhether itshouldbeintransmitmodeorreceivemode.IftheSRWnflagishigh,themasterisrequestingtoreaddatafromthebus,sotheslavedeviceshouldbeintransmitmode.WhentheSRWnflagiszero, themasterwillwritedata to thebus, thereforetheslavedeviceshouldbeinreceivemodetoreadthisdata.

Bit1 Unimplemented,readas“0”Bit0 RXAKn:I2CBusReceiveacknowledgeflag

0:Slavereceivesacknowledgeflag1:Slavedoesnotreceiveacknowledgeflag

TheRXAKnflag is thereceiveracknowledgeflag.WhentheRXAKnflag is0, itmeansthataacknowledgesignalhasbeenreceivedatthe9thclock,after8bitsofdatahavebeentransmitted.Whentheslavedeviceinthetransmitmode,theslavedevicecheckstheRXAKnflagtodetermineifthemasterreceiverwishestoreceivethenextbyte.TheslavetransmitterwillthereforecontinuesendingoutdatauntiltheRXAKnflagis1.Whenthisoccurs,theslavetransmitterwillreleasetheSDAnlinetoallowthemastertosendaSTOPsignaltoreleasetheI2CBus.

Rev. 1.10 7 ne 0 01 Rev. 1.10 73 ne 0 01



I2C Bus CommunicationCommunicationontheI2Cbusrequiresfourseparatesteps,aSTARTsignal,aslavedeviceaddresstransmission,adatatransmissionandfinallyaSTOPsignal.WhenaSTARTsignalisplacedontheI2Cbus,alldevicesonthebuswillreceivethissignalandbenotifiedoftheimminentarrivalofdataonthebus.ThefirstsevenbitsofthedatawillbetheslaveaddresswiththefirstbitbeingtheMSB.Iftheaddressofthemicrocontrollermatchesthatofthetransmittedaddress,theHAASnbitintheSIMnCTL1registerwillbesetandanI2Cinterruptwillbegenerated.Afterenteringtheinterruptserviceroutine, themicrocontrollerslavedevicemustfirstchecktheconditionoftheHAASnbittodeterminewhethertheinterruptsourceoriginatesfromanaddressmatchorfromthecompletionofan8-bitdata transfer.Duringadata transfer,note thatafter the7-bitslaveaddresshasbeentransmitted,thefollowingbit,whichisthe8thbit, istheread/writebitwhosevaluewillbeplacedintheSRWnbit.Thisbitwillbecheckedbythemicrocontrollertodeterminewhethertogointotransmitorreceivemode.BeforeanytransferofdatatoorfromtheI2Cbus, themicrocontrollermustinitialisethebus.Thefollowingarestepstoachievethis:

• Step1WritetheslaveaddressofthemicrocontrollertotheI2CbusaddressregisterSIMnAR.

• Step2SettheSIMnENbitintheSIMnCTL0registerto″1″toenabletheI2Cbus.

• Step3SettheESIMnbitandSIMMuti-FunctioninterruptenablebitoftheinterruptcontrolregistertoenabletheI2Cbusinterrupt.

I2C Bus Initialisation Flow Chart

Rev. 1.10 7 ne 0 01 Rev. 1.10 73 ne 0 01



Start SignalTheSTARTsignalcanonlybegeneratedbythemasterdeviceconnectedtotheI2Cbusandnotbythemicrocontroller,whichisonlyaslavedevice.ThisSTARTsignalwillbedetectedbyalldevicesconnectedtotheI2Cbus.Whendetected, this indicatesthat theI2CbusisbusyandthereforetheHBBnbitwillbeset.ASTARTconditionoccurswhenahightolowtransitionontheSDAnlinetakesplacewhentheSCLnlineremainshigh.

Slave AddressThetransmissionofaSTARTsignalbythemasterwillbedetectedbyalldevicesontheI2Cbus.Todeterminewhichslavedevicethemasterwishestocommunicatewith,theaddressoftheslavedevicewillbesentoutimmediatelyfollowingtheSTARTsignal.Allslavedevices,afterreceivingthis7-bitaddressdata,willcompareitwiththeirown7-bitslaveaddress.Iftheaddresssentoutbythemastermatchestheinternaladdressofthemicrocontrollerslavedevice,thenaninternalI2Cbusinterruptsignalwillbegenerated.Thenextbitfollowingtheaddress,whichisthe8thbit,definestheread/writestatusandwillbesavedtotheSRWnbitoftheSIMnCTL1register.Thedevicewillthentransmitanacknowledgebit,whichisalowlevel,asthe9thbit.

ThemicrocontrollerslavedevicewillalsosetthestatusflagHAASnwhentheaddressesmatch.AsanI2Cbusinterruptcancomefromtwosources,whentheprogramenterstheinterruptsubroutine,theHAASnbitshouldbeexaminedtoseewhethertheinterruptsourcehascomefromamatchingslaveaddressorfromthecompletionofadatabytetransfer.Whenaslaveaddressismatched,thedevicemustbeplacedineitherthetransmitmodeandthenwritedatatotheSIMnDRregister,orinthereceivemodewhereitmustimplementadummyreadfromtheSIMnDRregistertoreleasetheSCLnline.

SRW BitTheSRWnbitintheSIMnCTL1registerdefineswhetherthemicrocontrollerslavedevicewishestoreaddatafromtheI2CbusorwritedatatotheI2Cbus.Themicrocontrollershouldexaminethisbittodetermineifitistobeatransmitterorareceiver.IftheSRWnbitissetto″1″thenthisindicatesthatthemasterwishestoreaddatafromtheI2Cbus,thereforethemicrocontrollerslavedevicemustbesetuptosenddatatotheI2Cbusasatransmitter.IftheSRWnbitis″0″thenthisindicatesthatthemasterwishestosenddatatotheI2Cbus,thereforethemicrocontrollerslavedevicemustbesetuptoreaddatafromtheI2Cbusasareceiver.

Acknowledge BitAfter themasterhas transmitted a calling address, any slavedeviceon the I2Cbus,whoseown internaladdressmatches thecallingaddress,mustgenerateanacknowledgesignal.Thisacknowledgesignalwill informthemasterthataslavedevicehasaccepteditscallingaddress.Ifnoacknowledgesignal isreceivedbythemaster thenaSTOPsignalmustbetransmittedbythemastertoendthecommunication.WhentheHAASnbitishigh,theaddresseshavematchedandthemicrocontrollerslavedevicemustchecktheSRWnbittodetermineifitistobeatransmitterorareceiver.IftheSRWnbitishigh,themicrocontrollerslavedeviceshouldbesetuptobeatransmittersotheHTXnbit in theSIMnCTL1registershouldbeset to″1″if theSRWnbit is lowthenthemicrocontrollerslavedeviceshouldbesetupasareceiverand theHTXnbit in theSIMnCTL1registershouldbesetto″0″.

Rev. 1.10 7 ne 0 01 Rev. 1.10 75 ne 0 01



Data ByteThe transmitteddata is8-bitswideand is transmittedafter theslavedevicehasacknowledgedreceiptofitsslaveaddress.TheorderofserialbittransmissionistheMSBfirstandtheLSBlast.Afterreceiptof8-bitsofdata,thereceivermusttransmitanacknowledgesignal,level″0″,beforeitcanreceivethenextdatabyte.Ifthetransmitterdoesnotreceiveanacknowledgebitsignalfromthereceiver,thenitwillreleasetheSDAnlineandthemasterwillsendoutaSTOPsignaltoreleasecontroloftheI2Cbus.ThecorrespondingdatawillbestoredintheSIMnDRregister.Ifsetupasa transmitter, themicrocontrollerslavedevicemustfirstwrite thedatatobetransmittedintotheSIMnDRregister.Ifsetupasareceiver,themicrocontrollerslavedevicemustreadthetransmitteddatafromtheSIMnDRregister.

Receive Acknowledge BitWhenthereceiverwishestocontinuetoreceivethenextdatabyte,itmustgenerateanacknowledgebit,knownasTXAKn,on the9thclock.Themicrocontroller slavedevice,which issetupasatransmitterwillchecktheRXAKnbitintheSIMnCTL1registertodetermineifitistosendanotherdatabyte,ifnotthenitwillreleasetheSDAnlineandawaitthereceiptofaSTOPsignalfromthemaster.

Data Timing Diagram

I2C Communication Timing Diagram

Rev. 1.10 7 ne 0 01 Rev. 1.10 75 ne 0 01



I2C Bus ISR Flow Chart

Rev. 1.10 76 ne 0 01 Rev. 1.10 77 ne 0 01



Peripheral Clock OutputThePeripheralClockOutputallowsthedevice tosupplyexternalhardwarewithaclocksignalsynchronisedtothemicrocontrollerclock.

Peripheral Clock OperationAstheperipheralclockoutputpin,PCLK,issharedwithanI/Oline,therequiredpinfunctionischosenviaPCKENintheSIM0CTL0register.ThePeripheralClockfunctioniscontrolledusingtheSIM0CTL0register.TheclocksourceforthePeripheralClockOutputcanoriginatefromeithertheTimer/EventCounter0overflowsignaldividedbytwooradividedratiooftheinternalfSYSclock.ThePCKENbitintheSIM0CTL0registeristheoverallon/offcontrol,settingthebithighenablesthePeripheralClock,clearing itdisables it.The requireddivision ratioof thesystemclock isselectedusingthePCKPSC0andPCKPSC1bitsinthesameregister.IfthesystementerstheSleepMode,thePeripheralClockoutputwillbedisabled.

Peripheral Clock Block Diagram

Rev. 1.10 76 ne 0 01 Rev. 1.10 77 ne 0 01



BuzzerOperatinginasimilarwaytotheProgrammableFrequencyDivider,theBuzzerfunctionprovidesameansofproducingavariablefrequencyoutput,suitableforapplicationssuchasPiezo-buzzerdrivingorotherexternalcircuits thatrequireaprecisefrequencygenerator.TheBZandBZpinsformacomplementarypair,andarepin-sharedwithI/Opins,PA0andPA1.Aconfigurationoptionisusedtoselectfromoneofthreebuzzeroptions.ThefirstoptionisforbothpinsPA0andPA1tobeusedasnormalI/Os,thesecondoptionisforbothpinstobeconfiguredasBZandBZbuzzerpins,thethirdoptionselectsonlythePA0pintobeusedasaBZbuzzerpinwiththePA1pinretainingitsnormalI/Opinfunction.NotethattheBZpinistheinverseoftheBZpinwhichtogethergenerateadifferentialoutputwhichcansupplymorepowertoconnectedinterfacessuchasbuzzers.

Thebuzzerisdrivenbytheinternalclocksource,whichthenpassesthroughadivider,thedivisionratioofwhichisselectedbyconfigurationoptionstoprovidearangeofbuzzerfrequenciesfromfS/22 to fS/29.Theclocksource thatgenerates fS,which in turncontrols thebuzzer frequency,canoriginatefromthreedifferentsources, theexternal32.768kHzoscillator(LXT), the internal32kHzRCoscillator(LIRC)ortheSystemoscillatordividedby4(fSYS/4), thechoiceofwhichisdeterminedbythefSclocksourceconfigurationoption.Notethatthebuzzerfrequencyiscontrolledbyconfigurationoptions,whichselectboththesourceclockfortheinternalclockfSandtheinternaldivisionratio.Therearenointernalregistersassociatedwiththebuzzerfrequency.

If theconfigurationoptionshaveselectedbothpinsPA0andPA1 to functionasaBZandBZcomplementarypairofbuzzeroutputs,thenforcorrectbuzzeroperationitisessentialthatbothpinsmustbesetupasoutputsbysettingbitsPAC0andPAC1ofthePACportcontrolregistertozero.ThePA0databitinthePAdataregistermustalsobesethightoenablethebuzzeroutputs,ifsetlow,bothpinsPA0andPA1willremainlow.InthiswaythesinglebitPA0ofthePAregistercanbeusedasanon/offcontrolforboththeBZandBZbuzzerpinoutputs.NotethatthePA1databitinthePAregisterhasnocontrolovertheBZbuzzerpinPA1.

Buzzer Function

Rev. 1.10 78 ne 0 01 Rev. 1.10 79 ne 0 01



PA0/PA1 Pin Function Control

PAC Register PAC0

PAC Register PAC1

PA Data Register PA0

PA Data Register PA1 Output Function

0 0 1 x PA0=BZ PA1=BZ

0 0 0 x PA0=″0″ PA1=″0″

0 1 1 x PA0=BZ PA1=input line

0 1 0 x PA0=″0″ PA1=input line

1 0 x D PA0=input line PA1=D

1 1 x x PA0=input line PA0=input line

″x" stands for don′t care, ″D″ stands for Data ″0″ or ″1″IfconfigurationoptionshaveselectedthatonlythePA0pinistofunctionasaBZbuzzerpin,thenthePA1pincanbeusedasanormalI/Opin.ForthePA0pintofunctionasaBZbuzzerpin,PA0mustbesetupasanoutputbysettingbitPAC0ofthePACportcontrolregistertozero.ThePA0databitinthePAdataregistermustalsobesethightoenablethebuzzeroutput,ifsetlowpinPA0willremainlow.InthiswaythePA0bitcanbeusedasanon/offcontrolfortheBZbuzzerpinPA0.IfthePAC0bitofthePACportcontrolregisterissethigh,thenpinPA0canstillbeusedasaninputeventhoughtheconfigurationoptionhasconfigureditasaBZbuzzeroutput.

Buzzer Output Pin Control

Note:Theabovedrawingshows thesituationwherebothpinsPA0andPA1are selectedbyconfigurationoptiontobeBZandBZbuzzerpinoutputs.ThePortControlRegisterofbothpinsmusthavealreadybeensetupasoutput.ThedatasetuponpinPA1hasnoeffectonthebuzzeroutputs.

Notethatnomatterwhatconfigurationoptionischosenforthebuzzer,iftheportcontrolregisterhassetupthepintofunctionasaninput,thenthiswilloverridetheconfigurationoptionselectionandforcethepintoalwaysbehaveasaninputpin.Thisarrangementenablesthepintobeusedasbothabuzzerpinandasaninputpin,soregardlessoftheconfigurationoptionchosen;theactualfunctionofthepincanbechangeddynamicallybytheapplicationprogrambyprogrammingtheappropriateportcontrolregisterbit.

Rev. 1.10 78 ne 0 01 Rev. 1.10 79 ne 0 01



InterruptsInterruptsareanimportantpartofanymicrocontrollersystem.WhenanexternaleventoraninternalfunctionsuchasaTimer/EventCounteroranA/Dconverter requiresmicrocontrollerattention,theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontroller todirectattentiontotheirrespectiveneeds.Thedevicecontainsseveralexternalinterruptandinternalinterruptsfunctions.TheexternalinterruptsarecontrolledbytheactionoftheexternalINT0,INT1andPINTpins,whiletheinternalinterruptsarecontrolledbytheTimer/EventCounteroverflows,theTimeBaseinterrupt,theRTCinterrupt,theSIM(SPI/I2C)interrupt,theA/Dconverterinterrupt,theUARTinterruptandSmartCardinterrupt.

Interrupt Structure

Rev. 1.10 80 ne 0 01 Rev. 1.10 81 ne 0 01



Interrupt RegistersOverallinterruptcontrol,whichmeansinterruptenablingandrequestflagsetting,iscontrolledbytheINTC0,INTC1,INTC2,MFIC0andMFIC1registers,whicharelocatedintheDataMemory.Bycontrollingtheappropriateenablebitsintheseregisterseachindividualinterruptcanbeenabledordisabled.Alsowhenan interruptoccurs, thecorresponding request flagwillbe setby themicrocontroller.Theglobalenableflagifclearedtozerowilldisableallinterrupts.

INTC0 Register

Bit 7 6 5 4 3 2 1 0Name — EIF0 URF CRDF EEI0 URE CRDE EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas″0″Bit6 EIF0:Externalinterrupt0interruptrequestflag

0:Inactive1:Active

Bit5 URF:UARTinterruptrequestflag0:Inactive1:Active

Bit4 CRDF:SmartCardinterruptrequestflag0:Inactive1:Active

Bit3 EEI0:Externalinterrupt0enable0:Disable1:Enable

Bit2 URE:UARTinterruptenable0:Disable1:Enable

Bit1 CRDE:SmartCardinterruptenable0:Disable1:Enable

Bit0 EMI:Masterinterruptglobalenable0:Disable1:Enable

Rev. 1.10 80 ne 0 01 Rev. 1.10 81 ne 0 01



INTC1 Register

Bit 7 6 5 4 3 2 1 0Name SCIRF T1F T0F EIF1 CIRE ET1I ET0I EEI1R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 SCIRF:SmartCardInsertion/Removalinterruptrequestflag0:Inactive1:Active

ThisbitistriggeredbytheCIRFbitofCSRregister.Bit6 T1F:Timer/EventCounter1interruptrequestflag

0:Inactive1:Active

Bit5 T0F:Timer/EventCounter0interruptrequestflag0:Inactive1:Active

Bit4 EIF1:Externalinterrupt1requestflag0:Inactive1:Active

Bit3 CIRE:SmartCardInsertion/Removalinterruptenable0:Disable1:Enable

Bit2 ET1I:Timer/EventCounter1interruptenable0:Disable1:Enable


Bit0 EEI1:Externalinterrupt1interruptenable0:Disable1:Enable

Rev. 1.10 8 ne 0 01 Rev. 1.10 83 ne 0 01



INTC2 Register

Bit 7 6 5 4 3 2 1 0Name — MF1F MF0F ADF — EMF1I EMF0I EADIR/W — R/W R/W R/W — R/W R/W R/WPOR — 0 0 0 — 0 0 0

Bit7 Unimplemented,readas″0″Bit6 MF1F:Multi-Function1interruptrequestflag

0:Inactive1:Active

Bit5 MF0F:Multi-function0interruptrequestflag0:Inactive1:Active

Bit4 ADF:A/DConverterinterruptrequestflag0:Inactive1:Active

Bit3 Unimplemented,readas″0″Bit2 EMF1I:Multi-Function1interruptenable

0:Disable1:Enable

Bit1 EMF0I:Multi-Function0interruptenable0:Disable1:Enable

Bit0 EADI:A/DConverterinterruptenable0:Disable1:Enable

Rev. 1.10 8 ne 0 01 Rev. 1.10 83 ne 0 01



MFIC0 Register

Bit 7 6 5 4 3 2 1 0Name PEF TBF RTF SIM0F EPI ETBI ERTI ESIM0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 PEF:ExternalPeripheralinterruptrequestflag0:Inactive1:Active

Bit6 TBF:TimeBaseinterruptrequestflag0:Inactive1:Active

Bit5 RTF:RealTimeClockinterruptrequestflag0:Inactive1:Active

Bit4 SIM0F:SIM0(SPI/I2C)interruptrequestflag0:Inactive1:Active

Bit3 EPI:ExternalPeripheralinterruptenable0:Disable1:Enable

Bit2 ETBI:TimeBaseinterruptenable0:Disable1:Enable

Bit1 ERTI:RealTimeClockinterruptenable0:Disable1:Enable

Bit0 ESIM0:SIM0(SPI/I2C)interruptenable0:Disable1:Enable

Rev. 1.10 8 ne 0 01 Rev. 1.10 85 ne 0 01



MFIC1 Register

Bit 7 6 5 4 3 2 1 0Name — T3F TF SIM1F — ET3I ETI ESIM1R/W — R/W R/W R/W — R/W R/W R/WPOR — 0 0 0 — 0 0 0

Bit7 Unimplemented,readas″0″Bit6 T3F:Timer/EventCounter3interruptrequestflag

0:Inactive1:Active

Bit5 T2F:Timer/EventCounter2interruptrequestflag0:Inactive1:Active

Bit4 SIM1F:SIM1(SPI/I2C)interruptrequestflag0:Inactive1:Active

Bit3 Unimplemented,readas″0″Bit2 ET3I:Timer/EventCounter3interruptenable

0:Disable1:Enable


Bit0 ESIM1:SIM1(SPI/I2C)interruptenable0:Disable1:Enable

Interrupt OperationATimer/EventCounteroverflow,TimeBase,RTCoverflow,SPI/I2Cdatatransfercomplete,anendofA/Dconversion,UARTevent,SmartCardevent,SmartCardinsertion/removalortheexternalinterrupt linebeingtriggeredwillallgenerateaninterruptrequestbysettingtheircorrespondingrequest flag.Whenthishappensand if theirappropriate interruptenablebit isset, theProgramCounter,whichstorestheaddressof thenext instructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwill thenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwill thenfetchitsnextinstructionfromthisinterruptvector.TheinstructionatthisvectorwillusuallybeaJMPstatementwhichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontrol theappropriateinterrupt.TheinterruptserviceroutinemustbeterminatedwithaRETIstatement,whichretrievestheoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagramwiththeirorderofpriority.

Onceaninterruptsubroutineisserviced,alltheotherinterruptswillbeblocked,astheEMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However,ifotherinterruptrequestsoccurduringthisinterval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.

Rev. 1.10 8 ne 0 01 Rev. 1.10 85 ne 0 01



Interrupt PriorityInterrupts,occurringintheintervalbetweentherisingedgesoftwoconsecutiveT2pulses,willbeservicedonthelatterofthetwoT2pulses,if thecorrespondinginterruptsareenabled.Incaseofsimultaneousrequests,thefollowingtableshowstheprioritythatisapplied.

Interrupt Source Priority VectorSmart Card Interrpt 1 04HUART Interrpt 08HExternal Interrpt 0 3 0CHExternal Interrpt 1 10HTimer/Event Counter 0 Overflow 5 14HTimer/Event Counter 1 Overflow 6 18HSmart Card Insertion/Removal Interrpt 7 1CHA/D Converter Interrpt 8 20HMlti-fnction 0 Interrpt 9 24HMlti-fnction 1 Interrpt 10 28H

TheSIM0interrupt,RealTimeclockinterrupt,TimeBaseinterruptandExternalPeripheralinterruptshare thesameinterruptvectorwhich is24Hwhile theSIM1interrupt,Timer/EventCounter2overflowandTimer/EventCounter3overflowinterruptsharethesameinterruptvectorwhichis28H.Eachoftheseinterruptshastheirownindividualinterruptflagbutalsosharethesamemulti-functioninterruptflagnamedMF0ForMF1Frespectively.TheMF0ForMF1FflagwillbeclearedbyhardwareoncethecorrespondingMulti-functioninterruptisserviced.HowevertheindividualinterruptsthathavetriggeredtheMulti-functioninterruptneedtobeclearedbytheapplicationprogram.

External InterruptForanexternalinterrupttooccur,theglobalinterruptenablebit,EMI,andexternalinterruptenablebits,EEI0andEEI1,mustfirstbeset.AdditionallythecorrectinterruptedgetypemustbeselectedusingtheMISC0register toenabletheexternal interruptfunctionandtochoosethetriggeredgetype.Anactualexternalinterruptwill takeplacewhentheexternalinterruptrequestflag,EIF0orEIF1,isset,asituationthatwilloccurwhenatransition,whosetypeischosenbytheedgeselectbit,appearsontheINT0orINT1pin.Theexternalinterruptpinsarepin-sharedwiththeI/OpinsPA0andPA1andcanonlybeconfiguredasexternalinterruptpinsiftheircorrespondingexternalinterruptenablebit in theINTC0orINTC1registerhasbeenset.ThepinmustalsobesetupasaninputbysettingthecorrespondingPAC.0andPAC.1bitsintheportcontrolregister.Whentheinterrupt isenabled, thestack isnotfulland thecorrect transitiontypeappearson theexternalinterruptpin,asubroutinecall to theexternal interruptvectorat location0CHor10H,will takeplace.Whenthe interrupt isserviced, theexternal interrupt request flags,EIF0orEIF1,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorselectionson thispinwill remainvalideven if thepin isusedasanexternalinterruptinput.

TheMISC0registerisusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.Achoiceofeitherrising,fallingorbothrisingandfallingedgetypescanbechosentotriggeranexternalinterrupt.NotethattheMISC0registercanalsobeusedtodisabletheexternalinterruptfunction.

Theexternalinterruptpinsareconnectedtoaninternalfiltertoreducethepossibilityofunwantedexternal interruptsdue toadversenoiseorspikeson theexternal interrupt inputsignal.As thisinternal filtercircuitwillconsumea limitedamountofpower, thesoftwarecontrolbitsnamedINT0FLTandINT1FLTrespectively in theRCFLTregisterareprovided toswitchoff thefilterfunction,anoptionwhichmaybebeneficial inpowersensitiveapplications,but inwhich theintegrityoftheinputsignalishigh.

Rev. 1.10 86 ne 0 01 Rev. 1.10 87 ne 0 01



MISC0 Register

Bit 7 6 5 4 3 2 1 0Name CRDCKS1 CRDCKS0 SMF SMCEN INT1S1 INT1S0 INT0S1 INT0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 CRDCKS1~CRDCKS0:SmartCardinterfaceclocksourcedividedratioselectionDescribedelsewhere

Bit5 SMF:SmartCardclockoutputCCLKfrequencyfCCLKselectionDescribedelsewhere

Bit4 SMCEN:SmartCardinterfaceclockcontrolDescribedelsewhere

Bit3~2 INT1S1~INT1S0:ExternalInterrupt1activeedgeselection00:Disabled01:Risingedgetrigger10:Fallingedgetrigger11:Bothrisingandfallingedgestrigger

Bit1~0 INT0S1~INT0S0:ExternalInterrupt0activeedgeselection00:Disabled01:Risingedgetrigger10:Fallingedgetrigger11:Bothrisingandfallingedgestrigger

RC Filter Control Register – RCFLT

Bit 7 6 5 4 3 2 1 0Name — — INT1FLT INT0FLT TM3FLT TMFLT TM1FLT TM0FLTR/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas″0″Bit5 INT1FLT:ExternalInterrupt1inputRCFilterenablecontrol

0:Disabled1:Enable

Bit4 INT0FLT:ExternalInterrupt0inputRCFilterenablecontrol0:Disabled1:Enable

Bit3 TM3FLT:Timer/EventCounter3inputRCFilterenablecontrolDescribedelsewhere.




Rev. 1.10 86 ne 0 01 Rev. 1.10 87 ne 0 01



External Peripheral InterruptTheExternalPeripheralInterruptoperatesinasimilarwaytotheexternalinterruptandiscontainedwithintheMulti-function0interrupt.

Foranexternalperipheralinterrupttooccur,theglobalinterruptenablebit,EMI,externalperipheralinterruptenablebit,EPI,andMulti-function0interruptenablebit,EMF0I,mustfirstbeset.Anactualexternalperipheral interruptwill takeplacewhentheexternal interruptrequestflag,PEF,isset,asituationthatwilloccurwhenanegativetransition,appearsonthePINTpin.Theexternalperipheral interruptpin ispin-sharedwithoneof theI/Opins,andisconfiguredasaperipheralinterruptpinviathecorrespondingportcontrolregisterbit.Whentheinterruptisenabled,thestackisnotfullandanegativetransitiontypeappearsontheexternalperipheralinterruptpin,asubroutinecall to theMulti-function interruptvectorat location24H,will takeplace.When theexternalperipheralinterruptisserviced,theEMIbitwillbeclearedtodisableotherinterrupts,howeveronlytheMF0Finterruptrequestflagwillbereset.AsthePEFflagwillnotbeautomaticallyreset,ithastobeclearedbytheapplicationprogram.

Timer/Event Counter InterruptForaTimer/EventCounter0orTimer/EventCounter1interrupttooccur,theglobalinterruptenablebit,EMI,andthecorrespondingtimerinterruptenablebit,ET0IorET1Imustfirstbeset.AnactualTimer/EventCounterinterruptwill takeplacewhentheTimer/EventCounterrequestflag,T0ForT1Fisset,asituationthatwilloccurwhentheTimer/EventCounteroverflows.Whentheinterruptisenabled, thestackisnotfullandaTimer/EventCounteroverflowoccurs,asubroutinecall tothetimerinterruptvectorat location14Hor18H,will takeplace.Whentheinterruptisserviced,the timer interruptrequestflag,T0ForT1F,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

TimerEventCounter0andTimer/EventCounter1have theirownindividual interruptvectors.However the interruptvectorforTimer/EventCounter2orTimer/Eventcounter3 iscontainedwithin theMulti-function1Interrupt.ForaTimer/EventCounter2oraTimer/Eventcounter3interrupt tooccur, theglobal interruptenablebit,EMI,Timer/EventCounter2orTimer/Eventcounter3interruptenablebit,ET2IorET3I,andMulti-function1interruptenablebit,EMF1I,mustfirstbeset.Anactual interruptwill takeplacewhentheTimer/EventCounter2orTimer/Eventcounter3requestflag,T2ForT3F,isset,asituationthatwilloccurwhentheTimer/EventCounter2orTimer/Eventcounter3overflows.Whentheinterruptisenabled,thestackisnotfullandtheTimer/EventCounter2orTimer/Eventcounter3overflows,asubroutinecalltotheMulti-functioninterruptvectoratlocation28H,will takeplace.WhentheTimer/Event2orTimer/Eventcounter3 interrupt isserviced, theEMIbitwillbeclearedtodisableother interrupts,howeveronly theMulti-functioninterruptrequestflagwillbereset.AstheT2ForT3Fflagwillnotbeautomaticallyreset,ithastobeclearedbytheapplicationprogram.

Rev. 1.10 88 ne 0 01 Rev. 1.10 89 ne 0 01



A/D InterruptForanA/DInterrupt tobegenerated, theglobal interruptenablebitEMIandtheA/DInterruptenablebitEADImustfirstbeset.AnactualA/DInterruptwilltakeplacewhentheA/DInterruptrequestflag,ADF,isset,asituationthatwilloccurwhentheA/Dconversionprocesshasfinished.Whentheinterrupt isenabled, thestackisnotfullandtheA/Dconversionprocesshasended,asubroutinecalltotheA/Dinterruptvectoratlocation20H,willtakeplace.WhentheA/DInterruptisserviced,theA/DinterruptrequestflagADFwillbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

Smart Card InterruptForaSmartCardInterrupttobegenerated,theglobalinterruptenablebitEMImustfirstbesetaswellasoneof theassociatedSmartCardeventInterruptenablebits.TheSmartCardeventsthatwillgenerateaninterruptincludesituationssuchasaCardvoltageerror,aCardcurrentoverload,awaitingtimeroverflow,aparityerror,atransmitbufferemptyoranendoftransmissionorreception.OnceoneoftheassociatedSmartCardeventinterruptenablecontrolbitsisset,itwillautomaticallysettheCRDEbitto1toenabletherelatedSmartCardinterrupt.AnactualSmartCardInterruptwilltakeplacewhentheSmartCardInterruptrequestflag,CRDF,isset,asituationthatwilloccurwhenaSmartCardeventhasoccurred.Whentheinterrupt isenabled, thestackisnotfullandaSmartCardeventhasoccurred,asubroutinecalltotheSmartCardinterruptvectoratlocation04H,willtakeplace.WhentheSmartCardInterruptisserviced,theSmartCardinterruptrequestflagCRDFwillbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

Smart Card Insertion/Removal InterruptForaSmartCardInsertion/RemovalInterrupttobegenerated,theglobalinterruptenablebitEMIandtheSmartCardInsertion/RemovalinterruptenablebitCIREmustfirstbeset.AnactualSmartCardInsertion/RemovalInterruptwilltakeplacewhentheSmartCardInsertion/RemovalInterruptrequestflag,SCIRF, isset,asituationthatwilloccurwhentheSmartCardhasbeeninsertedorremoved.Whentheinterruptisenabled,thestackisnotfullandtheSmartCardhasbeeninsertedor removed,asubroutinecall to theSmartCardInsertion/RemovalInterruptvectorat location1CH,willtakeplace.WhentheSmartCardInsertion/RemovalInterruptisserviced,theSmartCardInsertion/RemovalinterruptrequestflagSCIRFwillbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

SIM (SPI/I2C Interface) InterruptsThetwoSIM(SPI/I2C)interruptsnamedSIM0interruptandSIM1interruptarecontainedwithintheMulti-function0InterruptandMulti-function1Interruptrespectively.

ForanSIM(SPI/I2Cinterface)interrupttooccur, theglobalinterruptenablebitnamedEMI,theassociatedSIMinterruptenablecontrolbitnamedESIM0orESIM1andtheMulti-functioninterruptenablebitnamedEMF0IorEMF1Imustbefirstset.AnactualSIM(SPI/I2Cinterface)interruptwilltakeplacewhentheSIM(SPI/I2Cinterface)requestflag,SIM0ForSIM1F,isset,asituationthatwilloccurwhenabyteofdatahasbeentransmittedorreceivedbytheSPI/I2CinterfaceorwhenanI2Caddressmatchoccurs.Whentheinterruptisenabled,thestackisnotfullandabyteofdatahasbeentransmittedorreceivedbytheSPI/I2CinterfaceoranI2Caddressmatchoccurs,asubroutinecall totheSIM(SPI/I2Cinterface)interruptvectorat location24Hor28Hrespectively,will takeplace.WhenSIMthe interrupt isserviced, theEMIbitwillbeautomaticallycleared todisableotherinterrupts,howeveronlytheMF0ForMF1Finterruptrequestflagwillbereset.AstheSIMrequestflagknownasSIM0ForSIM1Fwillnotbeautomaticallyreset,ithastobeclearedbytheapplicationprogram.

Rev. 1.10 88 ne 0 01 Rev. 1.10 89 ne 0 01



Multi-function InterruptTwoadditional interruptsknownas theMulti-function0interruptandMulti-function1interruptareprovided.Unlike theother interrupts, the interrupthasno independentsource,but rather isformedfromseveralotherexistinginterruptsources.TheMulti-function0interruptcontains theSIM0interrupt,TimeBaseinterrupt,RealTimeClockinterrupt,ExternalPeripheralinterruptwhiletheMulti-function1interruptcontainstheSIM1interrupt,Timer2overflowinterruptandTimer3overflowinterrupt.

ForaMulti-functioninterrupttooccur,theglobalinterruptenablebit,EMI,andtheMulti-functioninterruptenablebit,EMF0IorEMF1I,mustfirstbeset.AnactualMulti-functioninterruptwilltakeplacewhentheMulti-functioninterruptrequestflag,MF0ForMF1F,isset.ThiswilloccurwheneitheraTimeBaseoverflow,aRealTimeClockoverflow,SIM0orSIM1interrupt,anExternalPeripheralInterrupt,Timer2overflowinterruptorTimer3overflowinterrupt isgenerated.Whentheinterruptisenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithintheMulti-functioninterruptsoccurs,asubroutinecalltotheMulti-functioninterruptvectoratlocation24Hor28Hrespectivelywilltakeplace.Whentheinterruptisserviced,theMulti-Functionrequestflag,MF0ForMF1F,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.However, itmustbenotedthat therequestflagsfromtheoriginalsourceof theMulti-functioninterrupt,namelytheTime-Baseinterrupt,RealTimeClockinterrupt,SIMinterrupts,ExternalPeripheral interrupt,Timer2overflowinterruptorTimer3overflowinterruptwillnotbeautomaticallyresetandmustbemanuallyresetbytheapplicationprogram.

Real Time Clock InterruptTheRealTimeClockInterruptiscontainedwithintheMulti-function0Interrupt.

ForaRealTimeClockinterrupt tobegenerated, theglobal interruptenablebit,EMI,RealTimeClockinterruptenablebit,ERTI,andMulti-function0interruptenablebit,EMF0I,mustfirstbeset.AnactualRealTimeClockinterruptwilltakeplacewhentheRealTimeClockrequestflag,RTF,isset,asituationthatwilloccurwhentheRealTimeClockoverflows.Whentheinterruptisenabled,thestackisnotfullandtheRealTimeClockoverflows,asubroutinecall totheMulti-function0interruptvectoratlocation24H,will takeplace.WhentheRealTimeClockinterruptisserviced,theEMIbitwillbeclearedtodisableotherinterrupts,howeveronlytheMF0Finterruptrequestflagwillbereset.AstheRTFflagwillnotbeautomaticallyreset,ithastobeclearedbytheapplicationprogram.

SimilarinoperationtotheTimeBaseinterrupt,thepurposeoftheRTCinterruptisalsotoprovidean interrupt signalat fixed timeperiods.TheRTC interruptclocksourceoriginates from theinternalclocksource fS.This fS inputclockfirstpasses throughadivider, thedivisionratioofwhichisselectedbyprogrammingtheappropriatebitsintheRTCCregistertoobtainlongerRTCinterruptperiodswhosevaluerangesfrom28/fS~215/fS.TheclocksourcethatgeneratesfS,whichinturncontrolstheRTCinterruptperiod,canoriginatefromthreedifferentsources, the32.768kHzoscillator(LXT), the internal32kHzRCoscillator(LIRC)or theSystemoscillatordividedby4(fSYS/4),thechoiceofwhichisdeterminebythefSclocksourceconfigurationoption.

Rev. 1.10 90 ne 0 01 Rev. 1.10 91 ne 0 01



RTC Interrupt

Note that theRTCinterruptperiod iscontrolledbybothconfigurationoptionsandan internalregisterRTCC.Aconfigurationoptionselects thesourceclockfor the internalclockfS,andtheRTCCregisterbitsRT2,RT1andRT0selectthedivisionratio.Notethattheactualdivisionratiocanbeprogrammedfrom28to215.

RTCC Register

Bit 7 6 5 4 3 2 1 0Name — — LVDO QOSC LVDC RT RT1 RT0R/W — — R R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas″0″Bit5 LVDO:LowVoltageDetectorOutput

0:Normalvoltage1:Lowvoltagedetected

Bit4 QOSC:RTCOscillatorQuick-startenablecontrol0:Enable1:Disable

Bit3 LVDC:LowVoltageDetectorenablecontrol0:Disable1:Enable

Bit2~0 RT2~RT0:RTCInterruptPeriodselection000:28/fS

001:29/fS

010:210/fS

011:211/fS

100:212/fS

101:213/fS

110:214/fS

111:215/fS

Rev. 1.10 90 ne 0 01 Rev. 1.10 91 ne 0 01



Time Base InterruptTheTimeBaseInterruptiscontainedwithintheMulti-function0Interrupt.

ForaTimeBaseInterrupttobegenerated,theglobalinterruptenablebit,EMI,TimeBaseInterruptenablebit,ETBI,andMulti-function0interruptenablebit,EMF0I,mustfirstbeset.AnactualTimeBaseInterruptwilltakeplacewhentheTimeBaseInterruptrequestflag,TBF,isset,asituationthatwilloccurwhentheTimeBaseoverflows.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecalltotheMulti-function0interruptvectoratlocation24H,willtakeplace.WhentheTimeBaseInterruptisserviced,theEMIbitwillbeclearedtodisableotherinterrupts,howeveronlytheMF0Finterruptrequestflagwillbereset.AstheTBFflagwillnotbeautomaticallyreset,ithastobeclearedbytheapplicationprogram.

ThepurposeoftheTimeBasefunctionistoprovideaninterruptsignalatfixedtimeperiods.TheTimeBaseinterruptclocksourceoriginatesfromtheTimeBaseinterruptclocksourceoriginatesfromtheinternalclocksourcefS.ThisfSinputclockfirstpassesthroughadivider,thedivisionratioofwhichisselectedbyconfigurationoptionstoprovidelongerTimeBaseinterruptperiods.TheTimeBaseinterrupt time-outperiodrangesfrom212/fS~215/fS.TheclocksourcethatgeneratesfS,whichinturncontrolstheTimeBaseinterruptperiod,canoriginatefromthreedifferentsources,the32.768kHzoscillator(LXT),theinternal32kHzRCoscillator(LIRC)ortheSystemoscillatordividedby4(fSYS/4),thechoiceofwhichisdeterminebythefSclocksourceconfigurationoption.

Essentiallyoperatingasaprogrammabletimer,whentheTimeBaseoverflowsitwillsetaTimeBaseinterruptflagwhichwillinturngenerateanInterruptrequestviatheMulti-function0Interruptvector.

Time Base Interrupt

Rev. 1.10 9 ne 0 01 Rev. 1.10 93 ne 0 01



Programming ConsiderationsBydisablingtheinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,onceaninterruptrequestflagisset,itwillremaininthisconditionintheINTC0,INTC1,INTC2,MFIC0andMFIC1registersuntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptserviceroutineisexecuted,asonlytheMulti-functioninterruptrequestflags,willbeautomaticallycleared,theindividualrequestflagforthefunctionneedstobeclearedbytheapplicationprogram.

It isrecommendedthatprogramsdonotusethe″CALL″instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode, thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenteringtheSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.Toreturn froman interrupt subroutine,eithera″RET″or″RETI″ instructionmaybeexecuted.The″RETI″ instruction inaddition toexecutinga return to themainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.The″RET″instructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbit in itspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.

Rev. 1.10 9 ne 0 01 Rev. 1.10 93 ne 0 01



Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

Inaddition to thepower-onreset,situationsmayarisewhere it isnecessary toforcefullyapplyaresetconditionwhenthemicrocontroller isrunning.Oneexampleof this iswhereafterpowerhasbeenappliedandthemicrocontrollerisalreadyrunning,theRESlineisforcefullypulledlow.Insuchacase,knownasanormaloperationreset,someof themicrocontrollerregistersremainunchangedallowing themicrocontroller toproceedwithnormaloperationafter thereset line isallowedtoreturnhigh.AnothertypeofresetiswhentheWatchdogTimeroverflowsandresetsthemicrocontroller.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.

AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullreset,similartotheRESresetisimplementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.

Reset FunctionsThereare fiveways inwhichamicrocontroller resetcanoccur, througheventsoccurringbothinternallyandexternally:

• Power-onResetThemostfundamentalandunavoidableresetistheonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensuresthatcertainotherregistersarepresettoknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.AlthoughthemicrocontrollerhasaninternalRCresetfunction, if theVDDpowersupplyrisetime isnot fastenoughordoesnotstabilisequicklyatpower-on, the internal reset functionmaybeincapableofprovidingproperresetoperation.ForthisreasonitisrecommendedthatanexternalRCnetworkisconnectedtotheRESpin,whoseadditionaltimedelaywillensurethattheRESpinremainslowforanextendedperiodtoallowthepowersupplytostabilise.Duringthistimedelay,normaloperationofthemicrocontrollerwillbeinhibited.AftertheRESlinereachesacertainvoltagevalue,theresetdelaytimetRSTDisinvokedtoprovideanextradelaytimeafterwhich themicrocontrollerwillbeginnormaloperation.TheabbreviationSSTin thefiguresstandsforSystemStart-upTimer.Formostapplicationsa resistorconnectedbetweenVDDand theRESpinandacapacitorconnectedbetweenVSSand theRESpinwillprovideasuitableexternal resetcircuit.AnywiringconnectedtotheRESpinshouldbekeptasshortaspossibletominimiseanystraynoiseinterference.ForapplicationsthatoperatewithinanenvironmentwheremorenoiseispresenttheEnhancedResetCircuitshownisrecommended.

Rev. 1.10 9 ne 0 01 Rev. 1.10 95 ne 0 01



Power-On Reset Timing ChartMoreinformationregardingexternalresetcircuitsislocatedinApplicationNoteHA0075EontheHoltekwebsite.

Note:"*"ItisrecommendedthatthiscomponentisaddedforaddedESDprotection"**"Itisrecommendedthatthiscomponentisaddedinenvironmentswherepowerlinenoiseissignificant

External RES Circuit

• RESPinResetThis typeof resetoccurswhen themicrocontroller is already runningand theRESpin isforcefullypulledlowbyexternalhardwaresuchasanexternalswitch.Inthiscaseasinthecaseofotherreset,theProgramCounterwillresettozeroandprogramexecutioninitiatedfromthispoint.

RES Reset Timing Chart

• LowVoltageReset−LVRThemicrocontrollercontainsalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedevice,whichisselectedviaaconfigurationoption.If thesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery,theLVRwillautomaticallyreset thedevice internally.TheLVRincludes thefollowingspecifications:ForavalidLVRsignal,alowvoltage,i.e.,avoltageintherangebetween0.9V~VLVRmustexistforgreaterthanthevaluetLVRspecifiedintheA.C.characteristics.Ifthelowvoltagestatedoesnotexceed1ms,theLVRwillignoreitandwillnotperformaresetfunction.OneofarangeofspecifiedvoltagevaluesforVLVRcanbeselectedusingconfigurationoptions.TheVLVRvaluewillbeselectedasapairinconjunctionwithaLowVoltageDetectvalue.

Low Voltage Reset Timing Chart

Rev. 1.10 9 ne 0 01 Rev. 1.10 95 ne 0 01



• WatchdogTime-outResetduringNormalOperationTheWatchdogtime-outResetduringnormaloperationisthesameasahardwareRESpinresetexceptthattheWatchdogtime-outflagTOwillbesetto″1″.

WDT Time-out Reset during Normal Operation Timing Chart

• WatchdogTime-outResetduringPowerDownTheWatchdogtime-outResetduringPowerDownisalittledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto″0″andtheTOflagwillbesetto″1″.RefertotheA.C.CharacteristicsfortSSTdetails.

WDT Time-out Reset during Power Down Timing Chart

Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchasthePowerDownfunctionorWatchdogTimer.Theresetflagsareshowninthetable:

TO PDF RESET Conditions0 0 RES reset dring power-on RES or LVR reset dring normal operation1 WDT time-ot reset dring normal operation1 1 WDT time-ot reset dring Power Down

Note: ″u″ stands for unchangedThefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition After RESETProgram Conter Reset to zeroInterrpts All interrpts will be disabledWDT Clear after reset WDT begins contingTimer/Event Conter Timer Conter will be trned offPrescaler The Timer Conter Prescaler will be clearedInpt/Otpt Ports I/O ports will be setp as inptsStack Pointer Stack Pointer will point to the top of the stack

Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrolleris inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachofthemicrocontrollerinternalregisters.

Rev. 1.10 96 ne 0 01 Rev. 1.10 97 ne 0 01



Register Reset(Power-On)

RES Reset(Normal Oper.)

WDT Time-out(Normal Oper.)

WDT Time-out(HALT)*

MP0 x x x x x x x x MP1 x x x x x x x x BP - - 0 - 0 0 0 0 - - 0 - 0 0 0 0 - - 0 - 0 0 0 0 - - - ACC x x x x x x x x PCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBLP x x x x x x x x TBLH x x x x x x x x TBHP - - x x x x x x - - - - - - RTCC - - 0 0 0 1 1 1 - - 0 0 0 1 1 1 - - 0 0 0 1 1 1 - - STATUS - - 0 0 x x x x - - - - 1 - - 1 1 MISC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MISC1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CLKMOD 0 0 0 0 0 111 0 0 0 0 0 111 0 0 0 0 0 111 DCDC - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - INTC0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - INTC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTC - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - - MFIC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFIC1 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - - PAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PBPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PBC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PCPU - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - PC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PCC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 USR 0 0 0 0 1 0 11 0 0 0 0 1 0 11 0 0 0 0 1 0 11 UCR1 0 0 0 0 0 0 x 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 x 0 UCR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRG x x x x x x x x x x x x x x x x x x x x x x x x TXR_RXR x x x x x x x x x x x x x x x x x x x x x x x x PWM0L 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 - - - PWM0H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM1L 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 - - - PWM1H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWML 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 - - - PWM2H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM3L 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 - - - PWM3H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR0 x x x x x x x x x x x x x x x x x x x x x x x x TMR0C 0 0 - 0 1 0 0 0 0 0 - 0 1 0 0 0 0 0 - 0 1 0 0 0 - TMR1H x x x x x x x x x x x x x x x x x x x x x x x x TMR1L x x x x x x x x x x x x x x x x x x x x x x x x TMR1C 0 0 0 0 1 - - - 0 0 0 0 1 - - - 0 0 0 0 1 - - - - - -

Rev. 1.10 96 ne 0 01 Rev. 1.10 97 ne 0 01



Register Reset(Power-On)

RES Reset(Normal Oper.)

WDT Time-out(Normal Oper.)

WDT Time-out(HALT)*

TMR x x x x x x x x x x x x x x x x x x x x x x x x TMRC 0 0 - 0 1 0 0 0 0 0 - 0 1 0 0 0 0 0 - 0 1 0 0 0 - TMR3 x x x x x x x x x x x x x x x x x x x x x x x x TMR3C 0 0 - 0 1 0 0 0 0 0 - 0 1 0 0 0 0 0 - 0 1 0 0 0 - RCFLT - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - ADRL x x x x - - - - x x x x - - - - x x x x - - - - - - - -ADRH x x x x x x x x x x x x x x x x x x x x x x x x ADCR 0 1 - - - 0 0 0 0 1 - - - 0 0 0 0 1 - - - 0 0 0 - - - ACSR 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 ADPCR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM0CTL0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - -SIM0CTL1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 SIM0DR x x x x x x x x x x x x x x x x x x x x x x x x SIM0AR/SIM0CTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM1CTL0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - -SIM1CTL1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 SIM1DR x x x x x x x x x x x x x x x x x x x x x x x x SIM1AR/SIM1CTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAL x x x x - - - - x x x x - - - - x x x x - - - - x x x x - - - -DAH x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x xDACTRL x x x - - - - 0 x x x - - - - 0 x x x - - - - 0 - - - - CCR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSR 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 CCCR 0 0 x x x 0 x 0 0 0 x x x 0 x 0 0 0 x x x 0 x 0 x x x x CETU1 0 - - - - 0 0 1 0 - - - - 0 0 1 0 - - - - 0 0 1 - - - - CETU0 0 111 0 1 0 0 0 111 0 1 0 0 0 111 0 1 0 0 CGT1 - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - CGT0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 CWT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CWT1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 CWT0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 CIER 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 - CIPR 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 - CTXB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRXB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Note:″u″standsforunchanged″x″standsforunknown″−″standsforunimplemented

Rev. 1.10 98 ne 0 01 Rev. 1.10 99 ne 0 01



OscillatorVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplicationrequirements.Six typesofsystemclockscanbeselectedwhilevariousclocksourceoptionsareprovided formaximumflexibility.Alloscillatoroptionsare selected through theconfigurationoptions.

System Clock ConfigurationsTherearemanywaysofgeneratingthesystemclock,threehighspeedoscillatorsandtwolowspeedoscillatorssuppliedclock.Anexternalclocksourcecanalsobeusedasthesystemclock.Thethreehighspeedoscillatorsaretheexternalcrystal/ceramicoscillator(HXT), theexternalRCnetwork(ERC)andthe internalhighspeedRCoscillator(HIRC).Thetwolowspeedoscillatorsare theexternal32.768kHzcrystaloscillator(LXT)andtheinternal32kHzRCoscillator(LIRC).SelectingwhetherthelowfrequencyorhighoscillatorisusedasthesystemoscillatorisimplementedusingtheHLCLKbitintheCLKMODregister.Thesourceclockforthehighspeedoscillatorischosenviaconfigurationoptionsaswellasthelowspeedoscillator.ThefrequencyoftheslowclockisalsodeterminedusingtheSLOWC0~SLOWC2bitsintheCLKMODregister.

External Crystal/ Ceramic Oscillator − HXTAfter selecting theexternal crystal configurationoption, the simpleconnectionof a crystalacrossOSC1andOSC2, isnormallyall that is required tocreate thenecessaryphaseshiftandfeedbackforoscillation,withoutrequiringexternalcapacitors.However, forsomecrystal typesand frequencies, toensureoscillation, itmaybenecessary toadd twosmallvaluecapacitors,C1andC2.Using a ceramic resonatorwill usually require two small value capacitors,C1andC2, tobeconnectedas shown foroscillation tooccur.ThevaluesofC1andC2shouldbe selected in consultationwith the crystal or resonatormanufacturer′s specification. Inmost applications, resistorRP1 is not required, however for those applicationswhere theLVRfunction isnotused,RP1maybenecessary toensure theoscillator stops runningwhenVDDfallsbelow itsoperating range.The internaloscillatorcircuitcontainsa filtercircuit toreduce thepossibilityof erraticoperationdue tonoiseon theoscillatorpins.Anadditionalconfigurationoptionmustbesetup toconfigure thedeviceaccording towhether theoscillatorfrequencyishigh,definedasequaltoorabove1MHz,orlow,whichisdefinedasbelow1MHz.MoreinformationregardingoscillatorapplicationsislocatedontheHoltekwebsite.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk,itisimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwithinterconnectinglinesarealllocatedasclosetotheMCUaspossible.

Crystal/Ceramic Oscillator

Rev. 1.10 98 ne 0 01 Rev. 1.10 99 ne 0 01



Crystal Oscillator C1 and C2 Values

Crystal Frequency C1 C220MHz — —12MHz — —8MHz — —4MHz — —1MHz — —

455kHz (see Note 2) 10pF 10pFNote: 1. C1 and C vales are for gidance only.

2. XTAL mode configuration option: 455kHz.3. RP1=5MΩ~10MΩ is recommended.

Crystal Recommended Capacitor Values

External RC Oscillator − ERCUsingtheERCoscillatoronlyrequiresthataresistor,withavaluebetween47kΩand1.5MΩ,isconnectedbetweenOSC1andVDD,anda470pFcapacitorisconnectedbetweenOSC1andground,providinga lowcostoscillatorconfiguration.It isonly theexternalresistor thatdetermines theoscillationfrequency;theexternalcapacitorhasnoinfluenceoverthefrequencyandisconnectedforstabilitypurposesonly.Devicetrimmingduringthemanufacturingprocessandtheinclusionof internal frequencycompensationcircuitsareused toensure that the influenceof thepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresistance/frequencyreferencepoint,itcanbenotedthatwithanexternal150kΩresistorconnectedandwitha5Vvoltagepowersupplyandtemperatureof25°Cdegrees, theoscillatorwillhaveafrequencyof4MHzwithinatoleranceof2%.HereonlytheOSC1pinisused,whichissharedwithI/OpinPA2,leavingpinPA3freeforuseasanormalI/Opin.

Notethataninternalcapacitortogetherwiththeexternalresistor,ROSC,arethecomponentswhichdeterminethefrequencyof theoscillator.Theexternalcapacitorshownonthediagramdoesnotinfluencethefrequencyofoscillation.Thisexternalcapacitorshouldbeaddedtoimproveoscillatorstabilityiftheopen-drainOSC2outputisutilisedintheapplicationcircuit.Theinternaloscillatorcircuitcontainsa filtercircuit toreduce thepossibilityoferraticoperationdue tonoiseon theoscillatorpins.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk,itisimportanttolocatethecapacitorandresistorasclosetotheMCUaspossible.

External RC Oscillator – ERC

Rev. 1.10 100 ne 0 01 Rev. 1.10 101 ne 0 01



Internal High Speed RC Oscillator − HIRCTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.TheinternalRCoscillatorhasthreefixedfrequenciesofeither4MHz,8MHzor12MHz.Devicetrimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyofeither3Vor5Vandatatemperatureof25°Cdegrees,thefixedoscillationfrequencyof4MHz,8MHzor12MHzwillhavea tolerancewithin2%.Note that if this internalsystemclockoption isselected,as itrequiresnoexternalpinsforitsoperation,I/OpinsPA2andPA3arefreeforuseasnormalI/Opins.

Internal Low Speed Oscillator − LIRCTheInternal32kHzSystemOscillatorisoneofthelowfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.ItisafullyintegratedRCoscillatorwithatypicalfrequencyof32kHzat5V,requiringnoexternalcomponentsforitsimplementation.Devicetrimmingduringthemanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethat theinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandata temperatureof25°Cdegrees, theoscillationfrequencyof32kHzwillhaveafrequencyrangefrom28.1kHzto34.4kHz.

Internal RC Oscillator – LIRC

External 32.768kHz Oscillator − LXTTheExternal32.768kHzCrystalSystemOscillatorisoneofthelowfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.Thisclocksourcehasafixedfrequencyof32.768kHzandrequiresa32.768kHzcrystaltobeconnectedbetweenpinsXT1andXT2.Theexternalresistorandcapacitorcomponentsconnectedtothe32.768kHzcrystalarenecessarytoprovideoscillation.Forapplicationswhereprecise frequenciesareessential, thesecomponentsmayberequired toprovidefrequencycompensationduetodifferentcrystalmanufacturingtolerances.Duringpower-upthereisatimedelayassociatedwiththeLXToscillatorwaitingforittostart-up.

WhenthemicrocontrollerenterstheSLEEPorIDLEMode,thesystemclockisswitchedofftostopmicrocontrolleractivityand toconservepower.However, inmanymicrocontrollerapplicationsitmaybenecessary tokeep the internal timersoperationalevenwhenthemicrocontroller is intheSLEEPorIDLEMode.Todothis,anotherclock, independentof thesystemclock,mustbeprovided.

However,forsomecrystals,toensureoscillationandaccuratefrequencygeneration,itisnecessarytoaddtwosmallvalueexternalcapacitors,C1andC2.TheexactvaluesofC1andC2shouldbeselected inconsultationwith thecrystalor resonatormanufacturers′ specification.Theexternalparallelfeedbackresistor,Rp,isrequired.

SomeconfigurationoptionsdetermineiftheXT1/XT2pinsareusedfortheLXToscillatororasI/Opins.

• IftheLXToscillatorisnotusedforanyclocksource,theXT1/XT2pinscanbeusedasnormalI/Opins.

• IftheLXToscillatorisusedforanyclocksource,the32.768kHzcrystalshouldbeconnectedtotheXT1/XT2pins.

Rev. 1.10 100 ne 0 01 Rev. 1.10 101 ne 0 01



Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk,itisimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwithinterconnectinglinesarealllocatedasclosetotheMCUaspossible.

LXT Oscillator C1 and C2 Values

Crystal Frequency C3 C432768Hz 8pF 10pF

Note: 1. C3 and C vales are for gidance only.2. RP2=5M~10MΩ is recommended.

32.768kHz Crystal Recommended Capacitor Values

Crystal/Ceramic Oscillator

LXT Oscillator Low Power FunctionTheLXToscillatorcanfunctioninoneoftwomodes,theQuickStartModeandtheLowPowerMode.ThemodeselectionisexecutedusingtheQOSCbitintheRTCCregister.

QOSC Bit LXT Mode0 Qick Start1 Low-power

Afterpoweron,theQOSCbitwillbeautomaticallyclearedtozeroensuringthattheLXToscillatorisintheQuickStartoperatingmode.IntheQuickStartModetheLXToscillatorwillpowerupandstabilisequickly.However,aftertheLXToscillatorhasfullypoweredupitcanbeplacedintotheLow-powermodebysettingtheQOSCbithigh.Theoscillatorwillcontinuetorunbutwithreducedcurrentconsumption,asthehighercurrentconsumptionisonlyrequiredduringtheLXToscillatorstart-up.Inpowersensitiveapplications,suchasbatteryapplications,wherepowerconsumptionmustbekepttoaminimum,itisthereforerecommendedthattheapplicationprogramsetstheQOSCbithighabout2secondsafterpower-on.

Itshouldbenotedthat,nomatterwhatconditiontheQOSCbit isset to, theLXToscillatorwillalwaysfunctionnormally,theonlydifferenceisthatitwilltakemoretimetostartupifintheLow-powermode.

External Oscillator − ECThesystemclockcanalsobesuppliedbyanexternallysuppliedclockgivingusersamethodofsynchronizing theirexternalhardware to themicrocontrolleroperation.This isselectedusingaconfigurationoptionandsupplyingtheclockonpinOSC1.PinOSC2canbeusedasanormalI/Opiniftheexternaloscillatorisused.Theinternaloscillatorcircuitcontainsafiltercircuittoreducethepossibilityoferraticoperationduetonoiseontheoscillatorpin.However,asthefiltercircuitconsumesacertainamountofpower,anoscillatorconfigurationoptionexiststoturnthisfilteroff.Notusing the internal filtershouldbeconsidered inpowersensitiveapplicationsandwhere theexternallysuppliedclockisofahighintegrityandsuppliedbyalowimpedancesource.

Supplementary OscillatorsThelowspeedoscillators,inadditiontoprovidingasystemclocksourcearealsousedtoprovideaclocksourcetotwootherdevicefunctions.ThesearetheWatchdogTimerandtheTimeBaseInterrupts.

Rev. 1.10 10 ne 0 01 Rev. 1.10 103 ne 0 01



System Operating ModesThedevicehas theability tooperate inseveraldifferentmodes.Thisrangeofoperatingmodes,knownasNormalMode,SlowMode,IdleModeandSleepMode,allowthedevicetorunusingawide rangeofdifferent slowand fastclocksources.Thedevicesalsopossess theability todynamicallyswitchbetweendifferentclocksandoperatingmodes.Withthischoiceofoperatingfunctionsusersareprovidedwiththeflexibilitytoensuretheyobtainoptimalperformancefromthedeviceaccordingtotheirapplicationspecificrequirements.

Clock SourcesIndiscussingthesystemclocksforthedevice,theycanbeseenashavingadualclockmode.ThesedualclocksarewhatareknownasaHighOscillatorandtheotherasaLowOscillator.TheHighandLowOscillatorarethesystemclocksourcesandcanbeselecteddynamicallyusingtheHLCLKbitintheCLKMODregister.TheHighOscillatorhastheinternalnamefMwhosesourceisselectedusingaconfigurationoptionfromachoiceofeitheranexternalcrystal/resonator,externalRCoscillatororexternalclocksource.

CLKMOD Register

Bit 7 6 5 4 3 2 1 0Name SLOWC SLOWC1 SLOWC0 SIMIDLE LTO HTO IDLEN HLCLKR/W R/W R/W R/W R/W R R R/W R/WPOR 0 0 0 0 0 1 1 1

Bit7~5 SLOWC2~SLOWC0:LowspeedclockfrequencyfSLOWselection000:fSL001:fSL010:fM/64011:fM/32100:fM/16101:fM/8110:fM/4111:fM/2

Bit4 SIMIDLE:SIMn(SPI/I2C)ContinuesRunninginIDLEmodecontrol0:Disable1:Enable

Bit3 LTO:LowspeedOscillatorreadyflag0:Notready1:Ready

Bit2 HTO:HighspeedOscillatorreadyflag0:Notready1:Ready

Thisisthehighspeedsystemoscillatorreadyflagwhichindicateswhenthehighspeedsystemoscillatorisstable.Thisflagisclearedto“0”byhardwarewhenthedeviceispoweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.Thereforethisflagwillalwaysbereadas“1”bytheapplicationprogramafterdevicepower-on.

Bit1 IDLEN:Idlemodecontrol0:Disable(SLEEPmode)1:Enable(IDLEmode)

Bit0 HLCLK:SystemclockfrequencyfSYSselection0:fM

1:fSLOW

Rev. 1.10 10 ne 0 01 Rev. 1.10 103 ne 0 01



TheLowOscillatorclocksourcehas the internalname fSL,whosesource isalso selectedbyconfigurationoptionfromachoiceofeitheranexternal32.768kHzoscillator(LXT)ortheinternal32kHzRCoscillator (LIRC).This internal fSL, fMclock, is furthermodifiedby theSLOWC0~SLOWC2bitsintheCLKMODregistertoprovidethelowfrequencyclocksourcefSLOW.

Anadditionalsubinternalclock,withtheinternalnamefSUB,isa32kHzclocksourcewhichcanbesourcedfromeither theinternal32K_INToscillatororanexternal32768Hzcrystal,selectedbyconfigurationoption.TogetherwithfSYS/4,itisusedasaclocksourceforcertaininternalfunctionssuchastheLCDdriver,WatchdogTimer,Buzzer,RTCInterruptandTimeBaseInterrupt.TheLCDclocksourceisthefSUBclocksourcedividedby8,givingafrequencyof4kHz.TheinternalclockfS,issimplyachoiceofeitherfSUBorfSYS/4,usingaconfigurationoption.

Dual Clock Mode Operation

Rev. 1.10 10 ne 0 01 Rev. 1.10 105 ne 0 01



Dual Clock Mode Structure

Rev. 1.10 10 ne 0 01 Rev. 1.10 105 ne 0 01



Operating ModesAfter thecorrectclocksourceconfigurationselectionsaremade,overalloperationof thechosenclockisachievedusingtheCLKMODregister.AcombinationoftheHLCLKandIDLENbitsintheCLKMODregisteranduseoftheHALTinstructiondetermineinwhichmodethedevicewillberun.ThedevicescanoperateinthefollowingModes.

Normal modefMon,fSLOWon,fSYS=fM,CPUon,fSon,fWDTon/offdependingupontheWDTconfigurationoptionandWDTcontrolregister.

Slow Mode0fMoff, fSYS=fSLOW, fSLOW=fSL=fLIRCor fLXT,CPUon, fSon, fWDTon/offdependingupon theWDTconfigurationoptionandWDTcontrolregister.

Slow Mode1fMon,fSYS=fSLOW=fM/2~fM/64,CPUon,fSon,fWDTon/offdependingupontheWDTconfigurationoptionandWDTcontrolregister.

IDLE modefM,fSLOW,fSYSoff,CPUoff;fSUBon,fSon/offbyselectingfSUBorfSYS/4,fWDTon/offdependingupontheWDTconfigurationoptionandWDTcontrolregister.

TheIDLEmodeisdeterminedby theIDLEModeControlbitnamedIDLENin theCLKMODregisterwhentheHALTinstructionisexecuted.If thisbit ishigh,whenaHALTinstructionisexecutedthedevicewillenter theIDLEMode.If thebit is lowthedevicewillenter theSLEEPModewhenaHALTinstructionisexecuted.

SLEEP modefM,fSLOW,fSYS,fS,CPUoff;fSUB,fWDTon/offdependingupontheWDTconfigurationoptionandWDTcontrolregister.

TheSLEEPmodeisdeterminedbysettingtheIDLEModeControlbitnamedIDLENto0whentheHALTinstructionisexecuted.

Operation ModeDescription

CPU fSYS fSUB fS

Normal Mode On fM On OnSlow 0 Mode On fSLOW=fLIRC or fLXT On OnSlow 1 Mode On fSLOW=fM/2~fM/6 On OnIDLE Mode Off On/Off (1) On On/Off (3)

SLEEP Mode Off Off On/Off (2) On/Off (3)

Note:1.IntheIDLEMode,thefSYSclockon/offfunctionisdeterminedbywhethertheSIMIDLEbitsetto1or0respectivelyandcanonlybeusedforthemasterSPIoperationorPCLKoutputforwhichtheclocksourcecomesfromthefSYSclock.

2.IntheSLEEPmodethefSUBclockon/offfunctionisdeterminedbywhethertheWDTisenabledordisabledrespectively.

3.ThefSclockon/offfunctionintheIDLEorSLEEPmodeisdeterminedbywhether theselectedclocksourceoftheWDTfunctionisfSUBorthefSYS/4clock.

Rev. 1.10 106 ne 0 01 Rev. 1.10 107 ne 0 01



Power Down Mode and Wake-up

Power Down ModeAlloftheHoltekmicrocontrollerhavetheabilitytoenteraPowerDownMode.Whenthedeviceentersthismode,thenormaloperatingcurrent,willbereducedtoanextremelylowstandbycurrentlevel.Thisoccursbecausewhenthedeviceenters thePowerDownMode, thesystemoscillatorisstoppedwhichreducesthepowerconsumptiontoextremelylowlevels,however,asthedevicemaintainsitspresentinternalcondition,itcanbewokenupatalaterstageandcontinuerunning,withoutrequiringafull reset.Thisfeature isextremelyimportant inapplicationareaswhere theMCUmusthaveitspowersupplyconstantlymaintainedtokeepthedeviceinaknownconditionbutwherethepowersupplycapacityislimitedsuchasinbatteryapplications.

Entering the Power Down ModeThere isonlyonewayfor thedevice toenter thePowerDownModeandthat is toexecute the″HALT″instructionintheapplicationprogram.Whenthisinstructionisexecuted,thefollowingwilloccur:

• Thesystemoscillatorwillstoprunningandtheapplicationprogramwillstopat the″HALT″instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandresumecountingiftheWDTclocksourceisselectedtocomefromtheWDToscillator.TheWDTwillstopifitsclocksourceoriginatesfromthesystemclock.

• TheI/Oportswillmaintaintheirpresentcondition.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

Standby Current ConsiderationsAsthemainreasonforenteringthePowerDownModeistokeepthecurrentconsumptionoftheMCUtoas lowavalueaspossible,perhapsonly in theorderofseveralmicro-amps, thereareotherconsiderationswhichmustalsobe takenintoaccountby thecircuitdesigner if thepowerconsumptionistobeminimized.SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeundonbedpins,whichmusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrentisdrawnorconnectedonlytoexternalcircuitsthatdonotdrawcurrent,suchasotherCMOSinputs.AlsonotethatadditionalstandbycurrentwillalsoberequirediftheconfigurationoptionshaveenabledtheWatchdogTimerinternaloscillator.

Rev. 1.10 106 ne 0 01 Rev. 1.10 107 ne 0 01



Wake-upAfterthesystementersthePowerDownMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• Anexternalreset

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

If thesystemiswokenupbyanexternal reset, thedevicewillexperiencea full systemreset,however,ifthedeviceiswokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiated.Althoughbothof thesewake-upmethodswill initiatearesetoperation, theactualsourceof thewake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflag isclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe″HALT″instruction.TheTOflagissetifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.

EachpinonPortAcanbesetupviaanindividualconfigurationoptiontopermitanegativetransitiononthepin towake-upthesystem.WhenaPortApinwake-upoccurs, theprogramwill resumeexecutionattheinstructionfollowingthe″HALT″instruction.

Ifthesystemiswokenupbyaninterrupt,thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterrupt isdisabledor theinterrupt isenabledbut thestackisfull, inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe″HALT″instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelated interrupt isfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflagisset to″1″beforeenteringthePowerDownMode,thewake-upfunctionoftherelatedinterruptwillbedisabled.

Nomatterwhatthesourceofthewake-upeventis,onceawake-upsituationoccurs,atimeperiodequal to1024systemclockperiodswillbe requiredbeforenormalsystemoperation resumes.However,ifthewake-uphasoriginatedduetoaninterrupt,theactualinterruptsubroutineexecutionwillbedelayedbyanadditionaloneormorecycles.Ifthewake-upresultsintheexecutionofthenextinstructionfollowingthe″HALT″instruction,thiswillbeexecutedimmediatelyafterthe1024systemclockperioddelayhasended.

Rev. 1.10 108 ne 0 01 Rev. 1.10 109 ne 0 01



Low Voltage Detector − LVDTheLowVoltageDetectinternalfunctionprovidesameansfortheusertomonitorwhenthepowersupplyvoltagefallsbelowacertainfixedlevelasspecifiedintheDCcharacteristics.

LVD OperationTheLVDfunctionmustbefirstenabledviaaconfigurationoptionafterwhichbits3and5oftheRTCCregisterareusedtocontroltheoverallfunctionoftheLVD.Bit3istheenable/disablecontrolbitandisknownasLVDC,whensetlowtheoverallfunctionoftheLVDwillbedisabled.Bit5istheLVDdetectoroutputbitandisknownasLVDO.Undernormaloperation,andwhenthepowersupplyvoltageisabovethespecifiedVLVDvalueintheDCcharacteristicsection,theLVDObitwillremainatazerovalue.IfthepowersupplyvoltageshouldfallbelowthisVLVDvaluethentheLVDObitwillchangetoahighvalueindicatingalowvoltagecondition.NotethattheLVDObitisaread-onlybit.BypollingtheLVDObitintheRTCCregister,theapplicationprogramcanthereforedeterminethepresenceofalowvoltagecondition.

Afterpower-on,orafterareset,theLVDwillbeswitchedoffbyclearingtheLVDCbitintheRTCCregistertozero.NotethatiftheLVDisenabledtherewillbesomepowerconsumptionassociatedwithitsinternalcircuitry,however,byclearingtheLVDCbittozerothepowercanbeminimised.ItisimportantnottoconfusetheLVDwiththeLVRfunction.IntheLVRfunctionanautomaticresetwillbegeneratedbythe,whereasintheLVDfunctiononlytheLVDObitwillbeaffectedwithnoinfluenceonotherfunctions.

Therearearangeofvoltagevalues,selectedusingaconfigurationoption,whichcanbechosentoactivatetheLVD.

Rev. 1.10 108 ne 0 01 Rev. 1.10 109 ne 0 01



Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.ItoperatesbyprovidingadeviceresetwhentheWatchdogTimercounteroverflows.

Watchdog Timer OperationTheWatchdogTimerclocksourceisprovidedbytheinternalclock,fS,whichisinturnsuppliedbyoneoftwosourcesselectedbyconfigurationoption:fSUBorfSYS/4.NotethatiftheWatchdogTimerconfigurationoptionhasbeendisabled,thenanyinstructionrelatingtoitsoperationwillresultinnooperation.

Mostof theWatchdogTimeroptions,suchasenable/disable,WatchdogTimerclocksourceandclearinstructiontypeareselectedusingconfigurationoptions.InadditiontoaconfigurationoptiontoenabletheWatchdogTimer,therearefourbits,WDTEN3~WDTEN0,intheMISC1registertoofferanadditionalenablecontroloftheWatchdogTimer.Thesebitsmustbesettoaspecificvalueof1010todisable theWatchdogTimer.Anyothervaluesfor thesebitswillkeeptheWatchdogTimerenabled.Afterpoweronthesebitswillhavethedisabledvalueof1010.

OneoftheWDTclocksourcesis theinternalfSUB,whichcanbesourcedfromeithertheinternal32kHzRCoscillator(LIRC)ortheexternal32.768kHzoscillator(LXT).TheLIRCoscillatorhasanapproximateperiodof31.2msatasupplyvoltageof5V.However, itshouldbenotedthatthisspecified internalclockperiodcanvarywithVDD, temperatureandprocessvariations.TheLXToscillatorissuppliedbyanexternal32768Hzcrystal.TheotherWatchdogTimerclocksourceoptionisthefSYS/4clock.WhethertheWatchdogTimerclocksourceisit′stheLIRC,theLXToscillatororfSYS/4,itisdividedby213~216,usingconfigurationoptiontoobtaintherequiredWatchdogTimertime-outperiod.Themaxtimeoutperiodiswhenthe216optionisselected.Thistime-outperiodmayvarywithtemperature,VDDandprocessvariations.Astheclearinstructiononlyresetsthelaststageof thedividerchain,for thisreasontheactualdivisionratioandcorrespondingWatchdogTimertime-outcanvarybyafactoroftwo.TheexactdivisionratiodependsupontheresidualvalueintheWatchdogTimercounterbeforetheclearinstructionisexecuted.

Watchdog Timer

Rev. 1.10 110 ne 0 01 Rev. 1.10 111 ne 0 01



MISC1 Register

Bit 7 6 5 4 3 2 1 0Name ODE3 ODE ODE1 ODE0 WDTEN3 WDTEN WDTEN1 WDTEN0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 1 0 1 0

Bit7~4 ODE3~ODE0:PA3~PA0OpenDraincontrolDescribedinInput/OutputPortsection

Bit3~0 WDTEN3, WDTEN2, WDTEN1, WDTEN0:WDTfunctionenable1010:WDTdisabledOthervalues:WDTenabledRecommendedvalueis″0101″

If the″watchdogtimerenable″configurationoptionisselected, thenthewatchdogtimerwillalwaysbeenabledandtheWDTEN3~WDTEN0controlbitswillhavenoeffect.TheWDTisonlydisabledwhenboththeWDTconfigurationoptionisdisabledandwhenbitsWDTEN3~WDTEN0=1010.TheWDTisenabledwheneithertheWDTconfigurationoptionisenabledorwhenbitsWDTEN3~WDTEN0≠1010

If thefSYS/4clockisusedas theWatchdogTimerclocksource, itshouldbenotedthatwhenthesystementersthePowerDownMode,thentheinstructionclockisstoppedandtheWatchdogTimerwill loseitsprotectingpurposes.Forsystemsthatoperateinnoisyenvironments,usingtheLIRCoscillatorisstronglyrecommended.

Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However, if thesystemis in thePowerDownMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.Thefirstisanexternalhardwarereset,whichmeansalowlevelontheRESpin,thesecondisusingthewatchdogsoftwareinstructionsandthethirdisviaa″HALT″instruction.

Clearing the Watchdog TimerTherearetwomethodsofusingsoftwareinstructionstocleartheWatchdogTimer,oneofwhichmustbechosenbyconfigurationoption.Thefirstoptionistousethesingle″CLRWDT″instructionwhile thesecond is touse the twocommands″CLRWDT1″and″CLRWDT2″.For the firstoption,asimpleexecutionof″CLRWDT″willcleartheWDTwhileforthesecondoption,both″CLRWDT1″and″CLRWDT2″mustbothbeexecutedtosuccessfullycleartheWatchdogTimer.Notethatforthissecondoption,if″CLRWDT1″isusedtocleartheWatchdogTimer,successiveexecutionsofthisinstructionwillhavenoeffect,onlytheexecutionofa″CLRWDT2″instructionwillcleartheWatchdogTimer.Similarlyafterthe″CLRWDT2″instructionhasbeenexecuted,onlyasuccessive″CLRWDT1″instructioncancleartheWatchdogTimer.

Rev. 1.10 110 ne 0 01 Rev. 1.10 111 ne 0 01



UART InterfaceThedevicecontainsanintegratedfull-duplexasynchronousserialcommunicationsUARTinterfacethatenablescommunicationwithexternaldevicesthatcontainaserialinterface.TheUARTfunctionhasmanyfeaturesandcantransmitandreceivedataseriallybytransferringaframeofdatawitheightorninedatabitsper transmissionaswellasbeingable todetecterrorswhen thedata isoverwrittenorincorrectlyframed.TheUARTfunctionpossessesitsowninternal interruptwhichcanbeusedtoindicatewhenareceptionoccursorwhenatransmissionterminates.

TheintegratedUARTfunctioncontainsthefollowingfeatures:

• Full-duplex,asynchronouscommunication

• 8or9bitscharacterlength

• Even,oddornoparityoptions

• Oneortwostopbits

• Baudrategeneratorwith8-bitprescaler

• Parity,framing,noiseandoverrunerrordetection

• Supportforinterruptonaddressdetect(lastcharacterbit=1)

• Separatelyenabledtransmitterandreceiver

• 2-byteDeepFIFOReceiveDataBuffer

• Transmitandreceiveinterrupts

• Interruptscanbeinitializedbythefollowingconditions:♦ TransmitterEmpty♦ TransmitterIdle♦ ReceiverFull♦ ReceiverOverrun♦ AddressModeDetect

UART Data Transfer Scheme

Rev. 1.10 11 ne 0 01 Rev. 1.10 113 ne 0 01



UART External InterfaceTocommunicatewithanexternalserialinterface,theinternalUARThastwoexternalpinsknownasTXandRX.TheTXpinistheUARTtransmitterpin,whichcanbeusedasageneralpurposeI/Oorotherpin-sharedfunctionalpin if thepin isnotconfiguredasaUARTtransmitter,whichoccurswhentheTXENbitintheUCR2controlregisterisequaltozero.Similarly,theRXpinistheUARTreceiverpin,whichcanalsobeusedasageneralpurposeI/Opin,ifthepinisnotconfiguredasareceiver,whichoccursiftheRXENbitintheUCR2registerisequaltozero.AlongwiththeUARTENbit,theTXENandRXENbits,ifset,willautomaticallysetuptheseI/Opinsorotherpin-sharedfunctionaltotheirrespectiveTXoutputandRXinputconditionsanddisableanypull-highresistoroptionwhichmayexistontheTXandRXpins.

UART Data Transfer SchemeTheblockdiagramshowstheoveralldatatransferstructurearrangementfortheUARTinterface.Theactualdata tobe transmittedfromtheMCUis first transferred to theTXRregisterby theapplicationprogram.ThedatawillthenbetransferredtotheTransmitShiftRegisterfromwhereitwillbeshiftedout,LSBfirst,ontotheTXpinataratecontrolledbytheBaudRateGenerator.OnlytheTXRregisterismappedontotheMCUDataMemory,theTransmitShiftRegisterisnotmappedandisthereforeinaccessibletotheapplicationprogram.

DatatobereceivedbytheUARTisacceptedontheexternalRXpin,fromwhereit isshiftedin,LSBfirst, to theReceiverShiftRegisterataratecontrolledbytheBaudRateGenerator.Whentheshiftregisterisfull,thedatawillthenbetransferredfromtheshiftregistertotheinternalRXRregister,whereit isbufferedandcanbemanipulatedbytheapplicationprogram.OnlytheRXRregisterismappedontotheMCUDataMemory,theReceiverShiftRegisterisnotmappedandisthereforeinaccessibletotheapplicationprogram.

Itshouldbenotedthattheactualregisterfordatatransmissionandreception,althoughreferredtointhetext,andinapplicationprograms,asseparateTXRandRXRregisters,onlyexistsasasinglesharedregisterintheDataMemory.ThissharedregisterknownastheTXR/RXRregisterisusedforbothdatatransmissionanddatareception.

UART Status and Control RegistersTherearefivecontrolregistersassociatedwiththeUARTfunction.TheUSR,UCR1andUCR2registerscontroltheoverallfunctionoftheUART,whiletheBRGregistercontrolstheBaudrate.TheactualdatatobetransmittedandreceivedontheserialinterfaceismanagedthroughtheTXR_RXRdataregisters.

TXR_RXR RegisterTheTXR_RXRregisteristhedataregisterwhichisusedtostorethedatatobetransmittedontheTXpinorbeingreceivedfromtheRXpin.

Bit 7 6 5 4 3 2 1 0Name TXRX7 TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x x x x x x x x

“x”: nknownBit7~0 TXRX7~TXRX0:UARTTransmit/ReceiveDatabits

Rev. 1.10 11 ne 0 01 Rev. 1.10 113 ne 0 01



USR RegisterTheUSR register is the status register for theUART,whichcanbe readby theprogram todeterminethepresentstatusoftheUART.AllflagswithintheUSRregisterarereadonlyandfurtherexplanationsaregivenbelow:

Bit 7 6 5 4 3 2 1 0Name PERR NF FERR OERR RIDLE RXIF TIDLE TXIFR/W R R R R R R R RPOR 0 0 0 0 1 0 1 1

Bit7 PERR:Parityerrorflag0:Noparityerrorisdetected1:Parityerrorisdetected

ThePERRflagistheparityerrorflag.Whenthisreadonlyflagis“0”,itindicatesaparityerrorhasnotbeendetected.Whentheflagis“1”,itindicatesthattheparityofthereceivedwordisincorrect.ThiserrorflagisapplicableonlyifParitymode(oddoreven)isselected.TheflagcanalsobeclearedbyasoftwaresequencewhichinvolvesareadtothestatusregisterUSRfollowedbyanaccesstotheRXRdataregister.

Bit6 NF:Noiseflag0:Nonoiseisdetected1:Noiseisdetected

TheNFflagis thenoiseflag.Whenthisreadonlyflagis“0”, it indicatesnonoisecondition.Whentheflagis“1”,itindicatesthattheUARThasdetectednoiseonthereceiverinput.TheNFflagissetduringthesamecycleastheRXIFflagbutwillnotbesetinthecaseofasoverrun.TheNFflagcanbeclearedbyasoftwaresequencewhichwillinvolveareadtothestatusregisterUSRfollowedbyanaccesstotheRXRdataregister.

Bit5 FERR:Framingerrorflag0:Noframingerrorisdetected1:Framingerrorisdetected

TheFERRflagistheframingerrorflag.Whenthisreadonlyflagis“0”,itindicatesthat thereisnoframingerror.Whentheflagis“1”, it indicates thataframingerrorhasbeendetectedforthecurrentcharacter.TheflagcanalsobeclearedbyasoftwaresequencewhichwillinvolveareadtothestatusregisterUSRfollowedbyanaccesstotheRXRdataregister.

Bit4 OERR:Overrunerrorflag0:Nooverrunerrorisdetected1:Overrunerrorisdetected

TheOERRflagistheoverrunerrorflagwhichindicateswhenthereceiverbufferhasoverflowed.Whenthisreadonlyflagis“0”,itindicatesthatthereisnooverrunerror.Whentheflagis“1”,itindicatesthatanoverrunerroroccurswhichwillinhibitfurthertransferstotheRXRreceivedataregister.Theflagisclearedbyasoftwaresequence,which isa read to thestatusregisterUSRfollowedbyanaccess to theRXRdataregister.

Bit3 RIDLE:Receiverstatus0:Datareceptionisinprogress(databeingreceived)1:Nodatareceptionisinprogress(receiverisidle)

TheRIDLEflagisthereceiverstatusflag.Whenthisreadonlyflagis“0”,itindicatesthatthereceiverisbetweentheinitialdetectionofthestartbitandthecompletionofthestopbit.Whentheflagis“1”, it indicates that thereceiver is idle.Betweenthecompletionofthestopbitandthedetectionofthenextstartbit,theRIDLEbitis“1”indicatingthattheUARTreceiverisidleandtheRXpinstaysinlogichighcondition.

Rev. 1.10 11 ne 0 01 Rev. 1.10 115 ne 0 01



Bit2 RXIF:ReceiveRXRdataregisterstatus0:RXRdataregisterisempty1:RXRdataregisterhasavailabledata

TheRXIFflagisthereceivedataregisterstatusflag.Whenthisreadonlyflagis“0”,itindicatesthattheRXRreaddataregisterisempty.Whentheflagis“1”,itindicatesthat theRXRreaddataregistercontainsnewdata.When thecontentsof theshiftregisteraretransferredtotheRXRregister,aninterruptisgeneratedifRIE=1intheUCR2register.Ifoneormoreerrorsaredetectedinthereceivedword,theappropriatereceive-relatedflagsNF,FERR,and/orPERRaresetwithinthesameclockcycle.TheRXIFflagisclearedwhentheUSRregisterisreadwithRXIFset,followedbyareadfromtheRXRregister,andiftheRXRregisterhasnodataavailable.

Bit1 TIDLE:Transmissionstatus0:Datatransmissionisinprogress(databeingtransmitted)1:Nodatatransmissionisinprogress(transmitterisidle)

TheTIDLEflag isknownas the transmissioncompleteflag.Whenthis readonlyflagis“0”,it indicatesthatatransmissionisinprogress.Thisflagwillbesetto“1”whentheTXIFflagis“1”andwhenthereisnotransmitdataorbreakcharacterbeingtransmitted.WhenTIDLEisequalto1, theTXpinbecomesidlewiththepinstateinlogichighcondition.TheTIDLEflagisclearedbyreadingtheUSRregisterwithTIDLEsetandthenwritingtotheTXRregister.Theflagisnotgeneratedwhenadatacharacterorabreakisqueuedandreadytobesent.

Bit0 TXIF:TransmitTXRdataregisterstatus0:Characterisnottransferredtothetransmitshiftregister1:Characterhastransferredtothetransmitshiftregister(TXRdataregisterisempty)

TheTXIFflagisthetransmitdataregisteremptyflag.Whenthisreadonlyflagis“0”,itindicatesthatthecharacterisnottransferredtothetransmittershiftregister.Whentheflagis“1”,it indicatesthatthetransmittershiftregisterhasreceivedacharacterfromtheTXRdataregister.TheTXIFflag isclearedbyreadingtheUARTstatusregister(USR)withTXIFsetandthenwriting to theTXRdataregister.Note thatwhentheTXENbit isset, theTXIFflagbitwillalsobesetsincethetransmitdataregisterisnotyetfull.

Rev. 1.10 11 ne 0 01 Rev. 1.10 115 ne 0 01



UCR1 RegisterTheUCR1registertogetherwiththeUCR2registerarethetwoUARTcontrolregistersthatareusedtosetthevariousoptionsfortheUARTfunctionsuchasoverallon/offcontrol,paritycontrol,datatransferbitlength,etc.Furtherexplanationoneachofthebitsisgivenbelow:

Bit 7 6 5 4 3 2 1 0Name UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8R/W R/W R/W R/W R/W R/W R/W R WPOR 0 0 0 0 0 0 x 0

“x”: nknownBit7 UARTEN:UARTfunctionenablecontrol

0:DisableUART.TXandRXpinsareI/Oorotherpin-sharedfunctions1:EnableUART.TXandRXpinsfunctionasUARTpins

TheUARTENbit is theUARTenablebit.Whenthisbit isequalto“0”,theUARTwillbedisabledand theRXpinaswellas theTXpinwillbesetas I/Oorotherpin-sharedfunctions.Whenthebit isequal to“1”, theUARTwillbeenabledandtheTXandRXpinswillfunctionasdefinedbytheTXENandRXENenablecontrolbits.WhentheUARTisdisabled,itwillemptythebuffersoanycharacterremaininginthebufferwillbediscarded.Inaddition,thevalueofthebaudratecounterwillbereset.IftheUARTisdisabled,allerrorandstatusflagswillbereset.AlsotheTXEN,RXEN,TXBRK,RXIF,OERR,FERR,PERRandNFbitswillbecleared,whiletheTIDLE,TXIFandRIDLEbitswillbeset.Othercontrolbits inUCR1,UCR2andBRGregisterswillremainunaffected.IftheUARTisactiveandtheUARTENbitiscleared,allpendingtransmissionsandreceptionswillbeterminatedandthemodulewillberesetasdefinedabove.WhentheUARTisre-enabled, itwill restart in thesameconfiguration.

Bit6 BNO:Numberofdatatransferbitsselection0:8-bitdatatransfer1:9-bitdatatransfer

Thisbit isusedtoselect thedata lengthformat,whichcanhaveachoiceofeither8-bitor9-bitformat.Whenthisbitisequalto“1”,a9-bitdatalengthformatwillbeselected.Ifthebitisequalto“0”,thenan8-bitdatalengthformatwillbeselected.If9-bitdatalengthformatisselected,thenbitsRX8andTX8willbeusedtostorethe9thbitofthereceivedandtransmitteddatarespectively.

Bit5 PREN:Parityfunctionenablecontrol0:Parityfunctionisdisabled1:Parityfunctionisenabled

Thisbitistheparityfunctionenablebit.Whenthisbitisequalto1,theparityfunctionwillbeenabled.Ifthebitisequalto0,thentheparityfunctionwillbedisabled.

Bit4 PRT:Paritytypeselectionbit0:Evenparityforparitygenerator1:Oddparityforparitygenerator

Thisbitistheparitytypeselectionbit.Whenthisbitisequalto1,oddparitytypewillbeselected.Ifthebitisequalto0,thenevenparitytypewillbeselected.

Bit3 STOPS:Numberofstopbitsselection0:Onestopbitformatisused1:Twostopbitsformatisused

Thisbitdeterminesifoneortwostopbitsaretobeused.Whenthisbitisequalto“1”,twostopbitsformatareused.Ifthebitisequalto“0”,thenonlyonestopbitformatisused.

Rev. 1.10 116 ne 0 01 Rev. 1.10 117 ne 0 01



Bit2 TXBRK:Transmitbreakcharacter0:Nobreakcharacteristransmitted1:Breakcharacterstransmit

TheTXBRKbit is theTransmitBreakCharacterbit.Whenthisbit isequal to“0”,therearenobreakcharactersandtheTXpinoperatsnormally.Whenthebitisequalto“1”,therearetransmitbreakcharactersandthetransmitterwillsendlogiczeros.Whenthisbit isequal to“1”,after thebuffereddatahasbeentransmitted, thetransmitteroutputisheldlowforaminimumofa13-bitlengthanduntiltheTXBRKbitisreset.

Bit1 RX8:Receivedatabit8for9-bitdatatransferformat(readonly)Thisbitisonlyusedif9-bitdatatransfersareused,inwhichcasethisbitlocationwillstorethe9thbitofthereceiveddataknownasRX8.TheBNObitisusedtodeterminewhetherdatatransfesarein8-bitor9-bitformat.

Bit0 TX8:Transmitdatabit8for9-bitdatatransferformat(writeonly)Thisbit isonlyusedif9-bitdata transfersareused, inwhichcasethisbit locationwillstorethe9thbitof thetransmitteddataknownasTX8.TheBNObit isusedtodeterminewhetherdatatransfesarein8-bitor9-bitformat.

UCR2 RegisterTheUCR2registeris thesecondoftheUARTcontrolregistersandservesseveralpurposes.Oneofitsmainfunctionsistocontrolthebasicenable/disableoperationif theUARTTransmitterandReceiveraswellasenablingthevariousUARTinterruptsources.Theregisteralsoservestocontrolthebaudratespeed, receiverwake-upfunctionenableand theaddressdetect functionenable.Furtherexplanationoneachofthebitsisgivenbelow:

Bit 7 6 5 4 3 2 1 0Name TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 TXEN:UARTTransmitterenablecontrol0:UARTTransmitterisdisabled1:UARTTransmitterisenabled

ThebitnamedTXENistheTransmitterEnableBit.Whenthisbitisequalto“0”,thetransmitterwillbedisabledwithanypendingdata transmissionsbeingaborted. Inadditionthebufferswillbereset.InthissituationtheTXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.IftheTXENbitisequalto“1”andtheUARTENbitisalsoequalto1,thetransmitterwillbeenabledandtheTXpinwillbecontrolledbytheUART.ClearingtheTXENbitduringatransmissionwillcausethedatatransmissiontobeabortedandwillresetthetransmitter.Ifthissituationoccurs,theTXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.

Bit6 RXEN:UARTReceiverenablecontrol0:UARTReceiverisdisabled1:UARTReceiverisenabled

ThebitnamedRXENistheReceiverEnableBit.Whenthisbit isequalto“0”,thereceiverwillbedisabledwithanypendingdatareceptionsbeingaborted.Inadditionthereceiverbufferswillbereset.InthissituationtheRXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.IftheRXENbitisequalto“1”andtheUARTENbitisalsoequalto1,thereceiverwillbeenabledandtheRXpinwillbecontrolledbytheUART.ClearingtheRXENbitduringareceptionwillcausethedatareceptiontobeabortedandwillresetthereceiver.Ifthissituationoccurs,theRXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.

Rev. 1.10 116 ne 0 01 Rev. 1.10 117 ne 0 01



Bit5 BRGH:BaudRatespeedselection0:Lowspeedbaudrate1:Highspeedbaudrate

ThebitnamedBRGHselectsthehighorlowspeedmodeoftheBaudRateGenerator.Thisbit, togetherwiththevalueplacedinthebaudrateregister,BRG,controls thebaudrateoftheUART.Ifthebitisequalto0,thelowspeedmodeisselected.

Bit4 ADDEN:Addressdetectfunctionenablecontrol0:Addressdetectionfunctionisdisabled1:Addressdetectionfunctionisenabled

ThebitnamedADDENistheaddressdetectionfunctionenablecontrolbit.Whenthisbit isequalto1,theaddressdetectionfunctionisenabled.Whenitoccurs,if the8thbit,whichcorrespondstoRX7ifBNO=0,orthe9thbit,whichcorrespondstoRX8ifBNO=1,hasavalueof“1”,thenthereceivedwordwillbeidentifiedasanaddress,ratherthandata.Ifthecorrespondinginterruptisenabled,aninterruptrequestwillbegeneratedeachtimethereceivedwordhastheaddressbitset,whichisthe8thor9thbitdependingonthevalueoftheBNObit.If theaddressbitknownasthe8thor9thbitofthereceivedwordis“0”withtheaddressdetectionfunctionbeingenabled,aninterruptwillnotbegeneratedandthereceiveddatawillbediscarded.

Bit3 WAKE:RXpinfallingedgewake-upfunctionenablecontrol0:RXpinwake-upfunctionisdisabled1:RXpinwake-upfunctionisenabled

Thebitenablesordisablesthereceiverwake-upfunction.Ifthisbitisequalto1andthedeviceisinIDLEorSLEEPmode,afallingedgeontheRXpinwillwakeupthedevice.Ifthisbitisequalto0andthedeviceisinIDLEorSLEEPmode,anyedgetransitionsontheRXpinwillnotwakeupthedevice.

Bit2 RIE:Receiverinterruptenablecontrol0:Receiverrelatedinterruptisdisabled1:Receiverrelatedinterruptisenabled

Thebitenablesordisablesthereceiverinterrupt.Ifthisbitisequalto1andwhenthereceiveroverrunflagOERRorreceiveddataavailableflagRXIFisset, theUARTinterruptrequestflagwillbeset.Ifthisbitisequalto0,theUARTinterruptrequestflagwillnotbeinfluencedbytheconditionoftheOERRorRXIFflags.

Bit1 TIIE:TransmitterIdleinterruptenablecontrol0:Transmitteridleinterruptisdisabled1:Transmitteridleinterruptisenabled

Thebitenablesordisablesthetransmitteridleinterrupt.If thisbit isequalto1andwhenthetransmitter idleflagTIDLEisset,duetoa transmitter idlecondition, theUARTinterruptrequestflagwillbeset.If thisbit isequalto0,theUARTinterruptrequestflagwillnotbeinfluencedbytheconditionoftheTIDLEflag.

Bit0 TEIE:TransmitterEmptyinterruptenablecontrol0:Transmitteremptyinterruptisdisabled1:Transmitteremptyinterruptisenabled

Thebitenablesordisablesthetransmitteremptyinterrupt.Ifthisbitisequalto1andwhenthetransmitteremptyflagTXIFisset,duetoatransmitteremptycondition,theUARTinterruptrequestflagwillbeset.If thisbit isequalto0,theUARTinterruptrequestflagwillnotbeinfluencedbytheconditionoftheTXIFflag.

Rev. 1.10 118 ne 0 01 Rev. 1.10 119 ne 0 01



Baud Rate GeneratorTosetupthespeedoftheserialdatacommunication,theUARTfunctioncontainsitsowndedicatedbaudrategenerator.Thebaudrate iscontrolledbyitsowninternalfreerunning8-bit timer, theperiodofwhichisdeterminedbytwofactors.Thefirstof these is thevalueplacedin theBRGregisterandthesecondisthevalueoftheBRGHbitwithintheUCR2controlregister.TheBRGHbitdecides,ifthebaudrategeneratoristobeusedinahighspeedmodeorlowspeedmode,whichinturndeterminestheformulathatisusedtocalculatethebaudrate.ThevalueintheBRGregister,N,whichisusedinthefollowingbaudratecalculationformuladeterminesthedivisionfactor.NotethatNisthedecimalvalueplacedintheBRGregisterandhasarangeofbetween0and255.

UCR2 BRGH Bit 0 1Baud Rate (BR) fSYS/[64(N+1)] fSYS/[16(N+1)]

ByprogrammingtheBRGHbitwhichallowsselectionoftherelatedformulaandprogrammingtherequiredvalueintheBRGregister,therequiredbaudratecanbesetup.Notethatbecausetheactualbaudrateisdeterminedusingadiscretevalue,N,placedintheBRGregister,therewillbeanerrorassociatedbetweentheactualandrequestedvalue.ThefollowingexampleshowshowtheBRGregistervalueNandtheerrorvaluecanbecalculated.

BRG Register

Bit 7 6 5 4 3 2 1 0Name BRG7 BRG6 BRG5 BRG BRG3 BRG BRG1 BRG0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x x x x x x x x

“x”: nknownBit7~0 BRG7~BRG0:BaudRatevalues

ByprogrammingtheBRGHbit intheUCR2registerwhichallowsselectionof therelatedformuladescribedaboveandprogramming therequiredvalue in theBRGregister,therequiredbaudratecanbesetup.

Rev. 1.10 118 ne 0 01 Rev. 1.10 119 ne 0 01



Calculating the Baud Rate and Error ValuesForaclockfrequencyof4MHz,andwithBRGHsetto0determinetheBRGregistervalueN,theactualbaudrateandtheerrorvalueforadesiredbaudrateof4800.

FromtheabovetablethedesiredbaudrateBR=fSYS

[64(N+1)]

Re-arrangingthisequationgivesN=fSYS

BR×64−1

GivingavalueforN=40000004800×64

−1=12.0208

Toobtaintheclosestvalue,adecimalvalueof12shouldbeplacedintotheBRGregister.ThisgivesanactualorcalculatedbaudratevalueofBR= 4000000

64(12+1)=4808

Thereforetheerrorisequalto4808−48004800 =0.16%Thefollowing tablesshowtheactualvaluesofbaudrateanderrorvaluesfor the twovalueofBRGH.

Baud RateK/bps

Baud Rates for BRGH=0

fSYS=4MHz fSYS=3.579545MHz fSYS=7.159MHz

BRG Kbaud Error(%) BRG Kbaud Error(%) BRG Kbaud Error(%)0.3 07 0.300 0.16 185 0.300 0.00 — — —1. 51 1.0 0.16 6 1.190 -0.83 9 1.03 0.3. 5 .0 0.16 .3 1.3 6 .380 -0.83.8 1 .808 0.16 11 .661 -.90 .863 1.39.6 6 8.99 -6.99 5 9.31 -.90 11 9.3 -.90

19. 0.833 8.51 18.63 -.90 5 18.63 -.9038. — — — — — — 3.86 -.9057.6 0 6.500 8.51 0 55.930 -.90 1 55.930 -.90115. — — — — — — 0 111.859 -.90

Baud Rates and Error Values for BRGH=0

Baud RateK/bps

Baud Rates for BRGH=1

fSYS=4MHz fSYS=3.579545MHz fSYS=7.159MHz

BRG Kbaud Error(%) BRG Kbaud Error(%) BRG Kbaud Error(%)0.3 — — — — — — — — —1. 07 1.0 0.16 185 1.03 0.3 — — —. 103 .0 0.16 9 .06 0.3 185 .06 0.3.8 51 .808 0.16 6 .76 -0.83 9 .811 0.39.6 5 9.615 0.16 9.77 1.3 6 9.50 -0.83

19. 1 19.31 0.16 11 18.63 -.90 19.5 1.338. 6 35.71 -6.99 5 37.86 -.90 11 37.86 -.9057.6 3 6.5 8.51 3 55.930 -.90 7 55.930 -.90115. 1 15 8.51 1 111.86 -.90 3 111.86 -.9050 0 50 0 — — — — — —

Baud Rates and Error Values for BRGH=1

Rev. 1.10 10 ne 0 01 Rev. 1.10 11 ne 0 01



UART Setup and ControlFordatatransfer,theUARTfunctionutilizesanon-return-to-zero,morecommonlyknownasNRZ,format.Thisiscomposedofonestartbit,eightorninedatabitsandoneor twostopbits.ParityissupportedbytheUARThardwareandcanbesetuptobeeven,oddornoparity.Forthemostcommondataformat,8databitsalongwithnoparityandonestopbit,denotedas8,N,1,isusedasthedefaultsetting,whichisthesettingatpower-on.Thenumberofdatabitsandstopbits,alongwiththeparity,aresetupbyprogrammingthecorrespondingBNO,PRT,PRENandSTOPSbitsintheUCR1register.Thebaudrateusedtotransmitandreceivedataissetupusingtheinternal8-bitbaudrategenerator,whilethedataistransmittedandreceivedLSBfirst.AlthoughthetransmitterandreceiveroftheUARTarefunctionallyindependent,theybothusethesamedataformatandbaudrate.Inallcasesstopbitswillbeusedfordatatransmission.

Enabling/Disabling the UART InterfaceThebasicon/offfunctionoftheinternalUARTfunctioniscontrolledusingtheUARTENbitintheUCR1register.IftheUARTEN,TXENandRXENbitsareset,thenthesetwoUARTpinswillactasnormalTXoutputpinandRXinputpinrespectively.IfnodataisbeingtransmittedontheTXpin,thenitwilldefaulttoalogichighvalue.

ClearingtheUARTENbitwilldisabletheTXandRXpinsandthesetwopinswillbeusedasanI/Oorotherpin-sharedfunctionalpin.WhentheUARTfunction isdisabled, thebufferwillberesettoanemptycondition,atthesametimediscardinganyremainingresidualdata.DisablingtheUARTwillalsoresettheenablecontrol,theerrorandstatusflagswithbitsTXEN,RXEN,TXBRK,RXIF,OERR,FERR,PERRandNFbeingclearedwhilebitsTIDLE,TXIFandRIDLEwillbeset.Theremainingcontrolbits in theUCR1,UCR2andBRGregisterswill remainunaffected.If theUARTENbit in theUCR1register isclearedwhile theUARTisactive, thenallpendingtransmissionsand receptionswillbe immediatelysuspendedand theUARTwillbe reset toaconditionasdefinedabove.IftheUARTisthensubsequentlyre-enabled,itwillrestartagaininthesameconfiguration.

Rev. 1.10 10 ne 0 01 Rev. 1.10 11 ne 0 01



Data, Parity and Stop Bit SelectionTheformatof thedata tobe transferred iscomposedofvariousfactorssuchasdatabit length,parityon/off,paritytype,addressbitsandthenumberofstopbits.ThesefactorsaredeterminedbythesetupofvariousbitswithintheUCR1register.TheBNObitcontrols thenumberofdatabitswhichcanbesettoeither8or9.ThePRTbitcontrolsthechoiceifoddorevenparity.ThePRENbitcontrolstheparityon/offfunction.TheSTOPSbitdecideswhetheroneortwostopbitsaretobeused.Thefollowingtableshowsvariousformatsfordatatransmission.Theaddressdetectmodecontrolbitidentifiestheframeasanaddresscharacter.Thenumberofstopbits,whichcanbeeitheroneortwo,isindependentofthedatalength.

Start Bit Data Bits Address Bits Parity Bits Stop BitExample of 8-bit Data Formats

1 8 0 0 11 7 0 1 11 7 1 0 1

Example of 9-bit Data Formats1 9 0 0 11 8 0 1 11 8 1 0 1

Transmitter Receiver Data Format

Thefollowingdiagramshows the transmitandreceivewaveformsforboth8-bitand9-bitdataformats.

8-Bit Data Format

9-Bit Data Format

UART TransmitterDatawordlengthsofeither8or9bitscanbeselectedbyprogrammingtheBNObitintheUCR1register.WhenBNObitisset, thewordlengthwillbesetto9bits.Inthiscasethe9thbit,whichistheMSB,needstobestoredintheTX8bitintheUCR1register.AtthetransmittercoreliestheTransmitterShiftRegister,morecommonlyknownas theTSR,whosedata isobtainedfromthetransmitdataregister,whichisknownas theTXRregister.Thedata tobe transmittedis loadedintothisTXRregisterbytheapplicationprogram.TheTSRregisterisnotwrittentowithnewdatauntilthestopbitfromtheprevioustransmissionhasbeensentout.Assoonasthisstopbithasbeentransmitted,theTSRcanthenbeloadedwithnewdatafromtheTXRregister, ifit isavailable.ItshouldbenotedthattheTSRregister,unlikemanyotherregisters, isnotdirectlymappedintotheDataMemoryareaandassuch isnotavailable to theapplicationprogramfordirect read/writeoperations.AnactualtransmissionofdatawillnormallybeenabledwhentheTXENbitisset,butthedatawillnotbetransmitteduntiltheTXRregisterhasbeenloadedwithdataandthebaudrategeneratorhasdefinedashiftclocksource.However,thetransmissioncanalsobeinitiatedbyfirstloadingdataintotheTXRregister,afterwhichtheTXENbitcanbeset.Whenatransmissionofdatabegins,theTSRisnormallyempty,inwhichcaseatransfertotheTXRregisterwillresultinanimmediatetransfertotheTSR.IfduringatransmissiontheTXENbitiscleared,thetransmissionwillimmediatelyceaseandthetransmitterwillbereset.TheTXoutputpinwillthenreturntotheI/Oorotherpin-sharedfunction.

Rev. 1.10 1 ne 0 01 Rev. 1.10 13 ne 0 01



Transmitting DataWhentheUARTistransmittingdata,thedataisshiftedontheTXpinfromtheshiftregister,withtheleastsignificantbitLSBfirst.Inthetransmitmode,theTXRregisterformsabufferbetweentheinternalbusandthetransmittershiftregister.Itshouldbenotedthatif9-bitdataformathasbeenselected,thentheMSBwillbetakenfromtheTX8bitintheUCR1register.Thestepstoinitiateadatatransfercanbesummarizedasfollows:

• MakethecorrectselectionoftheBNO,PRT,PRENandSTOPSbitstodefinetherequiredwordlength,paritytypeandnumberofstopbits.

• SetuptheBRGregistertoselectthedesiredbaudrate.

• Set theTXENbit toensurethat theUARTtransmitterisenabledandtheTXpinisusedasaUARTtransmitterpin.

• AccesstheUSRregisterandwritethedatathatistobetransmittedintotheTXRregister.NotethatthisstepwillcleartheTXIFbit.

Thissequenceofeventscannowberepeatedtosendadditionaldata.ItshouldbenotedthatwhenTXIF=0,datawillbeinhibitedfrombeingwrittentotheTXRregister.ClearingtheTXIFflagisalwaysachievedusingthefollowingsoftwaresequence:

• AUSRregisteraccess

• ATXRregisterwriteexecution

Theread-onlyTXIFflagissetbytheUARThardwareandifsetindicatesthattheTXRregisterisemptyandthatotherdatacannowbewrittenintotheTXRregisterwithoutoverwritingthepreviousdata.IftheTEIEbitisset,thentheTXIFflagwillgenerateaninterrupt.Duringadatatransmission,awrite instruction to theTXRregisterwillplace thedata into theTXRregister,whichwillbecopiedtotheshiftregisterattheendofthepresenttransmission.Whenthereisnodatatransmissioninprogress,awriteinstructiontotheTXRregisterwillplacethedatadirectlyintotheshiftregister,resultinginthecommencementofdatatransmission,andtheTXIFbitbeingimmediatelyset.Whenaframetransmissioniscomplete,whichhappensafterstopbitsaresentorafterthebreakframe,theTIDLEbitwillbeset.TocleartheTIDLEbitthefollowingsoftwaresequenceisused:


• ATXRregisterwriteexecution

NotethatboththeTXIFandTIDLEbitsareclearedbythesamesoftwaresequence.

Transmitting BreakIf theTXBRKbit isset, then thebreakcharacterswillbesenton thenext transmission.Breakcharacter transmissionconsistsofastartbit, followedby13xN“0”bits,whereN=1,2,etc. ifabreakcharacteristobetransmitted,thentheTXBRKbitmustbefirstsetbytheapplicationprogramandthenclearedtogeneratethestopbits.Transmittingabreakcharacterwillnotgenerateatransmitinterrupt.Notethatabreakconditionlengthisatleast13bitslong.IftheTXBRKbitiscontinuallykeptatalogichighlevel, thenthetransmittercircuitrywill transmitcontinuousbreakcharacters.AftertheapplicationprogramhasclearedtheTXBRKbit,thetransmitterwillfinishtransmittingthelastbreakcharacterandsubsequentlysendoutoneortwostopbits.Theautomaticlogichighattheendofthelastbreakcharacterwillensurethatthestartbitofthenextframeisrecognized.

Rev. 1.10 1 ne 0 01 Rev. 1.10 13 ne 0 01



UART ReceiverTheUARTiscapableofreceivingwordlengthsofeither8or9bitscanbeselectedbyprogrammingtheBNObit intheUCR1register.WhenBNObit isset, thewordlengthwillbeset to9bits.Inthiscasethe9thbit,whichistheMSB,willbestoredintheRX8bitintheUCR1register.AtthereceivercoreliestheReceiverShiftRegistermorecommonlyknownastheRSR.ThedatawhichisreceivedontheRXexternalinputpinissenttothedatarecoveryblock.Thedatarecoveryblockoperatingspeedis16timesthatofthebaudrate,whilethemainreceiveserialshifteroperatesatthebaudrate.AftertheRXpinissampledforthestopbit,thereceiveddatainRSRistransferredtothereceivedataregister,iftheregisterisempty.ThedatawhichisreceivedontheexternalRXinputpinissampledthreetimesbyamajoritydetectcircuittodeterminethelogiclevelthathasbeenplacedontotheRXpin.ItshouldbenotedthattheRSRregister,unlikemanyotherregisters,isnotdirectlymappedintotheDataMemoryareaandassuchisnotavailabletotheapplicationprogramfordirectread/writeoperations.

Receiving DataWhentheUARTreceiverisreceivingdata,thedataisseriallyshiftedinontheexternalRXinputpintotheshiftregister,withtheleastsignificantbitLSBfirst.TheRXRregisterisatwobytesdeepFIFOdatabuffer,wheretwobytescanbeheldintheFIFOwhilethethirdbytecancontinuetobereceived.NotethattheapplicationprogrammustensurethatthedataisreadfromRXRbeforethethirdbytehasbeencompletelyshiftedin,otherwisethethirdbytewillbediscardedandanoverrunerrorOERRwillbesubsequentlyindicated.Thestepstoinitiateadatatransfercanbesummarizedasfollows:

• MakethecorrectselectionoftheBNO,PRT,PRENandSTOPSbitstodefinetherequiredwordlength,paritytypeandnumberofstopbits.

• SetuptheBRGregistertoselectthedesiredbaudrate.

• SettheRXENbittoensurethattheUARTreceiverisenabledandtheRXpinisusedasaUARTreceiverpin.

Atthispointthereceiverwillbeenabledwhichwillbegintolookforastartbit.

Whenacharacterisreceived,thefollowingsequenceofeventswilloccur:

• TheRXIFbitintheUSRregisterwillbesetthenRXRregisterhasdataavailable,atleastthreemorecharactercanberead.

• WhenthecontentsoftheshiftregisterhavebeentransferredtotheRXRregisterandiftheRIEbitisset,thenaninterruptwillbegenerated.

• Ifduringreception,aframeerror,noiseerror,parityerrororanoverrunerrorhasbeendetected,thentheerrorflagscanbeset.

TheRXIFbitcanbeclearedusingthefollowingsoftwaresequence:


• ARXRregisterreadexecution

Rev. 1.10 1 ne 0 01 Rev. 1.10 15 ne 0 01



Receiving BreakAnybreakcharacterreceivedbytheUARTwillbemanagedasaframingerror.ThereceiverwillcountandexpectacertainnumberofbittimesasspecifiedbythevaluesprogrammedintotheBNOandSTOPSbits.Ifthebreakismuchlongerthan13bittimes,thereceptionwillbeconsideredascompleteafterthenumberofbittimesspecifiedbyBNOandSTOPS.TheRXIFbitisset,FERRisset,zerosareloadedintothereceivedataregister,interruptsaregeneratedifappropriateandtheRIDLEbitisset.Ifalongbreaksignalhasbeendetectedandthereceiverhasreceivedastartbit,thedatabitsandtheinvalidstopbit,whichsetstheFERRflag,thereceivermustwaitforavalidstopbitbefore lookingfor thenextstartbit.Thereceiverwillnotmaketheassumptionthat thebreakconditiononthelineisthenextstartbit.AbreakisregardedasacharacterthatcontainsonlyzeroswiththeFERRflagset.Thebreakcharacterwillbeloadedintothebufferandnofurtherdatawillbereceiveduntilstopbitsarereceived.ItshouldbenotedthattheRIDLEreadonlyflagwillgohighwhenthestopbitshavenotyetbeenreceived.ThereceptionofabreakcharacterontheUARTregisterswillresultinthefollowing:

• Theframingerrorflag,FERR,willbeset.

• Thereceivedataregister,RXR,willbecleared.

• TheOERR,NF,PERR,RIDLEorRXIFflagswillpossiblybeset.

Idle StatusWhenthereceiverisreadingdata,whichmeansitwillbeinbetweenthedetectionofastartbitandthereadingofastopbit,thereceiverstatusflagintheUSRregister,otherwiseknownastheRIDLEflag,willhaveazerovalue.Inbetweenthereceptionofastopbitandthedetectionofthenextstartbit,theRIDLEflagwillhaveahighvalue,whichindicatesthereceiverisinanidlecondition.

Receiver InterruptThereadonlyreceiveinterruptflagRXIFintheUSRregister issetbyanedgegeneratedbythereceiver.Aninterrupt isgenerated ifRIE=1,whenawordis transferredfromtheReceiveShiftRegister,RSR,totheReceiveDataRegister,RXR.AnoverrunerrorcanalsogenerateaninterruptifRIE=1.

Rev. 1.10 1 ne 0 01 Rev. 1.10 15 ne 0 01



Managing Receiver ErrorsSeveraltypesofreceptionerrorscanoccurwithintheUARTmodule,thefollowingsectiondescribesthevarioustypesandhowtheyaremanagedbytheUART.

Overrun Error – OERRTheRXRregisteriscomposedofatwobytesdeepFIFOdatabuffer,wheretwobytescanbeheldintheFIFOregister,whileathirdbytecancontinuetobereceived.Beforethethirdbytehasbeenentirelyshiftedin,thedatashouldbereadfromtheRXRregister.If thisisnotdone,theoverrunerrorflagOERRwillbeconsequentlyindicated.

Intheeventofanoverrunerroroccurring,thefollowingwillhappen:

• TheOERRflagintheUSRregisterwillbeset.

• TheRXRcontentswillnotbelost.

• Theshiftregisterwillbeoverwritten.

• AninterruptwillbegeneratediftheRIEbitisset.

TheOERRflagcanbeclearedbyanaccess to theUSRregisterfollowedbyareadto theRXRregister.

Noise Error – NFOver-sampling isusedfordata recovery to identifyvalid incomingdataandnoise. Ifnoise isdetectedwithinaframe,thefollowingwilloccur:

• Thereadonlynoiseflag,NF,intheUSRregisterwillbesetontherisingedgeoftheRXIFbit.

• DatawillbetransferredfromtheshiftregistertotheRXRregister.

• Nointerruptwillbegenerated.Howeverthisbitrisesat thesametimeastheRXIFbitwhichitselfgeneratesaninterrupt.

NotethattheNFflagisresetbyaUSRregisterreadoperationfollowedbyanRXRregisterreadoperation.

Framing Error – FERRThereadonlyframingerrorflag,FERR,intheUSRregister,issetifazeroisdetectedinsteadofstopbits.Iftwostopbitsareselected,bothstopbitsmustbehigh.OtherwisetheFERRflagwillbeset.TheFERRflagisbufferedalongwiththereceiveddataandisclearedinanyreset.

Parity Error – PERRThereadonlyparityerrorflag,PERR,intheUSRregister,issetiftheparityofthereceivedwordisincorrect.Thiserrorflagisonlyapplicableiftheparityfunctionisenabled,PREN=1,andiftheparitytype,oddoreven,isselected.ThereadonlyPERRflagisbufferedalongwiththereceiveddatabytes.Itisclearedonanyreset,itshouldbenotedthattheFERRandPERRflagsarebufferedalongwiththecorrespondingwordandshouldbereadbeforereadingthedataword.

Rev. 1.10 16 ne 0 01 Rev. 1.10 17 ne 0 01



UART Interrupt StructureSeveralindividualUARTconditionscangenerateaUARTinterrupt.Whentheseconditionsexist,a lowpulsewillbegeneratedtoget theattentionof themicrocontroller.Theseconditionsareatransmitterdataregisterempty, transmitter idle,receiverdataavailable,receiveroverrun,addressdetectandanRXpinwake-up.Whenanyof theseconditionsarecreated, if itscorrespondinginterruptcontrol isenabledandthestackisnotfull, theprogramwill jumpto itscorrespondinginterruptvectorwhere itcanbeservicedbefore returning to themainprogram.Fourof theseconditionshavethecorrespondingUSRregisterflagswhichwillgenerateaUARTinterruptif itsassociated interruptenablecontrolbit in theUCR2register isset.The twotransmitter interruptconditionshave theirowncorrespondingenablecontrolbits,while the two receiver interruptconditionshaveasharedenablecontrolbit.TheseenablebitscanbeusedtomaskoutindividualUARTinterruptsources.

Theaddressdetectcondition,whichisalsoaUARTinterruptsource,doesnothaveanassociatedflag,butwillgenerateaUARTinterruptwhenanaddressdetectconditionoccurs if itsfunctionisenabledbysettingtheADDENbit in theUCR2register.AnRXpinwake-up,whichisalsoaUARTinterruptsource,doesnothaveanassociatedflag,butwillgenerateaUARTinterrupt ifthemicrocontrolleriswokenupbyafallingedgeontheRXpin,iftheWAKEandRIEbitsintheUCR2registerareset.NotethatintheeventofanRXwake-upinterruptoccurring,therewillbeacertainperiodofdelay,commonlyknownastheSystemStart-upTime,fortheoscillatortorestartandstabilizebeforethesystemresumesnormaloperation.

Note that theUSRregister flagsare readonlyandcannotbeclearedorsetby theapplicationprogram,neitherwill theybeclearedwhen theprogramjumps to thecorresponding interruptservicing routine, as is the case for someof theother interrupts.The flagswill be clearedautomaticallywhencertainactionsare takenbytheUART,thedetailsofwhicharegivenintheUARTregistersection.TheoverallUARTinterruptcanbedisabledorenabledby the relatedinterruptenablecontrolbitsintheinterruptcontrolregistersofthemicrocontrollertodecidewhethertheinterruptrequestedbytheUARTmoduleismaskedoutorallowed.

UART Interrupt Scheme

Rev. 1.10 16 ne 0 01 Rev. 1.10 17 ne 0 01



Address Detect ModeSettingtheAddressDetectfunctionenablecontrolbit,ADDEN,intheUCR2register,enablesthisspecialfunction.Ifthisbitissetto1,thenanadditionalqualifierwillbeplacedonthegenerationofaReceiverDataAvailable interrupt,which isrequestedbytheRXIFflag. If theADDENbitisequal to1, thenwhenthedata isavailable,an interruptwillonlybegenerated, if thehighestreceivedbithasahighvalue.NotethattherelatedinterruptenablecontrolbitandtheEMIbitofthemicrocontrollermustalsobeenabledforcorrectinterruptgeneration.Thehighestaddressbitisthe9thbitifthebitBNO=1orthe8thbitifthebitBNO=0.Ifthehighestbitishigh,thenthereceivedwordwillbedefinedasanaddressratherthandata.ADataAvailableinterruptwillbegeneratedeverytimethelastbitofthereceivedwordisset.IftheADDENbitisequalto0,thenaReceiveDataAvailableinterruptwillbegeneratedeachtimetheRXIFflagisset,irrespectiveofthedatalastbutstatus.Theaddressdetectionandparityfunctionsaremutuallyexclusivefunctions.Therefore,iftheaddressdetectfunctionisenabled,thentoensurecorrectoperation,theparityfunctionshouldbedisabledbyresettingtheparityfunctionenablebitPRENtozero.

ADDEN Bit 9 if BNO=1, Bit 8 if BNO=0 UART Interrupt Generated

00 √1 √

10 ×1 √

ADDEN Bit Function

UART Power Down Mode and Wake-upWhentheMCUisinthePowerDownMode,theUARTwillceasetofunction.Whenthedeviceenters thePowerDownMode,allclocksourcestothemoduleareshutdown.If theMCUentersthePowerDownModewhilea transmissionisstill inprogress, the transmissionwillbepauseduntiltheUARTclocksourcederivedfromthemicrocontrollerisactivated.Inasimilarway,iftheMCUentersthePowerDownModewhilereceivingdata,thenthereceptionofdatawilllikewisebepaused.WhentheMCUentersthePowerDownMode,notethattheUSR,UCR1,UCR2,transmitandreceiveregisters,aswellastheBRGregisterwillnotbeaffected.ItisrecommendedtomakesurefirstthattheUARTdatatransmissionorreceptionhasbeenfinishedbeforethemicrocontrollerentersthePowerDownmode.

TheUARTfunctioncontainsareceiverRXpinwake-upfunction,which isenabledordisabledbytheWAKEbitintheUCR2register.Ifthisbit,alongwiththeUARTenablebit,UARTEN,thereceiverenablebit,RXENandthereceiverinterruptbit,RIE,areallsetbeforetheMCUentersthePowerDownMode,thenafallingedgeontheRXpinwillwakeuptheMCUfromthePowerDownMode.Note thatas it takescertainsystemclockcyclesafterawake-up,beforenormalmicrocontrolleroperationresumes,anydatareceivedduringthistimeontheRXpinwillbeignored.

ForaUARTwake-upinterrupttooccur,inadditiontothebitsforthewake-upbeingset,theglobalinterruptenablebit,EMI,andtheUARTinterruptenablebit,URE,mustalsobeset.Ifthesetwobitsarenotsetthenonlyawakeupeventwilloccurandnointerruptwillbegenerated.Notealsothatasittakescertainsystemclockcyclesafterawake-upbeforenormalmicrocontrollerresumes,theUARTinterruptwillnotbegenerateduntilafterthistimehaselapsed.

Rev. 1.10 18 ne 0 01 Rev. 1.10 19 ne 0 01



Digital to Analog Converter − DACThedeviceincludesa12-bitDigitaltoAnalogConverterfunction.Thisfunctionallowsdigitaldatacontainedinthedevicetogenerateaudiosignals.

OperationThedata tobeconvertedisstoredin tworegistersDALandDAH.TheDAHregisterstores thehighest8-bits,DA11~DA4,whileDALstoresthelowest4-bits,DA3~DA0.Anadditionalcontrolregister,DACTRL,providesoverallDACon/offcontrol inaddition toa3-bit8-levelvolumecontrol.TheDACoutput ischanneledtopinAUDwhichispin-sharedwithI/OpinPC0.WhentheDACisenabledbysettingtheDACENbithigh,thentheoriginalI/Ofunctionwillbedisabled,alongwithanypull-highresistoroptions.TheDACoutputreferencevoltageis thepowersupplyvoltageVDD.

DAH Register

Bit 7 6 5 4 3 2 1 0Name DA11 DA10 DA9 DA8 DA7 DA6 DA5 DAR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 DA11~DA4:AudioOutputDAChighbytedata.

DAL Register

Bit 7 6 5 4 3 2 1 0Name DA3 DA DA1 DA0 — — — —R/W R/W R/W R/W R/W — — — —POR 0 0 0 0 — — — —

Bit7~4 DA3~DA0:AudioOutputDAClowbytedata.Bit3~0 Unimplemented,readas″0″

DACTRL Register

Bit 7 6 5 4 3 2 1 0Name VOL VOL1 VOL0 — — — — DACENR/W R/W R/W R/W — — — — R/WPOR 0 0 0 — — — — 0

Bit7~5 VOL2~VOL0:AudioOutputVolumecontrol.Theaudiooutputisatmaximumvolumeifthesebitsaresetto111Bwhiletheaudiooutputisatminimumvolumeifthesebitsaresetto000B.

Bit4~1 Unimplemented,readas″0″Bit0 DACEN:DACenableControl

0:DACisdisabled1:DACisenabled

Rev. 1.10 18 ne 0 01 Rev. 1.10 19 ne 0 01



DC/DC Converter and LDOThedevicecontainsaDC/DCConverterandanLDOtoprovidethepowersupplyfortheSmartCardinterfacepinsandtheexternalSmartCard.

TheDC/DCConverterisaPFMstep-upDC/DCconverterwithhighefficiencyandlowripple.Itrequiresonlythreeexternalcomponentstoprovideanoutputvoltageofeither3.8Vor5.5Vselectedby theDC/DCoutputvoltageselectionbitVSELin theDC2DCregister.TheDC/DCvoltageoutput isconnected toanexternalpin,VO,and thenmustexternallybeconnected to theLDOinput,LDOIN.Italsocontainsanenablecontrolbit,DCEN,intheDC2DCregistertoreducepowerconsumptionwheninthepowerdownmode.IftheSmartCardvoltageoutputisswitchedto0VbyclearingtheselectionbitsVC[1:0]intheCCRregister,theDC/DCconverterwillautomaticallybeturnedoffeveniftheenablecontrolbitDCENissetto1.

TheLDOisathree-terminalhighcurrentlowvoltagedropoutregulatorwithovercurrentprotection.Itsupportsthreeoutputvoltagesof1.8V,3.0Vor5.0VselectedbytheSmartCardVoltageselectionbitsVC1andVC0intheCCRregister.Itcandeliveramaximumoutputcurrentof35mA,55mAand60mAwhentheLDOoutputvoltageis1.8V,3.0Vand5.0Vrespectively.

VDD

DC/DC Converter

SELF VO

LDO

DCEN VSEL VC1

CVSSCRDVCC

VC0CRST

CC8

VSSSmart CardInterface pins

CDET

VDD

LDOVSSLDOIN

100uH/2Ω BEAD

22uF 10pF

4.7uF

DC/DC Converter Block Diagram

DC2DC Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — DCEN VSELR/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas″0″Bit1 DCEN:DC/DCenablecontrol

0:DC/DCconverterdisabled1:DC/DCconverterenabled

ThisbitisusedtocontroltheDC/DCconverterfunction.Ifthisbitissetto″1″,theDC/DCoutputvoltageisselectedbytheVSELselectionbit.Ifthisbitisclearedto0,theDC/DCconverterfunctionisdisabledandtheoutputvoltageisequaltothevalueof(VDD−VDIODE).

Bit0 VSEL:DC/DCoutputvoltageselection0:DC/DCoutputvoltageis3.8V1:DC/DCoutputvoltageis5.5V

Rev. 1.10 130 ne 0 01 Rev. 1.10 131 ne 0 01



Smart Card InterfaceThedevicecontainsaSmartCard Interfacecompatiblewith the ISO7816-3 standard.Thisinterface includes theCardInsertion/Removaldetection,UARTinterfacecontrol logicanddatabuffers,Powercontrolcircuits, internalTimerCountersandcontrol logiccircuits toperformtherequiredSmartCardoperations.TheSmartCardinterfaceactsasaSmartCardReadertofacilitatecommunicationwiththeexternalSmartCard.TheoverallfunctionsoftheSmartCardinterfaceiscontrolbyaseriesofregistersincludingcontrolandstatusregisters.

As the complexity of ISO7816-3 standard data protocol does not permit comprehensivespecifications tobeprovidedinthisdatasheet, thereadershouldthereforeconsultotherexternalinformationforadetailedunderstandingofthisstandard.

CRDVCCElementary Time Unit

(ETU)

Gard Time Conter(GTC)

fCCLK

UART control circits

UART TX/RX bffers

Interrpt Registers

Interrpt to MCU

Power Control

CDETCard Detection

CRST

CIO

CC

CC8

I/O Control

Clock Control

fETU

fETU

fGTC

fWTC CRDVCC

VDD

SMCEN

Waiting Time Conter(WTC)

Control R

egisters

CCLK

Interface PinsTocommunicatewithanexternalSmartCard, the internalSmartCard interfacehasaseriesofexternalpinsknownasCRDVCC,CRST,CCLK,CIO,CC4,CC8andCDET.TheCRDVCCpinisthepowersupplypinofoftheexternalSmartCardandtheSmartCardinterfacepinsdescribedaboveexcepttheCDETpin.ItcanoutputseveralvoltagelevelsasselectedbytheVC1andVC0selectionbits.TheCRSTpinis theresetoutputsignalwhichisusedtoreset theexternalSmartCard.Togetherwith the internalCRSTcontrolbit theMCUcancontrol theCRSTpin levelbywritingspecificdatatotheCRSTbitandobtaintheCRSTpinstatusbyreadingtheCRSTbit.TheCCLKpinis theclockoutputsignalusedtocommunicatewiththeexternalSmartCardtogetherwiththeserialdatapin,CIO.TheoperationofCCLKandCIOcanbeselectedastheUARTmodeautomaticallydrivenbytheUARTcontrolcircuits,ortheManualmodecontrolledbyconfiguringthe internalCCLKandCIObits respectivelyby theapplicationprogram.TheCDETpin is theexternalSmartCarddetectioninputpin.WhentheexternalSmartCard is insertedorremoved,itcanbedetectedandgeneratean interruptsignalwhich issent toMCUif thecorrespondinginterruptcontrolbitisenabled.TheCC4andCC8pinsareusedasI/OpinsandarecontrolledbythecorrespondingCC4andCC8bits.

Rev. 1.10 130 ne 0 01 Rev. 1.10 131 ne 0 01



Card DetectionIfanexternalSmartCardisinserted,theinternalcarddetectorcandetectthisinsertionoperationandgenerateaCardinsertioninterrupt.WhentheCardispresentanddetected,thepower-onsequencefortheexternalSmartCardshouldbeactivatedbytheapplicationprogramstosupplypowerfortheexternalSmartCard.SimilarlyiftheCardisremoved,theinternalcarddetectorcanalsodetecttheremovalandconsequentlygenerateaCardremovalinterrupt.LiketheCardinsertionoperation,theCardRemovaldeactivationproceduredefinedintheISO7816-3standardshouldbeactivatedbytheapplicationprograms.

Thecarddetectorcansupport twokindsofcarddetectswitchmechanisms.One isanormallyopenswitchmechanismwhen thecard isnotpresentand theother isanormallyclosedswitchmechanism.Afternotingwhichcarddetectswitchmechanismtypeisused,thecardswitchselectionshouldbeconfiguredbysettingtheselectionbitCDETintheCCRRegistertocorrectlydetecttheCardpresence.NomatterwhattypeofthecardswitchisselectedbyconfiguringtheCDETbit,theCardInsertion/RemovalFlag,CIRF,intheCSRregisterwillbesetto″1″whenthecardisactuallypresentontheCDETpin,andclearto"0"bytheapplicationprogram.Notethatthereisnohardwarede-bouncecircuitsinthecarddetector.AnychangeoftheCDETpinlevelwillcausetheCIRFbittochange.Therequiredde-bouncetimeshouldbehandledbytheapplicationprogram.

Thereisapullhighresistorintegratedinthecarddetector.AconfigurationoptioncandeterminewhetherthepullhighresistorisinternallyconnectedtotheCDETpin.

Internal Time Counter − ETU, GTC, WTCForproperdatatransfer,sometimingpurposedsettingproceduresmustbeexecutedbeforetheSmartCardInterfacecanbegintocommunicatewiththeexternalcard.TherearethreeinternalcountersnamedElementaryTimeUnit(ETU),GuardTimeCounter(GTC)andWaitingTimeCounter(WTC)whichareusedforthetimingrelatedfunctionsintheSmartCardinterfaceoperation.

Elementary Time Unit − ETUTheElementaryTimeUnit(ETU)isan11-bitup-countingcounterandgeneratestheclock,denotedasfETUtobeusedastheoperatingfrequencyfortheUARTtransmissionandreceptionintheSmartCard interface.Theclocksourceof theETUnamedasfCCLKcomesfromthefCRDclockandthefrequencyoffCCLKcanbefCRDorfCRD/2whichisselectedusingtheSMFbitintheMISC0register.ThefCRDclockisderivedfromthehighspeedclock,fM,andthefCRDfrequencycanbeequaltothefrequencyoffM,fM/2,fM/3orfM/4selectedbytheSmartCardclocksourceselectionbits,CRDCKS1andCRDCKS0

Thedata transferof theUARTinterface isacharacterframebasedprotocol,whichisbasicallyconsistsofaStartbit,8-bitdataandaParitybit.ThetimeperiodtETU(1/fETU),generatedbytheETU,isthetimeunitforUARTcharacterbit.TherearetworegistersrelatedtotheETUknownasthelowbyteETUregisterCETU0andthehighbyteETUregisterCETU1,whichstoretheexpectedcontentsoftheETU.EachtimethehighbyteETUregisterCETU1iswritten,theETUwillreloadthenewwrittenvalueandrestartcounting.Theelementary timeunit tETU isobtainedfromthefollowingformula.

tETU=(F/D)×(1/f)

F:clockrateconversioninteger

D:baudrateadjustmentinteger

f:clockrateofSmartCard

Rev. 1.10 13 ne 0 01 Rev. 1.10 133 ne 0 01



ThevaluesofFandD,as theyappear in theaboveformula,willbeobtainedfromtheAnswer-to-ResetpacketsentfromtheexternalSmartCardto theSmartCardinterface, thefirst timetheexternalSmartCardisinserted.WhentheSmartCardinterfacereceivesthisinformation,thevalueswhichshouldbewrittenintotheCETU0andCETU1canbecalculatedbyF/D.AsthevalueoftheETUregistersisobtainedbytheaboveformula,thecalculationresultsofthevaluemaynotbeaninteger.Ifthecalculationresultisnotanintegerandislessthantheintegernbutgreaterthantheinteger(n-1),eithertheintegernor(n-1)shouldbewrittenintotheCETU0andCETU1registersdependinguponwhethertheresultisclosertonor(n-1).Theintegernmentionedhereisadecimal.Ifthecalculationresultisclosetothevalueof(n-0.5), thecompensationmodeshouldbeenabledbysettingthecompensationenablecontrolbitCOMPintheCETU1registerto1forsuccessfuldatatransfer.Whentheresultisclosetothevalueof(n-0.5)andthecompensationmodeisenabled,thevaluewrittenintotheCETU0andCETU1registersshouldbenandthentheETUwillgeneratethetimeunitsequencewithnclockcyclesandnext(n-1)clockcyclesalternatelyandsoon.Thisresultsinanaveragetimeunitof(n-0.5)clockcyclesandallowsthetimegranularitydowntoahalfclockcycle.NotethattheETUwillreloadtheETUregistersvalueandrestartcountingatthetimewhentheStartbitappearsintheUARTmode.

CIO

Start bit

P

Parity bit

Character

COMP=0

COMP=1

n n n n n n n n n n

n n-1 n n n nn-1 n-1 n-1 n-1

(1 tETU=n clocks)

(CETU=n)

tETU

Data bits

Character Frame and Compensation Mode

Guard Time Counter − GTCTheGuardTimeCounter(GTC)isa9-bitup-countingcounterandgeneratestheminimumtimedurationknownasacharacter framedenotedas tGTCbetween twosuccessivecharacters inaUARTtransmission.TheclocksourceoftheGTCcomesfromtheETUnamedfETU.ThecharactertransmissionrateoftheUARTinterfaceiscontrolledbytGTCgeneratedbytheGTC.TherearetworegistersrelatedtotheGTCknownasthelowbyteGTCregister,CGT0,andthehighbyteGTCregister,CGT1,whichstoretheexpectedvalueoftheGTC.TheGTCvaluewillbereloadedattheendofthecurrentguardtimeperiod.NotethattheguardtimebetweenthelastcharacterreceivedfromtheSmartCardandthenextcharactertransmittedbytheSmartCardinterface(SmartCardreader)shouldbemanagedbytheapplicationprogram.

Rev. 1.10 13 ne 0 01 Rev. 1.10 133 ne 0 01



Waiting Time Counter − WTCTheWaitingTimeCounter(WTC)isa24-bitdown-countingcounterandgeneratesamaximumtimedurationdenotedastWTCforthedatatransmission.TheclocksourceoftheWTCcomesfromtheETUnamedfETU.Thedatatransferiscategorizedinto2types.OneistheCharactertransferwhichmeanseachdatatransmissionorreceptionisonecharacterwhiletheotheris theBlockstransferwhichmeanseachdatatransmissionorreceptionismorethanonecharacter.TheinformationrelatedtothedatatransfertypeorthenumberofthecharacterstobetransferrediscontainedintheAnswer-to-Resetpacket.

TherearethreedataregistersfortheWTCknownasthelowbyteWTCregisterCWT0,themiddlebyteWTCregisterCWT1andthehighbyteWTCregisterCWT2,whichstoretheexpectedWTCvalues.TheWTCcanbeusedinbothUARTmodeandManualmodeandcanreloadthevalueatspecificconditions.ThefunctionoftheWTCiscontrolledbytheWTENbitintheCCRregisterorbyaconfigurationoption.WhentheUARTinterfaceissettobeoperatedintheUARTmodeandtheWTCisenabled,theupdatedCWTvaluewillbeloadedintotheWTCastheStartbitisdetected.IftheUARTinterfaceissettobeoperatedintheManualmodeandtheWTCisenabled,theupdatedCWTvaluewillbeloadedintotheWTC.RegardlessofwhetheritisintheUARTmodeorManualmode,iftheWTENbitisclearedto″0″,theupdatedCWTvaluewillnotbeloadedintotheWTCuntiltheWTENbitisagainsetto1andtheWTCunderflowsfromthecurrentloadedvalue.

WhenthetransfertypeisconfiguredasaCharactertransfer,theWTCwillgeneratethemaximumtimeoutperiodoftheCharacterWaitingTime(CWT).IfthetransfertypeisconfiguredasaBlocktransfer,theWTCwillgeneratetheCharacterWaitingTime(CWT)exceptforthelastcharacter.TheBlockWaitingTime(BWT)shouldbeloadedintotheWTCdataregistersbeforetheStartbitofthelasttransmittedcharacteroccurs.AstheStartbitofthelasttransmittedcharacteroccurs,theBWTvaluewillbeloadintotheWTC.ThentheSmartCardmaybeexpectedtotransmitdatatotheSmartCardinterfaceintheBWTduration.If theSmartCarddoesnottransmitanydatacharacters, theWTCwillunderflow.WhentheWTCunderflows,thecorrespondingrequestflag,WTF,intheCSRregisterwillbeset.TheWaitingTimeUnderflowpendingflag,WTP,intheCIPRregister,willalsobesetiftheinterruptenablecontrolbit,WTE,intheCIERregisterisset.ThenaninterruptwillbegeneratedtonotifytheMCUthattheSmartCardhasnotrespondedtotheSmartCardreader.NotethatiftheWTCvalueissettozero,theWFTbitwillbeequalto″1″.

Smart Card Interface

Smart Card

Char 0 Char 1 Char n

Programthe BWT

BWT

Programthe CWT

Char 1

CWT

Start bit

Start bit

Char 0

WTC is reloaded on Start bit

Rev. 1.10 13 ne 0 01 Rev. 1.10 135 ne 0 01



Smart Card UART ModeDatatransferwiththeexternalSmartCardis implementedintotwooperatingmodes.Oneis theUARTmodewhiletheotheristheManualmode.ThedatatransfermodeisselectedbytheUARTmodeselectionbit,UMOD,intheCCRregister.WhentheUMODbitissetto″1″,theUARTmodeisenabledanddatatransferoperatesintheUARTmode.Otherwise,datatransferoperatesintheManualmodeif theUMODbit isset to″0″.TheUARTinterface isahalf-duplex interfaceandcommunicateswiththeexternalSmartCardviatheCCLKandCIOpins.TheCIOpincanbeselectedtobeconnectedtoapullhighresistorbyaconfigurationoption.AfteraresetconditiontheUARTinterfaceisinthereceptionmodebuttheUARTmodeisdisabled.WhentheUARTmodeisselected,datatransferisdrivenbytheUARTcircuitsautomaticallythroughtheCCLKandCIOpins.

Therearetwodataregistersrelatedtodatatransmissionandreception,CTXBandCRXB,whichstorethedatatobetransmittedandreceivedrespectively.IfacharacteriswrittenintotheCTXBregisterintheUARTmode,theUARTinterfacewillautomaticallyswitchtothetransmissionmodefromthereceptionmodeafterareset.WhentheUARTtransmissionorreceptionhasfinished,thecorrespondingrequestflagnamedTXCForRXCFissetto″1″.Ifthetransmitbufferisempty,thetransmitbufferemptyflag,TXBEF,willbesetto″1″.

TheUARTinterfacesupportsaparitygeneratorandaparitycheckfunction.Astheparityerroroccursduringadata transfer, thecorrespondingrequest flagnamed,PARF, in theCSRregisterwillbesetto″1″.OncethePARFbitissetto″1″,theParityerrorpendingflagPARPintheCIPRregisterwillbesetto″1″iftherelevantinterruptcontrolbitisenabled.ThenaninterruptsignalwillbegeneratedandsenttotheMCU.

There isaCharacterRepetitionfunctionsupportedby theUARTinterfacewhenaparityerroroccurs.TheCharacter repetitionfunction isenabledbysetting theCREPbit to1and then therepetitionfunctionisactivatedwhentheparityerroroccursduringdata transfers.Therepetitiontimescanbeselectedtobe4or5timesbyaconfigurationoption.WhentheCREPbitissetto1and therepetition times isset to4 times, theUARTinterface, if in the transmissionmode,willtransmitthedatarepeatedlyfor4timesatmostwhenanerrorsignaloccurs.IfthedatatransmittedbytheUARTinterfaceisreceivedbytheSmartCardreceiverwithoutaparityerrorduringthese4transmissions,thetransmissionrequestflag,TXCF,oftheUARTinterfacewillbesetto1andthePARFbitwillbeclearedto0.If theUARTinterfaceisinformedthatthereisstillanerrorsignalduringthe4transmissions,theparityerrorflagPARFoftheUARTinterfacewillbesetto1attheendof the4th transmissionbut the transmissionrequestflagTXCFwillnotbeset. If theUARTinterface is in thereceptionmode togetherwith theCREPbitbeingset to1, itwill informtheexternalSmartCardtransmitterthatthereisaparityerrorforatmost4times.IfthedatatransmittedbytheexternalSmartCardtransmitter isreceivedbytheUARTinterfacewithoutaparityerrorduringthe4receptions, thereceptionrequestflag,RXCF,oftheUARTinterfacewillbeset to1andthePARFbitwillbeclearedto0.Ifthereisstillaparityerrorduringthe4datareceptions,theUARTinterfacewillinformtheexternalSmartCardandtheparityerrorflag,PARF,oftheUARTinterfacewillbesetto1attheendofthe4threceptionaswellasthereceptionrequestflag,RXCF.

IftheCREPbitissetto″0″andtheUARTinterfaceisinthereceptionmode,boththePARFandRXCFbitswillbeset to″1″whenthedatawithparityerrorhasbeenreceivedbutthecharacterrepetitionwillnotbeactivated.If theUARTinterfaceis inthetransmissionmodeandtheCREPbitissetto″0″,itactsasanormaltransmitterandtheTXCFbitissetto″1″afterthedatahasbeentransmitted.IthasnoeffectonPARFbit.

Rev. 1.10 13 ne 0 01 Rev. 1.10 135 ne 0 01



WhendataisselectedtobetransferredintheManualmodebysettingtheUMODbitto0,thedataiscontrolledbythecontrolbit,CIO,intheCCCRregister.ThevalueoftheCIObitwillbereflectedimmediatelyon theCIOpin in theManualmode.Note that in theManualmode thecharacterrepetitionfunctionisnotavailableaswellastherelatedflagsandallthedatatransferishandledbytheapplicationprogram.TheclockusedtodrivetheexternalSmartCardthatappearsontheCCLKpincanbethefCCLKclockwhichisderivedfromtheinternalclocksourcenamedasthefCRDclockorthecontrolbit,CCLK,inCCCRregisterandselectedbytheSmartCardselectionbit,CLKSEL,intheCCCRregister.WhenCLKSELissetto1toselecttheclocksourcefortheSmartCardtobefCCLK,asoftwarecontrolbit,SMF,candeterminewhethertheclockoutputontheCCLKpin,whichcomesfromthefCRDclock,ismoreovertobedividedby2ornot.IfuserswishtohandletheCCLKclockmanually,theCLKSELbitshouldfirstbesetto0andthenthevalueoftheCCLKbitwillbepresentontheCCLKpin

WhentheSmartCardisfirstinserted,thedatadirectionconventionissentfirstintheAnswer-to-ResetpackettoinformtheSmartCardinterfacewhethertheMSBofthedataissentfirstortheLSBissentfirst.IfthedirectionconventionusedbytheSmartCardisthesameastheconventionusedbytheSmartCardinterface,theUARTinterfacewillgenerateareceptioninterruptifthereceptioninterrupt isenabledwithoutaparityerror flag.Otherwise, theUARTinterfacewillgenerateareceptioninterruptandtheparityerrorflagwillbeasserted.BycheckingtheparityerrorflagtheSmartCardinterfacecanknowifthedatadirectionconventioniscorrectornot.

Power ControlWhentheSmartCardisfirstinsertedanddetected, thepower-onsequencefortheexternalSmartCardshouldbeactivatedbytheapplicationprogramstosupplypowertotheexternalSmartCard.AlltheinformationnecessaryfortheSmartCardinterfacetocommunicatewiththeexternalCardiscontainedintheAnswer-to-Resetpacketincludingthedatatransfertype(CharacterorBlocks),thedatadirectionconvention(MSBorLSBfirst),theclockrateinformation(ETU,GTCorWTC),etc.Thevoltagelevelsuppliedto theSmartCardisalsodefinedin theAnswer-to-Resetpacket.TheSmartCardpowersupplyvoltage level isgeneratedbytheLDOandselectedbytheSmartCardPowerSupplyvoltageselectionbitsVC1andVC0in theCCRregister.WhentheexternalSmartCardisinserted,theapplicationprogramshouldsettheCRDVCCpintotheexpectedvoltageleveldefinedintheAnswer-to-Resetpacket.Similarly, thepowerdeactivationproceduredefinedintheISO7816-3standardshouldalsobeproperlyarrangedbytheapplicationprogramswhentheexternalSmartCardisremoved.AftertheexternalSmartCardisremoved,theSmartCardInterfaceCircuitryenablecontrolbit,CVCC,intheCCCRRegisterwillbeautomaticallyclearedtozerotopreventtheSmartCardInterfacemodulefrombeingre-modified.TheCRDVCCpinvoltagelevelandtherelatedSmartCardinterfaceregistercontentswillremainunchangedbuttherelevantSmartCardInterfacepinsincludingCRST,CCLK,CIO,CC4andCC8pinswillbekeptata lowlevelwhentheexternalCardisremoved.

ThePowerControlcircuitryprovidestheCardvoltageandcurrentindicatorstoavoidmalfunctions.WhentheCardvoltageiswithin itsspecifiedrange, theCardVoltageflagVCOKwillbeset to″1″. If theCard isnot in thespecifiedrange, theVCOKflagwillbecleared to″0″ to indicatethattheCardvoltageisnotwithinthespecifiedrange.AstheVCOKbitchangesfrom1to0,thecorrespondingpendingflagnamedVCPinCIPRregisterwillbesetto″1″iftheCardVoltageerrorinterruptcontrolVCEintheCIERregisterisenabled.

Rev. 1.10 136 ne 0 01 Rev. 1.10 137 ne 0 01



WhenthecurrentconsumedbytheexternalSmartCardiswithintherangespecifiedin theISO7816-3standard,theCardCurrentOverloadflagIOVFwillremainata″0″value.IftheCardcurrentisnotwithinthespecifiedrange,theIOVFflagwillbesetto″1″toindicatethattheCardCurrentistoohigh.AstheIOVFbitissetto1,therelevantpendingflag,IOVFP,intheCIPRregisterwillalsobesetto1iftheCardCurrentOverloadinterruptcontrolenablebit,IOVFE,intheCIERregisterisenabled.

Smart Card Interrupt StructureThereareseveralconditionsfortheSmartCardthattogenerateaSmartCardinterrupt.Whentheseconditionsexist,an interruptpulsewillbegeneratedtoget theattentionof themicrocontroller.TheseconditionsareaSmartCardInsertion/Removal,aSmartCardVoltageerror,aSmartCardCurrentOverload,aWaitingTimeCounterUnderflow,aParityerror, anendofaCharacterTransmissionorReceptionandanemptyTransmitbuffer.WhenaSmartCardinterruptisgeneratedbyanyoftheseconditions,thenifthecorrespondinginterruptenablecontrolbitinthehostMCUisenabledandthestackisnotfull,theprogramwilljumptothecorrespondinginterruptvectorwhereitcanbeservicedbeforereturningtothemainprogram.

ForSmartCardinterruptevents,exceptforCardInsertion/Removalevents,therearecorrespondingpendingflagswhichcanbemaskedbythecorrespondinginterruptenablecontrolbits.Whentherelated interruptenablecontrol isdisabled, thecorrespondinginterruptpendingflagwillnotbeaffectedbytherequestflagandnointerruptwillbegenerated.Iftherelatedinterruptenablecontrolisenabled, therelevant interruptpendingflagwillbeaffectedby therequest flagand then theinterruptwillbegenerated.ThependingflagregisterCIPRisreadonlyandoncethependingflagisreadbytheapplicationprogram,itwillbeautomaticallyclearedwhiletherelatedrequestflagshouldbeclearedbytheapplicationprogrammanually.

WhenaSmartCardInsertion/Removaleventoccurs,theCardInsertion/Removalrequestflag,CIRF,willbesetorcleardependsonthepresenceofacard,andaSmartCardInsertion/RemovalinterruptwillbedirectlygeneratedwithoutanyassociatedSmartCardinterruptcontrolbeingenabled.

ForaSmartCardinterruptoccurredtobeserviced, inadditionto thebitsfor thecorrespondinginterruptenablecontrolintheSmartCardinterfacebeingset,theglobalinterruptenablecontrolandtherelatedinterruptenablecontrolbitsinthehostMCUmustalsobeset.Ifthesebitsarenotset,thennointerruptwillbeserviced.

Rev. 1.10 136 ne 0 01 Rev. 1.10 137 ne 0 01



CSR Register

Card Insertion/Removal Reqest flag CIRF

Transmit Bffer Empty reqest flag TXBEF

End of Transmission Reqest flag TXCF

End of Reception Reqest flag RXCF

WTC UnderflowReqest flag WTF

Parity ErrorReqest flag PARF

Card Crrent OverloadReqest flag IOVF

Card Voltage StatsReqest flag VCOK

Interrpt Signal to MCU

Transmit Bffer Empty pending flag TXBEP

End of Transmission pending flag TXCP

End of Reception pending flag RXCP

WTC Underflowpending flag WTP

Parity Errorpending flag PARP

Card Crrent Overloadpending flag IOVFP

Card Voltage Errorpending flag VCP

CIPR Register

TXBEE

01

TXCE

01

RXCE

01

PARE

01

WTE

01

IOVFE

01

VCE

01

CIER Register

Interrpt Signal to MCU

Smart Card Interrupt Structure

Programming ConsiderationsSincethewholeSmartCardinterfaceisdrivenbytheclockfCRDwhichisderivedfromthehighspeedoscillator clock fM, theSmartCard interfacewillnotoperate, even interface registersread/writeoperations, if thehighspeedoscillatorclockfM isstopped.Forexample, if theMCUclocksourceisswitchedtothelowspeedclockfSLwhichcomesfromthelowspeedoscillatorLXTorLIRC,thenalloperationsrelatedtotheSmartCardinterfacearenotperformed.

Rev. 1.10 138 ne 0 01 Rev. 1.10 139 ne 0 01



Smart Card Interface Status and Control RegistersThereareseveralregistersassociatedwiththeSmartCardfunction.SomeoftheregisterscontroltheoverallfunctionoftheSmartCardinterfaceaswellastheinterrupts,whilesomeoftheregisterscontainthestatusbitswhichindicatetheSmartCarddatatransfersituations,errorconditionsandpowersupplyconditions.Also thereare tworegistersfor theUARTtransmissionandreceptionrespectivelytostorethedatareceivedfromortobetransmittedtotheexternalSmartCard.

Address Name POR State Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

50H CCR 0000 0000 RSTCRD CDET VC1 VC0 UMOD WTEN CREP CONV51H CSR 1000 0000 TXBEF CIRF IOVF VCOK WTF TXCF RXCF PARF52H CCCR 0-xx x0x0 CLKSEL — CC8 CC CIO CCLK CRST CVCC53H CETU1 0000 0001 COMP — — — — ETU10 ETU9 ETU854H CETU0 0111 0100 ETU7 ETU6 ETU5 ETU ETU3 ETU ETU1 ETU055H CGT1 ---- ---0 — — — — — — — GT856H CGT0 0000 1100 GT7 GT6 GT5 GT GT3 GT GT1 GT057H CWT 0000 0000 WT3 WT WT1 WT0 WT19 WT18 WT17 WT1658H CWT1 0010 0101 WT15 WT1 WT13 WT1 WT11 WT10 WT9 WT859H CWT0 1000 0000 WT7 WT6 WT5 WT WT3 WT WT1 WT05AH CIER 0-00 0000 TXBEE — IOVFE VCE WTE TXCE RXCE PARE5BH CIPR 0-00 0000 TXBEP — IOVFP VCP WTP TXCP RXCP PARP5CH CTXB 0000 0000 Smart Card Transmission Buffer (TB7~TB0)5DH CRXB 0000 0000 Smart Card Reception Buffer (RB7~RB0)

Smart Card Interface Register Summary

Rev. 1.10 138 ne 0 01 Rev. 1.10 139 ne 0 01



CCR RegisterTheCCRregistercontainsthecontrolbitsfortheSmartCardinterface.Furtherexplanationoneachbitisgivenbelow:

Bit 7 6 5 4 3 2 1 0Name RSTCRD CDET VC1 VC0 UMOD WTEN CREP CONVR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 RSTCRD:ResetcontrolfortheSmartCardinterface0:NoSmartCardinterfacereset1:ResettheSmartCardinterface(exceptRSTCRDbit)

ThisbitisusedtoresetthewholeSmartCardinterfaceexcepttheRSTCRDbit.Itissetandclearedbyapplicationprogram.

Bit6 CDET:Cardswitchtypeselection0:Switchisnormallyopenedifnocardispresent1:Switchisnormallyclosedifnocardispresent

Thisbitissetandclearedbyapplicationprogramtoconfiguretheswitchtypeofthecarddetector.

Bit5~4 VC1~VC0:Cardvoltageselection00:Cardvoltageisequalto0V01:Cardvoltageisequalto1.8V10:Cardvoltageisequalto3V11:Cardvoltageisequalto5V

ThesebitsaresetandclearedbyapplicationprogramtoselectthevoltagelevelfortheexternalSmartCard.

Bit3 UMOD:UARTmodeselection0:DatatransferinManualmode.1:DatatransferinUARTmode.

Thisbitissetandclearedbyapplicationprogramtoconfigurethedatatransfertype.Ifitisclearedto0,theCIOpinstatusisthesameasthevalueoftheCIObitintheCCCRregister.If it isset to1, theCIOpinisdrivenbytheinternalUARTcontrolcircuitry.BeforethedatatransfertypeisswitchedfromManualmodetoUARTmode,theCIObitmustbesetto1toavoidaUARTmalfunction.

Bit2 WTEN:WaitingTimeCounter(WTC)countingcontrol0:WTCstopscounting.1:WTCstartstocount.

TheWTENbit issetandclearedbyapplicationprogram.When theWTENbit iscleared to0,awriteaccess to theCWT2registerwill load thevalueheld in theCWT2~CWT0registers into theWTC. If it is set to1, theWTC isenabledandautomaticallyreloadedwiththevalueinCWT2~CWT0ateachstartbitoccurrence.

Bit1 CREP:CharacterRepetitionenablecontrolatparityerrorcondition0:Noretryonparityerror1:Automaticallyretryonparityerror

TheCREPbit is setandclearedbyapplicationprogram.When theCREPbit isclearedto0,boththeRXCFandPARFflagswillbesetonparityerrorinreceptionmodeafterthedataisreceivedwhilethePARFissetbuttheTXCFisclearedinthetransmissionmode.IftheCREPbitissetto1,thecharacterretrywillautomaticallybeactivatedonparityerrorfor4or5timesdependingupontheconfigurationoption.Inthetransmissionmodethecharacterwillbere-transmittedif thetransmitteddataisrefusedandthentheparityerrorflagPARFwillbesetat theendofthe4thor5thtransmissionbutTXCFwillnotbeset.Inthereceptionmodeifthereceiveddatahasaparityerrorduringthe4or5datatransfer,thereceiverwillinformthetransmitterfor4or5timesandthenthePARFandRXCFflagswillbothbesetattheendofthe4thor5threception.

Rev. 1.10 10 ne 0 01 Rev. 1.10 11 ne 0 01



Bit0 CONV:Datadirectionconvention0:LSBistransferredfirst.Setsupthedirectconvention:stateHencodesvalue1andconveystheleastsignificantbitfirst.

1:MSBistransferredfirst.Setsuptheinverseconvention:stateLencodesvalue1andconveysthemostsignificantbitfirst.

Thisbit issetandclearedby theapplicationprogramtoselect if thedata isLSBtransferredfirstorMSBtransferredfirst.Whenthedirectionconventionisthesameas thedirectionspecifiedby theexternalSmartCard,onlyRXCFwillbeset to1withoutparityerror.Otherwise,bothRXCFandPARFwillbesetto1afterthedataisreceived.

CSR RegisterTheCSRregistercontainsthestatusbitsfortheSmartCardinterface.Furtherexplanationoneachbitisgivenbelow:

Bit 7 6 5 4 3 2 1 0Name TXBEF CIRF IOVF VCOK WTF TXCF RXCF PARFR/W R R R R R R/W R R/WPOR 1 0 0 0 0 0 0 0

Bit7 TXBEF:Transmissionbufferemptyrequestflag0:Transmissionbufferisnotempty1:Transmissionbufferisempty

Thisbit isused to indicate if the transmitbuffer isemptyandissetorclearedbyhardwareautomatically.

Bit6 CIRF:CardInsertion/Removalrequestflag0:Nocardispresent.1:ACardispresent

Thisbit isused to indicate ifacard ispresentand is setorclearedbyhardwareautomatically.ThisbitwilltriggerSCIRFbitsynchronously.

Bit5 IOVF:CardCurrentOverloadrequestflag0:NoCardCurrentoverload1:CardCurrentoverload

Thebit issetorclearedbyhardwareautomaticallyandindicateswhether thecardcurrentisoverloaded.

Bit4 VCOK:CardVoltagestatusflag0:CardVoltageisnotinthespecifiedrange1:CardVoltageisinthespecifiedrange

Thebit issetorclearedbyhardwareautomaticallyandindicateswhether thecardvoltageisinthespecifiedrange.

Bit3 WTF:WaitingTimeCounter(WTC)underflowrequestflag0:TheWTCdoesnotunderflow.1:TheWTCunderflows.

Thisbit issetbyhardwareautomaticallyandindicatesif theWTCunderflows,andclearedbyapplicationprogram,whichsteps:clrWTEN,accessCWT2,setWTEN.

Bit2 TXCF:Charactertransmissionrequestflag0:Nocharactertransmittedrequest1:Acharacterhasbeentransmitted

TheTXCFbitissetbyhardwareandclearedbyapplicationprogram.Ifthebitissetto1,itindicatesthatthecharacterhasbeentransmitted.

Rev. 1.10 10 ne 0 01 Rev. 1.10 11 ne 0 01



Bit1 RXCF:CharacterRepetitionrequestflag0:Nocharacterreceivedrequest1:Acharacterhasbeenreceived

TheRXCFbitissetbyhardwareautomaticallyandclearedafterareadaccesstotheCRXBregisterbytheapplicationprogram.TheRXCFbitwillalwaysbesetto1whenacharacterisreceivedregardlessoftheresultoftheparitycheck.Whenthecharacterhasbeenreceived,thereceiveddatastoredintheCRXBregistershouldbemovedtothedatamemoryspecifiedbyusers.IfthecontentsoftheCRXBregisterarenotreadbeforetheendofthenextcharactershiftedin, thedatastoredintheCRXBregisterwillbeoverwritten.

Bit0 PARF:Parityerrorrequestflag0:Noparityerrorrequest1:Parityerrorhasbeenoccurred

Thisbit issetbyhardwareautomaticallyandclearedby theapplicationprogram.Whenacharacter isreceived, theparitycheckcircuitswillcheckthat theparity iscorrectornot.Iftheresultoftheparitycheckisnotcorrect, theparityerrorrequestflag,PARF,willbesetto1.Otherwise,thePARFbitwillremainatzero.

CCCR RegisterTheCCCRregistercontainsthecontrolbitsoftheSmartCardinterfacepins.Furtherexplanationoneachbitisgivenbelow:

Bit 7 6 5 4 3 2 1 0Name CLKSEL — CC8 CC CIO CCLK CRST CVCCR/W R/W — R/W R/W R/W R/W R/W R/WPOR 0 — x x x 0 x 0

"x": unknownBit7 CLKSEL:SmartCardClockselection

0:ThecontentoftheCCLKbitispresentontheexternalCCLKpin1:TheclockoutputontheexternalCCLKpincomesfromthefCCLKclock

ThisbitisusedtoselectwhichclocksourceispresentontheexternalCCLKpin.Itissetandclearedbyapplicationprogram.It isrecommendedthattoactivatetheclockataknownlevelacertainvalueshouldbeprogrammedintotheCCLKbitbeforetheCLKSELbitisswitchedfrom1to0.FordetailedfCCLKselections,refertotheMISC0registerinthisdatasheet.

Bit6 Unimplemented,readas″0″Bit5 CC8:CC8pincontrol

0:ThestatusoftheexternalCC8pinis01:ThestatusoftheexternalCC8pinis1

Thebit issetandclearedbyapplicationprogramtocontrol theexternalCC8pinstatus.ThevaluewrittenintothisbitwillbepresentontheexternalCC8pin.ReadingthisbitwillreturnthestatuspresentontheCC8pin.

Bit4 CC4:CC4pincontrol0:ThestatusoftheexternalCC4pinis01:ThestatusoftheexternalCC4pinis1

Thebit issetandclearedbyapplicationprogramtocontrol theexternalCC4pinstatus.ThevaluewrittenintothisbitwillbepresentontheexternalCC4pin.ReadingthisbitwillreturnthestatuspresentontheCC4pin.

Rev. 1.10 1 ne 0 01 Rev. 1.10 13 ne 0 01



Bit3 CIO:CIOpincontrol0:ThestatusoftheexternalCIOpinis01:TheexternalCIOpinremainsatanopendraincondition

ThisbitisavailableonlyiftheUMODbitintheCCRregisterisclearedto0(Manualmode).It issetandclearedbyapplicationprogramtocontrol theexternalCIOpinstatusinManualmode.ReadingthisbitwillreturnthestatuspresentontheCIOpin.ApullhighresistorcanbeconnectedtotheCIOpindeterminedbyaconfigurationoption.

Bit2 CCLK:CCLKpincontrol0:ThestatusoftheexternalCCLKpinis01:ThestatusoftheexternalCCLKpinis1

ThisbitisavailableonlyiftheUMODbitintheCCRregisterisclearedto0(Manualmode).ThebitissetandclearedbyapplicationprogramtocontroltheexternalCCLKpinstatusinManualmode.ReadingthisbitwillreturnthecurrentvalueintheregisterinsteadofthestatuspresentontheCCLKpin.

Bit1 CRST:CRSTpincontrol0:ThestatusoftheexternalCRSTpinis01:ThestatusoftheexternalCRSTpinis1

Thisbit issetandclearedbyapplicationprogramtocontrol theexternalCRSTpinstatus tobeused toreset theexternalSmartCard.Readingthisbitwill return thepresentstatusoftheCRSTpin.

Bit0 CVCC:SmartCardInterfaceCircuitryenablecontrol0:Smartcardinterfacecircuitryisdisabled1:Smartcardinterfacecircuitryisenabled.

ThisbitissetandclearedbyapplicationprogramtocontroltheSmartcardinterfacemoduleisswitchedonoroffwhentheexternalCardispresent.IftheexternalCardisnotpresenton theCDETpin, thisbit isnotavailable tocontrol theSmartcardinterfacecircuitryandwillautomaticallybeclearedto0byhardware.

Rev. 1.10 1 ne 0 01 Rev. 1.10 13 ne 0 01



MISC0 Register

Bit 7 6 5 4 3 2 1 0Name CRDCKS1 CRDCKS0 SMF SMCEN INT1S1 INT1S0 INT0S1 INT0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 CRDCKS1~CRDCKS0:SmartCardinterfaceclocksourcefCRDdividedratioselectionDescribedinthetablebelow.

Bit5 SMF:SmartCardinterfaceandclockoutputfrequencyfCCLKselectionDescribedinthetablebelow.

Bit4 SMCEN:SmartCardinterfaceclockcontrol0:fCCLKisdisabled1:fCCLKisenabled

ThisbitisusedtocontroltheSmartCardinterfaceclocksource.Ifthisbitisclearedtodisabletheclock,therelevantregistersintheSmartCardinterfacemodulecannotbeaccessed.WhentheSmartCardinterfaceclockisdisabled,ithasnoeffectontheCardinsertionorremovaldetections.

Bit3~2 INT1S1~INT1S0:ExternalInterrupt1activeedgeselectionDescribedelsewhere.

Bit1~0 INT0S1~INT0S0:ExternalInterrupt0activeedgeselectionDescribedelsewhere.

SMF CRDCKS1 CRDCKS0 fCCLK

0 0 0 fM/0 0 1 fM/30 1 0 fM/10 1 1 fM/1 0 0 fM/1 0 1 fM/61 1 0 fM/1 1 1 fM/8

Rev. 1.10 1 ne 0 01 Rev. 1.10 15 ne 0 01



CETU RegistersTheCETUregisters,CETU1andCETU0,containthespecificvaluesdeterminedbytheformuladescribedintheETUsection.ItalsoincludesacontrolbitoftheCompensationfunctionfortheETUtimegranularity.NotethatthevalueoftheETUmustbeintherangeof001Hto7FFH.ToobtainthemaximumETUdecimalvalueof2048,a000HvalueshouldbewrittenintotheETU10~ETU0bits.Furtherexplanationoneachbitisgivenbelow:

• CETU1 Register

Bit 7 6 5 4 3 2 1 0Name COMP — — — — ETU10 ETU9 ETU8R/W R/W — — — — R/W R/W R/WPOR 0 — — — — 0 0 1

Bit7 COMP:Compensationfunctionenablecontrol0:Compensationfunctionisdisabled1:Compensationfunctionisenabled

Thisbit issetandclearedbyapplicationprogramusedtocontrol theCompensationfunction.TheCompensationfunctionhasbeendescribedandmoredetailscanbeobtainedintheETUsection.

Bit6~3 Unimplemented,readas″0″Bit2~0 ETU10~ETU8:bit10~8oftheETUvalue

ThebitsaresetandclearedbyapplicationprogramtomodifytheETUvalues.WritingtotheCETU1registerwillreloadtheupdatedvalueintotheETUcounter.

• CETU0 Register

Bit 7 6 5 4 3 2 1 0Name ETU7 ETU6 ETU5 ETU ETU3 ETU ETU1 ETU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 1 1 0 1 0 0

Bit7~0 ETU7~ETU0:bit7~0oftheETUvalueThebitsaresetandclearedbyapplicationprogramtomodifytheETUvalues.

Rev. 1.10 1 ne 0 01 Rev. 1.10 15 ne 0 01



CGT RegistersTheCGTregistersnamedCGT1andCGT0store thespecificGTCvaluesobtained from theAnswer-to-Resetpacketdescribedin theGTCsection.Note that theGTCvaluesmustbein therangefrom00CHto1FFH.Furtherexplanationoneachbitisgivenbelow:

• CGT1 Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — — GT8R/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas″0″Bit0 GT8:bit8oftheGTCvalue

• CGT0 Register

Bit 7 6 5 4 3 2 1 0Name GT7 GT6 GT5 GT GT3 GT GT1 GT0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 1 1 0 0

Bit7~0 GT7~GT0:bit7~0oftheGTCvalueThebitsGT8~GT0aresetandclearedbyapplicationprogramtomodifytheGTCvalues.TheupdatedGTCvaluewillbeloadedintotheGTCcounterattheendofthecurrentguardtimeperiod.

CWT RegistersTheCWTregisters,CWT2,CWT1andCWT0,store thespecificWTCvalueobtainedfromtheAnswer-to-Resetpacketdescribedin theWTCsection.Note that theWTCvaluemustbein therangefrom0x002580Hto0xFFFFFFH.

• CWT2 Register

Bit 7 6 5 4 3 2 1 0Name WT3 WT WT1 WT0 WT19 WT18 WT17 WT16R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 WT23~WT16:bit23~16ofthevalue

• CWT1 Register

Bit 7 6 5 4 3 2 1 0Name WT15 WT1 WT13 WT1 WT11 WT10 WT9 WT8R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 1 0 0 1 0 1

Bit7~0 WT15~WT8:bit15~8oftheWTCvalue

• CWT0 Register

Bit 7 6 5 4 3 2 1 0Name WT7 WT6 WT5 WT WT3 WT WT1 WT0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 0 0 0 0 0 0 0

Bit7~0 WT7~WT0:bit7~0oftheWTCvalueThebitsWT23~WT0aresetandclearedbyapplicationprogramtomodifytheWTCvalues.Thereloadconditionsof theupdatedWTCvaluearedescribedintheWTCsection.UserscanrefertotheWTCsectionformoredetails.

Rev. 1.10 16 ne 0 01 Rev. 1.10 17 ne 0 01



CIER RegisterTheCIERregistercontains the interruptenablecontrolbitsforallof the interruptevents in theSmartCardinterface.Furtherexplanationoneachbitisgivenbelow:

Bit 7 6 5 4 3 2 1 0Name TXBEE — IOVFE VCE WTE TXCE RXCE PARER/W R/W — R/W R/W R/W R/W R/W R/WPOR 0 — 0 0 0 0 0 0

Bit7 TXBEE:TransmitBufferEmptyinterruptenablecontrol0:Disable1:Enable

ThisbitissetandclearedbyapplicationprogramusedtocontroltheTransmitBufferEmptyinterrupt. If thisbit isset to1, theTransmitBufferEmptyinterruptwillbegeneratedwhentheTransmitBufferisempty.

Bit6 Unimplemented,readas″0″Bit5 IOVFE:CardCurrentOverloadinterruptenablecontrol

0:Disable1:Enable

Thisbit issetandclearedbyapplicationprogramand isused tocontrol theCardCurrentOverloadinterrupt.Ifthisbitissetto1,theCardCurrentOverloadinterruptwillbegeneratedwhentheCardCurrentisoverloaded.

Bit4 VCE:CardVoltageErrorinterruptenablecontrol0:Disable1:Enable

Thisbit issetandclearedbyapplicationprogramand isused tocontrol theCardVoltageErrorinterrupt.Ifthisbitissetto1,theCardVoltageErrorinterruptwillbegeneratedwhentheCardVoltageisnotinthespecifiedrange.

Bit3 WTE:WaitingTimeCounterUnderflowinterruptenablecontrol0:Disable1:Enable

ThisbitissetandclearedbyapplicationprogramandisusedtocontroltheWaitingTimeCounterUnderflowinterrupt.If thisbit isset to1, theWaitingTimeCounterUnderflowinterruptwillbegeneratedwhentheWTCunderflows.

Bit2 TXCE:CharacterTransmissionCompletioninterruptenablecontrol0:Disable1:Enable

ThisbitissetandclearedbyapplicationprogramandisusedtocontroltheCharacterTransmissionCompletioninterrupt.Ifthisbitissetto1,theCharacterTransmissionCompletioninterruptwillbegeneratedattheendofthecharactertransmission.

Bit1 RXCE:CharacterReceptionCompletioninterruptenablecontrol0:Disable1:Enable

ThisbitissetandclearedbyapplicationprogramandisusedtocontroltheCharacterReceptionCompletion interrupt. If thisbit is set to1, theCharacterReceptionCompletioninterruptwillbegeneratedattheendofthecharacterreception.

Bit0 PARE:ParityErrorinterruptenablecontrol0:Disable1:Enable

Thisbit issetandclearedbyapplicationprogramandisusedtocontrol theParityErrorinterrupt.Ifthisbitissetto1,theParityErrorinterruptwillbegeneratedwhenaparityerroroccurs.

Rev. 1.10 16 ne 0 01 Rev. 1.10 17 ne 0 01



CIPR RegisterTheCIPRregistercontainstheinterruptpendingflagsforalloftheinterrupteventsintheSmartCardinterface.Thesependingflagscanbemaskedbythecorrespondinginterruptenablecontrolbits.Furtherexplanationoneachbitisgivenbelow:

Bit 7 6 5 4 3 2 1 0Name TXBEP — IOVFP VCP WTP TXCP RXCP PARPR/W R — R R R R R RPOR 0 — 0 0 0 0 0 0

Bit7 TXBEP:TransmitBufferEmptyinterruptpendingflag0:Nointerruptpending1:Interruptpending

Thisbit issetbyhardwareandclearedbya readaccess to this registerusing theapplicationprogram.ItisusedtoindicateifthereisaTransmitBufferEmptyinterruptpendingornot. If thecorrespondinginterruptenablecontrolbit isset to1andtheTransmitBufferisempty,thisbitwillbesetto1toindicatethattheTransmitBufferEmptyinterruptispending.

Bit6 Unimplemented,readas"0"Bit5 IOVFP:CardCurrentOverloadinterruptpendingflag

0:Nointerruptpending1:Interruptpending

Thisbit issetbyhardwareandclearedbya readaccess to this registerusing theapplicationprogram.ItisusedtoindicateifthereisaCardCurrentOverloadinterruptpendingornot. If thecorrespondinginterruptenablecontrolbit isset to1andtheCardCurrentisoverloaded,thisbitwillbesetto1toindicatethattheCardCurrentOverloadinterruptispending.

Bit4 VCP:CardVoltageErrorinterruptpendingflag0:Nointerruptpending1:Interruptpending

Thisbit issetbyhardwareandclearedbya readaccess to this registerusing theapplicationprogram.It isusedtoindicate if there isaCardVoltageError interruptpendingornot.Ifthecorrespondinginterruptenablecontrolbitissetto1andtheCardVoltageisnotinthespecifiedrange,thisbitwillbesetto1toindicatethattheCardVoltageErrorinterruptispending.

Bit3 WTP:WaitingTimeCounterUnderflowinterruptpendingflag0:Nointerruptpending1:Interruptpending

Thisbit is set byhardware and clearedby a read access to this register usingtheapplicationprogram. It isused to indicate if there isaWaitingTimeCounterUnderflowinterruptpendingornot.Ifthecorrespondinginterruptenablecontrolbitissetto1andtheWTCunderflows,thisbitwillbesetto1toindicatethattheWaitingTimeCounterUnderflowinterruptispending.

Bit2 TXCP:CharacterTransmissionCompletioninterruptpendingflag0:Nointerruptpending1:Interruptpending

Thisbit issetbyhardwareandclearedbya readaccess to this registerusing theapplicationprogram. It isused to indicate if there is aCharacterTransmissionCompletioninterruptpendingornot.Ifthecorrespondinginterruptenablecontrolbitissetto1andacharacterhasbeentransmitted,thisbitwillbesetto1toindicatethattheCharacterTransmissionCompletioninterruptispending.

Rev. 1.10 18 ne 0 01 Rev. 1.10 19 ne 0 01



Bit1 RXCP:CharacterReceptionCompletioninterruptpendingflag0:Nointerruptpending1:Interruptpending

Thisbit issetbyhardwareandclearedbya readaccess to this registerusing theapplicationprogram.ItisusedtoindicateifthereisaCharacterReceptionCompletioninterruptpendingornot.If thecorrespondinginterruptenablecontrolbit isset to1andacharacterhasbeenreceived,thisbitwillbesetto1toindicatethattheCharacterReceptionCompletioninterruptispending.

Bit0 PARP:ParityErrorinterruptpendingflag0:Nointerruptpending1:Interruptpending

Thisbit issetbyhardwareandclearedbya readaccess to this registerusing theapplicationprogram.ItisusedtoindicateifthereisaParityErrorinterruptpendingornot.Ifthecorrespondinginterruptenablecontrolbitissetto1andtheparityerroroccurs,thisbitwillbesetto1toindicatethattheParityErrorinterruptispending.

CTXB RegisterTheCTXBregisterisusedtostorethedatatobetransmitted.

Bit 7 6 5 4 3 2 1 0Name TB7 TB6 TB5 TB TB3 TB TB1 TB0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 TB7~TB0:databits7~0tobetransmitted

CRXB RegisterTheCRXBregisterisusedtostorethereceiveddata.Asthecharacterhasbeenreceivedcompletely,thevalueinCRXBregistershouldbereadtoavoidthenextcharacterbeingoverwritten.

Bit 7 6 5 4 3 2 1 0Name RB7 RB6 RB5 RB RB3 RB RB1 RB0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 RB7~RB0:bits7~0ofthereceiveddata

Rev. 1.10 18 ne 0 01 Rev. 1.10 19 ne 0 01



Configuration OptionsConfigurationoptionsrefertocertainoptionswithintheMCUthatareprogrammedintothedeviceduringtheprogrammingprocess.Duringthedevelopmentprocess,theseoptionsareselectedusingtheHT-IDEsoftwaredevelopmenttools.Astheseoptionsareprogrammedintothedeviceusingthehardwareprogrammingtools,oncetheyareselectedtheycannotbechangedlaterastheapplicationsoftwarehasnocontrolover theconfigurationoptions.Alloptionsmustbedefinedforpropersystemfunction,thedetailsofwhichareshowninthetable.

No. OptionsOscillator Options

1High speed System oscillator selection - fM External XTAL oscillator (HXT), External RC oscillator (ERC), Internal RC oscillator (HIRC) or External Oscillator (EC)

External oscillator (EC) clock filter control: enable or disable3 Internal RC oscillator (HIRC) frequency selection: 4MHz, 8MHz or 12MHz

Low speed System oscillator selection - fSL External 32.768kHz XTAL oscillator (LXT) or Internal 32kHz RC oscillator (LIRC)

5 Oscillator selection for fSUB External 32.768kHz XTAL oscillator (LXT) or Internal 32kHz RC oscillator (LIRC)

6 WDT Clock selection for fS fSUB or fSYS/

Watchdog Options7 Watchdog Timer fnction: enable or disable8 CLRWDT instrctions: 1 or instrctions9 WDT time-ot period: 1/fS 13/fS 1/fS or 15/fS

Time Base Option10 Time base time-ot period selection: 1/fS 13/fS 1/fS or 15/fS

Buzzer Options11 I/O or Buzzer output selection: PA0, PA1; BZ, PA1 or BZ, BZ1 Buzzer output frequency selection: fS/ fS/3 fS/ fS/5 fS/6 fS/7 fS/8 or fS/9

PFD Options13 I/O or PFD otpt selection: PC1 or PFD1 PFD source selection: PFD0 (from Timer/event counter 0) or PFD1 (from Timer/event counter 1)

RES Pin Option15 I/O or RES pin selection: PC7 or RES

LVD/LVR Options16 LVD fnction: enable or disable17 LVR fnction: enable or disable18 LVR/LVD voltage: .1V/.V or 3.15V/3.3V or .V/.V

Smart Card Interface Options19 CDET pin pll high fnction: enable or disable0 CIO pin pll high fnction: enable or disable1 Waiting Time Counter (WTC) function: enable or disable Character transfer repetition times selection: times or 5 times

Rev. 1.10 150 ne 0 01 Rev. 1.10 151 ne 0 01



No. OptionsSIM Option

3 Serial Interface Module 0 (SIM0) function: enable or disable SPI0 WCOL bit fnction: enable or disable5 SPI0 CSEN bit fnction: enable or disable6 IC0 clock debonce time selection: Disable 1 system clock or system clocks7 Serial Interface Module 1 (SIM1) function: enable or disable8 SPI1 WCOL bit fnction: enable or disable9 SPI1 CSEN bit fnction: enable or disable30 IC1 clock debonce time selection: disable 1 system clock or system clocks

Application Circuits

Note:"*"RecommendedcomponentforaddedESDprotection."**"Recommendedcomponentinenvironmentswherepowerlinenoiseissignificant.

Rev. 1.10 150 ne 0 01 Rev. 1.10 151 ne 0 01



Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe“CLRPCL”or“MOVPCL,A”.Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

Rev. 1.10 15 ne 0 01 Rev. 1.10 153 ne 0 01



Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction“RET”inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe“SET[m].i”or“CLR[m].i”instructionsrespectively.Thefeatureremovestheneedforprogrammerstofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe“HALT”instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

Rev. 1.10 15 ne 0 01 Rev. 1.10 153 ne 0 01



Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticADD A,[m] Add Data Memory to ACC 1 Z C AC OVADDM A,[m] Add ACC to Data Memory 1Note Z C AC OVADD Ax Add immediate data to ACC 1 Z C AC OVADC A,[m] Add Data Memory to ACC with Carry 1 Z C AC OVADCM A,[m] Add ACC to Data memory with Carry 1Note Z C AC OVSUB Ax Sbtract immediate data from the ACC 1 Z C AC OVSUB A,[m] Sbtract Data Memory from ACC 1 Z C AC OVSUBM A,[m] Sbtract Data Memory from ACC with reslt in Data Memory 1Note Z C AC OVSBC A,[m] Sbtract Data Memory from ACC with Carry 1 Z C AC OVSBCM A,[m] Sbtract Data Memory from ACC with Carry reslt in Data Memory 1Note Z C AC OVDAA [m] Decimal adjst ACC for Addition with reslt in Data Memory 1Note CLogic OperationAND A,[m] Logical AND Data Memory to ACC 1 ZOR A,[m] Logical OR Data Memory to ACC 1 ZXOR A,[m] Logical XOR Data Memory to ACC 1 ZANDM A,[m] Logical AND ACC to Data Memory 1Note ZORM A,[m] Logical OR ACC to Data Memory 1Note ZXORM A,[m] Logical XOR ACC to Data Memory 1Note ZAND Ax Logical AND immediate Data to ACC 1 ZOR Ax Logical OR immediate Data to ACC 1 ZXOR A,x Logical XOR immediate Data to ACC 1 ZCPL [m] Complement Data Memory 1Note ZCPLA [m] Complement Data Memory with reslt in ACC 1 ZIncrement & DecrementINCA [m] Increment Data Memory with reslt in ACC 1 ZINC [m] Increment Data Memory 1Note ZDECA [m] Decrement Data Memory with reslt in ACC 1 ZDEC [m] Decrement Data Memory 1Note ZRotateRRA [m] Rotate Data Memory right with reslt in ACC 1 NoneRR [m] Rotate Data Memory right 1Note NoneRRCA [m] Rotate Data Memory right throgh Carry with reslt in ACC 1 CRRC [m] Rotate Data Memory right throgh Carry 1Note CRLA [m] Rotate Data Memory left with reslt in ACC 1 NoneRL [m] Rotate Data Memory left 1Note NoneRLCA [m] Rotate Data Memory left throgh Carry with reslt in ACC 1 CRLC [m] Rotate Data Memory left throgh Carry 1Note C

Rev. 1.10 15 ne 0 01 Rev. 1.10 155 ne 0 01



Mnemonic Description Cycles Flag AffectedData MoveMOV A,[m] Move Data Memory to ACC 1 NoneMOV [m],A Move ACC to Data Memory 1Note NoneMOV Ax Move immediate data to ACC 1 NoneBit OperationCLR [m].i Clear bit of Data Memory 1Note NoneSET [m].i Set bit of Data Memory 1Note NoneBranch OperationMP addr mp nconditionally NoneSZ [m] Skip if Data Memory is zero 1Note NoneSZA [m] Skip if Data Memory is zero with data movement to ACC 1Note NoneSZ [m].i Skip if bit i of Data Memory is zero 1Note NoneSNZ [m].i Skip if bit i of Data Memory is not zero 1Note NoneSIZ [m] Skip if increment Data Memory is zero 1Note NoneSDZ [m] Skip if decrement Data Memory is zero 1Note NoneSIZA [m] Skip if increment Data Memory is zero with result in ACC 1Note NoneSDZA [m] Skip if decrement Data Memory is zero with result in ACC 1Note NoneCALL addr Sbrotine call NoneRET Retrn from sbrotine NoneRET Ax Retrn from sbrotine and load immediate data to ACC NoneRETI Retrn from interrpt NoneTable Read OperationTABRD [m] Read table (specific page) to TBLH and Data Memory Note NoneTABRDC [m] Read table (current page) to TBLH and Data Memory Note NoneTABRDL [m] Read table (last page) to TBLH and Data Memory Note NoneMiscellaneousNOP No operation 1 NoneCLR [m] Clear Data Memory 1Note NoneSET [m] Set Data Memory 1Note NoneCLR WDT Clear Watchdog Timer 1 TO PDFCLR WDT1 Pre-clear Watchdog Timer 1 TO PDFCLR WDT Pre-clear Watchdog Timer 1 TO PDFSWAP [m] Swap nibbles of Data Memory 1Note NoneSWAPA [m] Swap nibbles of Data Memory with reslt in ACC 1 NoneHALT Enter power down mode 1 TO PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.For the“CLRWDT1”and“CLRWDT2”instructionstheTOandPDFflagsmaybeaffectedbytheexecution status.TheTOandPDFflagsareclearedafterboth“CLRWDT1”and“CLRWDT2”instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

Rev. 1.10 15 ne 0 01 Rev. 1.10 155 ne 0 01



Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

Rev. 1.10 156 ne 0 01 Rev. 1.10 157 ne 0 01



CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

Rev. 1.10 156 ne 0 01 Rev. 1.10 157 ne 0 01



CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

Rev. 1.10 158 ne 0 01 Rev. 1.10 159 ne 0 01



JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

Rev. 1.10 158 ne 0 01 Rev. 1.10 159 ne 0 01



RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

Rev. 1.10 160 ne 0 01 Rev. 1.10 161 ne 0 01



RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

Rev. 1.10 160 ne 0 01 Rev. 1.10 161 ne 0 01



SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C

Rev. 1.10 16 ne 0 01 Rev. 1.10 163 ne 0 01



SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

Rev. 1.10 16 ne 0 01 Rev. 1.10 163 ne 0 01



TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

Rev. 1.10 16 ne 0 01 Rev. 1.10 165 ne 0 01



Package Information

Note that thepackage informationprovidedhere is for consultationpurposesonly.As thisinformationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsiteforthelatestversionofthePackage/CartonInformation.

Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.

• PackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)

• TheOperationInstructionofPackingMaterials

• Cartoninformation

http://www.holtek.com/en

http://www.holtek.com/en/package_carton_information

Rev. 1.10 16 ne 0 01 Rev. 1.10 165 ne 0 01



28-pin SSOP (150mil) Outline Dimensions

SymbolDimensions in inch

Min. Nom. Max.A — 0.36 BSC —B — 0.15 BSC —C 0.008 — 0.01 C’ — 0.390 BSC —D — — 0.069 E — 0.05 BSC —F 0.00 — 0.010 G 0.016 — 0.050 H 0.00 — 0.010α 0° — 8°

SymbolDimensions in mm

Min. Nom. Max.A — 6.0 BSC —B — 3.9 BSC —C 0.0 — 0.30 C’ — 9.9 BSC —D — — 1.75 E — 0.635 BSC —F 0.10 — 0.5 G 0.1 — 1.7 H 0.10 — 0.5 α 0° — 8°

Rev. 1.10 166 ne 0 01 Rev. 1.10 167 ne 0 01



44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions

SymbolDimensions in inch

Min. Nom. Max.A — 0.7 BSC —B — 0.39 BSC —C — 0.7 BSC —D — 0.39 BSC —E — 0.03 BSC —F 0.01 0.015 0.018G 0.053 0.055 0.057H — — 0.063I 0.00 — 0.006 0.018 0.0 0.030K 0.00 — 0.008α 0° — 7°

SymbolDimensions in mm

Min. Nom. Max.A — 1.00 BSC —B — 10.00 BSC —C — 1.00 BSC —D — 10.00 BSC —E — 0.80 BSC —F 0.30 0.37 0.5G 1.35 1.0 1.5H — — 1.60I 0.05 — 0.15 0.5 0.60 0.75K 0.09 — 0.0α 0° — 7°

Rev. 1.10 166 ne 0 01 Rev. 1.10 167 ne 0 01



Copyright© 2014 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accrate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that sch applications will be sitable withot frther modification nor recommends the se of its prodcts for application that may present a risk to hman life de to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit or web site at http://www.holtek.com.tw.

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