FPGA Vission1

Made by:Bhinjan DalwadiParth ParikhGhanshyam ZambareGuided by:Prof. Chintan S. Patel

BIRLA VISHWAKARMA MAHAVIDYALAY ENGINEERING COLLEGE

ELECTRONICS DEPARTMENT

Edge Detection Algorithms▪First Order Derivative Edge Detection Algorithms▪Sobel▪Canny▪Prewitt▪Roberts▪Second Order Derivative Edge Detection Algorithms▪Difference of Gaussian (DoG)▪Laplacian Of Gaussian (LoG)

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Why FPGA ?▪Fast image processing compared to CPU, GPU and DSP processor.▪Scalable to SoC.▪Cheaper and Rapid Development than ASIC.

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Source: Study and Comparison of Various Image Edge Detection Techniques

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Image Gradient▪Gradient of a digital image data is directional change in the pixel (or

colour) intensity. i.e. Differentiation of Pixel Intensity w.r.t. Distance

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Sobel Derivatives

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-1 0 1

-2 0 2

-1 0 1

-1 -2 -1

0 0 0

1 2 1

Gx=

Gy=

|𝐺|=√𝐺𝑥2+𝐺𝑦

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Sobel Derivative Algorithm On Image

Original Gradient EdgeOriginal Image Source: World Wild Life Org.

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Sobel Top Module

clk

rst

rdy

Pixel(8 bit) Grad_out(17 bit)

Sobel Top Module

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Structural Block Diagram

Block ROM input image Line Buffer

Sobel Operators

Block RAMoutput image VGA-Display

Sobel Top Module

Gradient

VGA Timing

Implementation hierarchy

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Block memory IP Core Configurations

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▪Block ROM/RAM▪Features:

• Low latency memory controller• Separate read and write channel interfaces to utilize dual port FPGA BRAM

technology• Configurable BRAM data width (8-, 32-, 64-, 128-, 256-, 512-, and 1024-bit)

(equals AXI slave port data width size)• Supports memory sizes up to a maximum of 2 MBytes (byte size 8 or 9)• Performance up to 450 MHz• Data widths from 1 to 4096 bits• Memory depths from 2 to 128k

VGA Interface▪Signals▪Hsync▪0-Tracing line is completed▪1-otherwise

▪Vsync▪0- when frame is changed▪1- otherwise

▪R-G-B▪Analog Input▪0-1v Range▪1-for Brightest▪0-for Darkest

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VGA Process Flow

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In_clk pixel_clk VGA Timing VGA Display

BRAM

System clkClock generator

Output_image

VGA Controller▪Fetches data from the Block RAM forwarded to the VGA port.▪Generates Hsync and Vsync pulses for synchronization.▪Pixel Clock is generated using LogiCORE IP Clock Generator (v4.03a)

Resolution (pixels)

Refresh Rate (Hz)

Pixel Clock (MHz)

Horizontal (pixel clocks) Vertical (rows)

Display Front Porch

Sync Pulse

Back Porch

Display Front Porch

Sync Pulse

Back Porch

640x48060 25.175 640 16 96 48 480 10 2 33

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Simulation Result

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Simulation Result

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Resource utilization report(nexys4 xc7a100tcsg324-1)

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Conclusion▪Implemented Sobel edge detection technique on FPGA.▪Simulated the hardware with VHDL test bench.▪Processing speed is 400 FPS for 500x500 Gray scale image. ▪Displayed processed image on screen through VGA interface. Image pixel

data stored in block ram which was displayed.▪Simulated Sobel edge detection technique using OpenCV and Python on

CPU.

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Future Work▪Add modules for further image processing.▪Implementing a switch for displaying both input image(original) and output

image(edge detected).

▪Make a complete SoC.▪Use Xilinx Zynq APSoC to make heterogeneous embedded system for image

processing.▪Use hardwired Dual core ARM Cortex A9 processor (PS block) of Xilinx ZYNQ

XC7Z010-1CLG400C with Linux for process controlling▪Create AXI (AMBA Standard) peripheral of the Sobel module

▪Enhance performance speed by over clocking.

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Reference▪R. Maini and D. H. Aggarwal, “Study and Comparison of Various Image

Edge Detection Techniques” International Journal of Image Processing http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.301.927&rep=rep1&type=pdf▪Shuichi Asano, Tsutomu Maruyama and Yoshiki Yamaguchi “Performance

comparison of FPGA, GPU and CPU in image processing, IEEE http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5272532▪S. Larson, “VGA Controller (VHDL) – Logic –eewiki” https://

eewiki.net/pages/viewpage.action?pageId=15925278• Xilinx DS512 LogicCORE IP Block Memory Generator v6.1, Data Sheet

www.xilinx.com>blk_mem_gen_ds512

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