*Silicon on Insulator (SOI) Based Devices Part 2Amitava DasGuptaDepartment of Electrical EngineeringI.I.T. MadrasChennai 600037adg@ee.iitm.ac.in

*Short channel effect (SCE) in SOICharge sharing due to source and drain is less in FD SOI

*Threshold Voltage variation FDSOI vs. Bulk (and PDSOI)

*SCE due to fringing fields in the BOXElectric field in the BOX due to S/D depletion charge tends to terminate in the silicon film rather than substrateThis induces inversion charge at the back surface and degrades subthreshold characteristics

*Fringing Fields in SOI Possible solutionsThinning of BOX But this results inIncrease in effective body capacitance and subthreshold slope Increase in source drain junction capacitance(Solution Use Silicon-on-Nothing (SON) ?)

*Dynamic Threshold MOSFETWhen device is ON (VGS is high)When VGS = VDD, For higher current drive (higher speed), VTh should be lowWhen device is OFF (VGS is low)

When VGS = 0,For low leakage current (low static power dissipation), VTh should be high

VTh should reduce with increase in VGS

*Dynamic Threshold MOSFET (PD SOI)Achieved by tying Gate and Body

Since VSB = -VGS

With increase in VGS, VTh reduces

Disadvantage : VGS cannot exceed 0.6V

*Dynamic Threshold MOSFET (FD SOI)As VGS increases, VTh reducesAdvantage over PDSOI : VGS is not limited to 0.6VDisadvantage : Substrate is common to all devices in chip So special scheme for isolation of substrate is necessary

*Why Double Gate (DG) MOSFETs?Short channel effects (SCE) in MOSFETs are due to field penetration from drain to sourceDue to SCE, gate has less control of channel, resulting inLower VTh (Threshold Voltage)Higher S (Subthreshold swing)To reduce SCE, the channel doping conc. (NA) has to be increased

*Why Double Gate (DG) MOSFETs? (contd.)For gate length (L) of 50nm, required NA is above 1018/cm3ProblemsFor NA > 1018/cm3, carrier mobility is very lowWhen L = 10 nm, channel volume ~ 10-18 cm3 , resulting in severe VTh variations due to random fluctuation of dopant atomsSolution Use DG MOSFETIt does not require channel doping for SCE controlA second gate and a fully depleted silicon film enhances the control of gateThe SOI film is undoped or lightly doped to ensure full depletionFor better SCE control, both gate oxide thicknesses (tox) are equally small and VG1 = VG2

*Subthreshold Swing in DG MOSFETSFor long channel devicesEffect of S/D can be ignoredSince SOI film is fully depleted and mobile charge conc. is negligible in subthreshold region, there is one-to-one correspondence between VG and channel potentialFor short channel devicesEffect of S/D cannot be ignoredTo suppress SCE, electrical distance of the channel centre to the gates must be much smaller than half the channel length

*Threshold Voltage of DG MOSFETSSince the silicon film is undoped it is virtually equipotential across the thickness results in volume inversionPopular definition of VTh (surface potential equal to 2B) cannot be usedAlternate definition :Gate voltage when inversion charge density reaches a particular value (QTh)QTh = 3.24 1010 /cm2 Poissons equation:

*Threshold Voltage of DG MOSFETS (contd.) VTh for long channel devices depends on the metal and silicon thicknessThreshold voltage shift reduces for smaller silicon thickness

*Logic Circuit using DG MOSFETsSeparate gate biasing in DG device provides variable threshold voltageIndependent front and back gate bias reduces the number of transistors for implementing logic functions

NANDPMOS turns ON when any input is LOWNORNMOS turns ON when any input is HIGHM. Chiang, et al, Novel high-density low-power logic circuit techniques using DG devices, IEEE Trans. Electron Devices, vol. 52, pp. 2339-2342, Oct. 2005

*Scaling LimitsCriterionS = 70 mV / decade (excellent)S = 100 mV / decade (moderate)VTh < 100VIf L changes by 30% due to process variation, VTh should change by less than 7% of supply voltageResults assuming tsi = 3 nm (onset of quantization effects) and tox = 0.9 nm (limited by direct tunneling) L can be reduced to 7 nm for S = 100 mV / decade L can be reduced to 12 nm for S = 70 mV / decadeApplying VTh < 100V, L can be reduced to 12 nm Applying process variation condition, L can be reduced to only 16 nm

*Ultra Thin DG SOI MOSFETCarrier confinement in very narrow potential wells is governed by the wave functions and energy levels of the various subbands.Self consistent solution of Schrdinger and Poissons equation is now necessary to calculate carrier concentrationsThe striking feature obtained by this solution is that most of the carriers flow through the middle of the film, and not at the interfaces

*Ultra Thin DG SOI MOSFETInteresting resultThe transconductance of DG SOI is more than double SG SOIWhy ?Most of carriers in DGSOI flow through the middle of the film, where the carrier mobility is much higher than at the interfaces

*Gate leakage current in DGSOISince the carrier concentration peak is away from the interface, gate leakage current in Ultra-thin DGSOI is less than bulk MOSFETSThis advantage is more pronounced for high-K dielectricsThis allows the use of thinner gate dielectrics leading to more aggressive scaling

*Multiple Gate SOI MOSFETsIncreasing the number of gates increases gate control and reduces SCE and subthreshold slopeThe Pi-gate has the advantages of quadruple gate, but is much easier to fabricateSingle GateDouble GateTriple GateQuadruple GatePi-GatePi-Gate Fabrication stepsJ.T. Park and J.P. Colinge, Multiple-Gate SOI MOSFETs: Device design guidelines, IEEE Trans. Electron Devices, vol. 49, pp. 2222-2228, Dec. 2002

*Special Triple Gate Device - FINFETRelatively simple processEffective channel width (W) = 2 x Hfin + TfinW can be increased by having multiple fins Devices with L = 18 nm and tox = 2.5 nm have been demonstratedEmpirical scaling rule to suppress SCE L > 3Tfin

*Double Gate MOSUltra thin body Double Gate MOSFinFETConventional SOI MOSEvolution of FinFET

*Double Gate MOSUltra thin body Double Gate MOSFinFETConventional SOI MOSEvolution of FinFET

*Double Gate MOSUltra thin body Double Gate MOSFinFETConventional SOI MOSEvolution of FinFET

*Double Gate MOSUltra thin body Double Gate MOSFinFETConventional SOI MOSEvolution of FinFET

*Double Gate MOSUltra thin body Double Gate MOSFinFET (Double or Triple Gate)Conventional SOI MOSEvolution of FinFETBOX

*SummarySOI MOS devices have several inherent advantages over conventional bulk MOS devicesTill recently, development of SOI CMOS was hampered by the non-availability of good quality SOI wafers. Modern techniques have improved the quality of these wafersPD SOI are similar to Bulk SOI. However, absence of substrate contact results in Floating Body EffectsFD SOI devices with Ultra thin Body (UTB) have several advantages over PD SOI/Bulk MOSFETsFD SOI devices have evolved into Multiple Gate FETs (MuGFETs) , which may be devices of futureThere is lot of scope of modelling these devices

Thank you*