Confidential Intento Design. Copyrights reserved 2015-2019
SOI Silicon Valley Symposium
ID-XploreTM: A disruptive EDA for emerging FDSOI applications
Dr. Ramy ISKANDER, CEOemail: [email protected]
9th April 2019: California, San Jose
Confidential Intento Design. Copyrights reserved 2015-2019
Presentation Outline
➢ Story of Intento Design
➢ Context Definition
➢ Calibration using dynamic body biasing
➢ Testbenches Configuration
➢ ID-Xplore™: Migration from FDSOI 28nm to 22FDX
➢ Performances Achieved
➢ Summary
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Our story
2012
Declared Patents through research work
Launched European FP7 project AUTOMICS
2013
Received a public fund to develop the first proof-of -concept
2014
Won a national competition for emerging technologies
2015
Incorporated Intento Design
Raised a fund from public and private investors (SEVENTURE and FOREIS)
Hired 7 employees
2016
Released the first version of ID-XploreTM
Got First client for ID-XploreTM
Won national research funds
2017 and beyond
2nd Round Fundraising in January 2017 to expand Sales & Support
ID-XploreTM patent granted WW
ID-SusbtrateTM patent acquired by Intento and protected WW
Second Release of ID-XploreTM
in Dec 2017
First strategic partnership with major foundry
Staff = 16 including 10 PhDs
2008
Ramy became an Associate Professor at Université Pierre et Marie Curie in Paris (UPMC)
2018 and Beyond
Boosting Commercialization and internationalization
First Steps for SCALE-UP
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Our Mission
Intento Design creates cognitive software for First-Time Right Analog Design.
Our mission is to create software that analog engineers love to use.
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“We’ve already seen the benefits of ID-Xplore in accelerating the design phase of different analogcircuits, thanks to the software’s fast and accurate exploration capabilities in advanced FD-SOIprocesses“, says Thierry Bion, Hardware Design Director, Aerospace Defense & Legacy Division,STMicroelectronics. “By facilitating IP reuse and sharing of design insights between engineers, ID-Xplore™ is helping our teams significantly accelerate new product introductions.”
FDXcelerator Partner
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Context Definition
✓ FD-SOI has the potential to deliver effective cost/performance alternatives to FinFET.
✓ FD-SOI raised the design complexity of finding appropriate design solutions. PVT → PVT+B
✓ ID-Xplore™:
❑ Migrates between technology processes seamlessly including FDSOI
❑ Determining the appropriate static and dynamic body biasing ranges to meet PVTB
❑ is fully integrated into Cadence Environment
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Output clock skew mismatch in 2-Channels Time-Interleaved ADC
Objectives:
1. Migrate the clock buffer to 22FDX FDSOI technology
2. Calibrate output clock skew mismatch using dynamic body biasing
Reference design:
Clock buffer of a 2-channels Time-Interleaved ADC in 28nm FDSOI with 1V1 supply.
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Calibration using body biasing
Skew mismatch is a physical limitation.
In such situation, dynamic body biasing is of high interest.
𝜇 − 𝑇𝑠𝑘𝑒𝑤,𝑏𝑏_𝑚𝑖𝑛 ≤ 3𝜎 ≤ 𝜇 + 𝑇𝑠𝑘𝑒𝑤,𝑏𝑏_𝑚𝑎𝑥
The dynamic body biasing range should cover the whole Skew mismatch range, i.e.
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Propagation delay control
Body biasing knob varies the threshold voltage and
the propagation delay of the inverter gate
𝑉𝑏𝑏,𝑛 𝑉𝑏𝑏,𝑝𝐺𝑁𝐷 𝑉𝐷𝐷
𝑉𝑏𝑏,𝑚𝑖𝑛 𝑉𝑏𝑏,𝑚𝑎𝑥
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Calibration loop
The calibration procedure compensates skew mismatch after fabrication:
1. Characterization: measure real skew mismatch
Time to analog conversion (e.g. phase detector + Charge Pump + filter).
2. Calibration: apply differential body biasing in buffers to adjust their delays
The body biasing calibration range should cover the real skew mismatch.
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Testbench for characterizing dynamic calibration range
Output buffers are typically sized using ID-Xplore™ taking into account:
Period#1: to determine
Testbench applies two body biasing conditions to measure skew:
Period#2: to determine μ= 𝑇𝑠𝑘𝑒𝑤,𝑏𝑏_𝑚𝑖𝑛
Period#3:
𝑉𝑏𝑏,𝑛 = 𝑉𝑏𝑏,𝑝 =𝑉𝑏𝑏,𝑚𝑖𝑛 + 𝑉𝑏𝑏,𝑚𝑎𝑥
2𝜇 = 𝑇𝑠𝑘𝑒𝑤,𝑡𝑦𝑝
𝑇𝑠𝑘𝑒𝑤,𝑏𝑏_𝑚𝑖𝑛, 𝑇𝑠𝑘𝑒𝑤,𝑏𝑏_𝑚𝑎𝑥
𝑉𝑏𝑏,𝑛 = 𝑉𝑏𝑏,𝑚𝑎𝑥 & 𝑉𝑏𝑏,𝑝 = 𝑉𝑏𝑏,𝑚𝑖𝑛
𝑉𝑏𝑏,𝑛 = 𝑉𝑏𝑏,𝑚𝑖𝑛 & 𝑉𝑏𝑏,𝑝 = 𝑉𝑏𝑏,𝑚𝑎𝑥 to determine μ= 𝑇𝑠𝑘𝑒𝑤,𝑏𝑏_𝑚𝑎𝑥
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Skew mismatch distribution modeled using Monte Carlo
transient simulation with 128 samples
Testbench for characterizing skew mismatch distribution
(μ-3σ) μ (μ+3σ)25/04/2019 12
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Specifications Setup
5 DC specs
10 TRAN specs
2 MC TRAN specs
3 TRAN specs
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Design Space Exploration in 22FDX
1. Eight valid designs satisfying all specifications are identified.
2. One design ‘global 0’ is selected and backannotated in OA DB.
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Cross-Referencing between Parameter and Performance Spaces
Tradeoffs Inspection in N-Dimensional Viewer
Parameter
SpacePerformance Space
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The following tradeoffs are displayed:
1. Active Area vs skew standard deviation
Conclusion: they have nonlinear inversed relation
2. Power consumption vs skew standard deviation
Conclusion: they have nonlinear inversed relation
Tradeoffs Inspection in N-Dimensional Viewer
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Front-End Signoff
After backannotating, ADE Assembler simulations fully agree with
ID-Xplore reported performances
Therefore, the design ‘global 0’ is CORRECT-BY-CONSTRUCTION
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Corner Validation in ADE-Assembler
Some specifications below are verified against temperature corner changing from -40°C to 105°C
We conclude that the design is robust w.r.t temperature variations.
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Eight Successful Designs Achieved
Performance Specs Reference1
(28nm)
Design [1]
(22FDX)
Design [2]
(22FDX)
Design [3]
(22FDX)
Mean skew μ (ps) 125±0.125 125.06 125.18 125.02 124.99
StdDev σ (ps)
[3σ]
< 0.8
[2.4]
0.55
[1.65]
0.56
[1.68]
0.71
[2.13]
0.76
[2.28]
Tuning range (ps) > ±2.4 ±0.4 ±2.9 ±3 ±3.8
Power (mW) < 10 5 3.8 3.4 3.5
1 Reference design: calibration range does not cover ±3σ real skew mismatch
Performance Design [4]
(22FDX)
Design [5]
(22FDX)
Design [6]
(22FDX)
Design [7]
(22FDX)
Design [8]
(22FDX)
Mean skew μ (ps) 124.99 124.96 125.041 125.066 125.063
StdDev σ (ps)
[3σ]
0.71
[2.13]
0.76
[2.28]
0.65
[1.95]
0.6
[1.8]
0.63
[1.89]
Tuning range (ps) ±2.95 ±3.86 ±2.98 ±3.08 ±3.03
Power (mW) 3.57 3.72 3.67 3.86 3.75
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✓ ID-Xplore significantly accelerates design and migration toward FDSOI technologies.
✓ Multiple correct-by-construction FDSOI designs are produced.
✓ ID-Xplore efficiently helps handles static and dynamic body biasing techniques.
✓ The Multi-dimensional inspection capability of ID-Xplore gives full insight over the
explored design space.
✓ Total time spent to generate 8 candidates FDSOI designs took less than a day.
Conclusions
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Confidential Intento Design. Copyrights reserved 2015-2019
Thank you for your kind attention.
Ramy ISKANDER, PhD
CEO
INTENTO DESIGN
office : +33 1 42 36 14 59
direct : +33 9 72 63 27 41
FR-cell : +33 6 61 61 21 68
email : [email protected]
mailing : 10 rue de Richelieu, 75001 Paris, FRwebsite : www.intento-design.com
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