119
Solving Problems with Reliability in the Lead-Free Era SMTA ICSR Toronto, Canada May 7, 2011 Cheryl Tulkoff, ASQ CRE DfR Solutions Sr. Member of the Technical Staff
| Date post: | 18-Nov-2014 |
| Category: |
Technology |
| Upload: | cheryl-tulkoff |
| View: | 194 times |
| Download: | 8 times |
Solving Problems with Reliability
in the Lead-Free Era
SMTA ICSR
Toronto, Canada
May 7, 2011
Cheryl Tulkoff, ASQ CRE
DfR Solutions
Sr. Member of the Technical Staff
High Reliability Course Abstract
o This webinar provides a focused but comprehensive
discussion on potential reliability issues that can arise within
Pb-free processes. Areas of potential high risk are
examined. For each reliability concern, a brief description
is provided, followed by the current state of industry
knowledge and an opportunity for risk mitigation based
upon the product design, materials, complexity, volumes,
and customer expectations of reliability. A final summary
provides the attendees a roadmap for ensuring the
reliability of Pb-free product.
Instructor Biography
o Cheryl Tulkoff has over 17 years of experience in electronics manufacturing with an emphasis on failure analysis and reliability. She has worked throughout the electronics manufacturing life cycle beginning with semiconductor fabrication processes, into printed circuit board fabrication and assembly, through functional and reliability testing, and culminating in the analysis and evaluation of field returns. She has also managed no clean and RoHS-compliant conversion programs and has developed and managed comprehensive reliability programs.
o Cheryl earned her Bachelor of Mechanical Engineering degree from Georgia Tech. She is a published author, experienced public speaker and trainer and a Senior member of both ASQ and IEEE. She holds leadership positions in the IEEE Central Texas Chapter, IEEE WIE (Women In Engineering), and IEEE ASTR (Accelerated Stress Testing and Reliability) sections. She chaired the annual IEEE ASTR workshop for four years and is also an ASQ Certified Reliability Engineer.
o She has a strong passion for pre-college STEM (Science, Technology, Engineering, and Math) outreach and volunteers with several organizations that specialize in encouraging pre-college students to pursue careers in these fields.
Agenda o Quick Refresher:
o SAC background & alternative alloys
o Why did SAC305 become the standard LF alloy?
o Part I: The Current State of Lead Free
o Components
o Suppliers
o Concerns
o Robustness
o Temperature Sensitivity
o Moisture Sensitivity
o Drivers
o Components of specific interest
o PCBs
o Surface Finishes: Focus on Pb-free HASL
o Laminate Cracking & Delamination
o PTH Barrel Cracking & CAF (Conductive Anodic Filament)
o Pad Cratering
o Electro-Chemical Migration (ECM)
o Solders
o Discussion of 2nd gen alloys
o Intermetallic formation
o Copper Dissolution
o Mixed Assembly
o Wave and Rework
o LF Solder Fountain
o Hole Fill Challenges
o Part II: Reliability Results
o Shock/Drop Test Results
o SAC vs SnPb
o Results of alternative alloys
o Vibration Results
o Thermal Cycling
o SAC vs SnPb
o Results of alternative alloys
o Will there be one winner?
o Fatigue (Shock & Vibration)
o Microstructural Stability
o HALT/HASS
o Conclusions
Quick Refresher
o Why did SAC305 become the standard LF alloy?
o Readily available
o Reasonable melting temp
o Had the least reliability issues compared to other options
SAC was never considered an ideal replacement for eutectic SnPb, it was
simply the best choice at the time
Sn Bi
Ag
Zn
Acceptable wetting
And high strength High Melting Point
217C Strength
Weakness
Melting point is
almost the same as SnPb
Easily oxidizes, corro-
sion cracking, voids,
poor wetting
Mixing with Pb degrades
strength and fatigue
resistance
(silver)
(bismuth) (zinc) (tin)
Good wetting and
high strength
In Inadequate source
of supply & corrosion
(indium)
+ Cu
SnAgCu
became the
industry
accepted Pb-
free alloy
Lead-free Alloy Summary
Module 1:
Components Component Robustness
8
Robustness - Components
Concerns
Potential for latent defects after exposure to Pb-free reflow temperatures
215°C - 220°C peak → 240°C - 260°C peak
Drivers
Initial observations of deformed or damaged components
Failure of component manufacturers to update specifications
Components of particular interest
Aluminum electrolytic capacitors
Ceramic chip capacitors
Surface mount connectors
Specialty components (RF, optoelectronic, etc.)
9
Component Robustness: Electrolytic Capacitors
V-Chip is an adaptation of electrolytic capacitors to surface
mount technology specifically designed to handle the high
temperatures. Can they withstand the higher temperatures
associated with Pb-free reflow?
Thru-hole electrolytic capacitors are not
suitable for SMT and are not designed
to handle reflow temperatures
10
Electrolytic Capacitors (cont.)
Surface mount electrolytic
capacitors (V-chip package)
Liquid electrolyte exposed to reflow and
rework temperatures
Driven by a change in
environments
Increase reflow/rework
temperatures
Can result in case distortion
and loss of seal
When does this mechanism occur?
How to differentiate this mechanism from other
degradation behavior?
NIC
DfR
B. Willis, SMART Group
11
Pb-Free Reflow Compatibility
0
100
200
300
400
500
600
700
800
1 10 100 1000 10000
Volume (mm3)
Tim
e t
o D
efo
rma
tio
n (
se
co
nd
s)
0
100
200
300
400
500
600
700
800
1 10 100 1000 10000
Volume (mm3)
Tim
e t
o d
efo
rma
tio
n (
se
co
nd
s)
235°C 260°C
At 235°C: 1 „failure‟ before peak temperature; 2 failures before 45 seconds
At 260°C: 1 failure after 5 seconds at peak; 7 failures before 45 seconds
Greatest risk
Small (10-100 mm3 volume) and large (>1000 mm3) components
12
V-Chip Capacitors: Reflow Profiling
o Temperature profiling during SnPb Reflow
o Large ball grid array (BGA)
o 16x18 V-chip (3600 mm3)
o Peak temperature of large can V-chip approximately 25°C to 30°C colder than BGA
o Interior solder joint under a BGA is often the coolest location on |the assembly
o The BGA solder joint must reach 240-245ºC for Pb-free reflow
o Suggests V-chip housing will likely see a worst-case temperature of 210-220ºC PCB: 16" x 17", 18 layer (100 mil)
V-Chip and Peak Reflow
o Some capacitor manufacturers have differentiated
peak temperature based on case size for V-chip
capacitors
o Larger capacitors can withstand higher peak temperatures
o Panasonic
o 8mm to 10mm diameter: +240°C to +250°C
o 12.5mm and larger diameter: +245°C to +255°C
www.arrowne.com/innov/in188/f_943.shtml (Panasonic)
14
Long-Term Reliability
o Accelerated life testing after exposure to various Pb-free reflow conditions
o 235ºC / 30 seconds
o 245ºC / 30 seconds
o 260ºC / 30 seconds
o Reflow profile had no effect on lifetime
o Indication of low risk of latent defects
o One deformed capacitor even showed nominal life
0.1
1
10
100
1000
10000
0 5 10 15 20 25 30 35 40 45
Time under Test at 165C (days)N
orm
alized
ES
R
Small (4 x 5) Medium (6.3 x 8)
Large (12.5 x 14)
Electrolytic Capacitors: Summary
o Primary electrolytic capacitor failure mode during Pb-free transition?
o Overheating during rework of microprocessor
o Drivers
o Electrolytic capacitors adjacent to the microprocessor
o Through-hole electrolytic capacitors have lower boiling point than surface-mount electrolytic capacitors
o Poorly controlled rework conditions (rework temps can reach 300C for over 5 seconds)
o Example of off-line processes being a critical source of failures
16
Ceramic Capacitors (Thermal Shock Cracks)
Due to excessive change in temperature
Reflow, cleaning, wave solder, rework
Inability of capacitor to relieve stresses during
transient conditions.
Maximum tensile stress occurs near end of
termination
Determined through transient thermal analyses
Model results validated through sectioning of
ceramic capacitors
exposed to thermal shock
conditions
Three manifestations
Visually detectable (rare)
Electrically detectable
Microcrack (worst-case)
NAMICS
AVX
17
Thermal Shock Crack: Visually Detectable
AVX
18
Thermal Shock Crack: Micro Crack
Variations in voltage or temperature will drive crack propagation
Induces a different failure mode
Increase in electrical resistance or decrease capacitance
DfR
19
Corrective Actions: Manufacturing
Solder reflow
Room temperature to preheat (max 2-3oC/sec)
Preheat to at least 150oC
Preheat to maximum temperature (max 4-5oC/sec)
Cooling (max 2-3oC/sec)
In conflict with profile from J-STD-020C (6oC/sec)
Make sure assembly is less than 60oC before cleaning
Wave soldering
Maintain belt speeds to a maximum of 1.2 to 1.5 meters/minute
Touch up
Eliminate
20
Corrective Actions: Design
Orient terminations parallel to wave solder
Avoid certain dimensions and materials (wave soldering)
Maximum case size for SnPb: 1210
Maximum case size for SAC305: 0805
Maximum thickness: 1.2 mm
C0G, X7R preferred
Adequate spacing from hand soldering operations
Use manufacturer‟s recommended bond pad dimensions or smaller (wave soldering)
Smaller bond pads reduce rate of thermal transfer
21
Is This a Thermal Shock Crack? No!
Cracking parallel to the electrodes is due to stack-up or sintering processes during capacitor manufacturing
These defects can not be detected using in-circuit (ICT) or functional test
Requires scanning acoustic microscopy (SAM)
With poor adhesion, maximum stress shifts away from the termination to the defect site
No correlation between failure rate and cooling rates (0.5 to 15ºC/sec)
22
Flex Cracking of Ceramic Capacitors
Excessive flexure of PCB under ceramic chip capacitor can induce cracking at the terminations
23
Flex Cracking of Ceramic Capacitors (cont.)
Excessive flexure of PCB under ceramic chip capacitor can induce cracking at the terminations
Pb-free more resistant to flex cracking
Correlates with Kemet results (CARTS 2005)
Rationale
Smaller solder joints
Residual compressive stresses
Influence of bond pad
Action Items
None
SnPb
SnAgCu
Summary
o Risk areas o Small volume V-chip electrolytic capacitors
o Through hole electrolyic capacitors near large BGAs
o Ceramic capacitors wave soldered or touched up
o Actions o Spec and confirm
o Peak reflow temperature requirements for SMT electrolytics (consider elimination if volume < 100mm3)
o Time at 300°C for through-hole electrolytics
o Initiate visual inspection of all SMT electrolytic capacitors (no risk of latency if no bulging or other damage observed)
o Ban touch up of ceramic capacitors (rework OK)
Module 2:
Components Temperature Sensitivity
Moisture Sensitivity
Peak Temperature Ratings
o Aka, „Temperature Sensitivity Level‟ (TSL)
o Some component manufacturers are not
certifying their components to a peak temperature of
260ºC
o 260ºC is industry default for „worst-case‟ peak
Pb-free reflow temperature
o Why lower than 260ºC?
o Industry specification
o Technology/Packaging limitation
26
Industry Specification (J-STD-020)
o Package size
o Number of component manufacturers rely on table and reflow profile suggested in J-STD-020C
o Larger package size, lower peak temperature
o Issues as to specifying dwell time
o J-STD-020C: Within 5ºC of 260ºC for 20-40 seconds
o Manufacturers: At 260ºC for 5-10 seconds
27
J-STD-020D.1 Reflow Profile (Update)
o Specification of peak package body temperature (Tp)
o Users must not exceed Tp
o Suppliers must be equal
to or exceed Tp
o Not yet widely adopted
28
TSL + MSL Example
o Peak temperature rating is 245C
o Problem, right?
o Not exactly
o Thickness > 2.5mm, Volume > 350mm3
o Peak temp specified by J-STD-020 is 245C
o Higher reflow temperature possible
o May require DOE / increase in MSL
29
TSL + MSL (cont.)
o Intel intends to comply with J-Std-020 MSL
requirements, which establishes the peak temperature
rating and MSL by package size
http://www.intel.com/technology/silicon/leadfree.htm
30
TSL + MSL (example – cont.)
o NEC has two soldering conditions
o IR50: 250C peak temperature
o IR60: 260C peak temperature
o Four packages (not parts) identified as IR50
o 208pinQFP(FP): 28 x 28 x 3.2
o 240pinQFP(FP): 32 x 32 x 3.2
o 304pinQFP(FP): 40 x 40 x 3.7
o 449pinPBGA: 27 x 27 x 1.7
o Peak temperatures could be 245C and still meet J-STD-020 requirements
o Suggests characterization separate from J-STD-020 may have been performed
31
32
TSL (cont.)
Limited examples of technology and package limitations
Surface mount connectors (primarily overcome)
RF devices (already sensitive to SnPb reflow)
Opto-electronic (LEDs, opto- isolators, etc.)
Examples Amphenol: “Amphenol connectors containing LEDs must NOT be processed
using Lead-free infra-red reflow soldering using JEDEC-020C (or similar) profiles”
Micron / Aptina: “Some Pb-free CMOS imaging products are limited to 235°C MAX peak temperature”
http://www.amphenolcanada.com/ProductSearch/GeneralInfo/Disclaimer%20for%20Connectors%20containing%20LEDs.htm
B. Willis, SMART Group
http://download.micron.com/pdf/technotes/tn_00_15.pdf
Moisture Sensitivity Level (MSL)
o Popcorning controlled through moisture sensitivity levels (MSL)
o Defined by IPC/JEDEC documents J-STD-020D.1 and J-STD-033B
o Higher profile in the industry due to transition to Pb-free and more aggressive packaging
o Higher die/package ratios
o Multiple die (i.e., stacked die)
o Larger components
33
MSL: Typical Issues and Action Items
o Identify your maximum MSL
o Driven by contract manufacturer (CM) capability and OEM risk aversion
o Majority limit between MSL3 and MSL4 (survey of the MSD Council of SMTA, 2004)
o High volume, low mix: tends towards MSL4 Low volume, high mix: tends towards MSL3
o Not all datasheets list MSL
o Can be buried in reference or quality documents
o Ensure that listed MSL conforms to latest version of J-STD-020
Cogiscan
34
MSL Issues and Actions (cont.)
o Most „standard‟ components have a
maximum MSL 3
o Components with MSL 4 and higher
o Large ball grid array (BGA) packages
o Encapsulated magnetic components (chokes,
transformers, etc.)
o Optical components (transmitters,
transceivers, sensors, etc.)
o Modules (DC-DC converters, GPS, etc.)
o MSL classification scheme in J-STD-020D is
only relevant to SMT packages with
integrated circuits
o Does not cover passives (IPC-9503) or wave
soldering (JESD22A111)
o If not defined by component manufacturer,
requires additional characterization
35
Aluminum and Tantalum Polymer Capacitors
Aluminum Polymer Capacitor
Tantalum Polymer Capacitor
36
Popcorning in Tantalum/Polymer Capacitors
o Pb-free reflow is hotter
o Increased susceptibility to popcorning
o Tantalum/polymer capacitors are the primary risk
o Approach to labeling can be inconsistent
o Aluminum Polymer are rated MSL 3 (SnPb)
o Tantalum Polymer are stored in moisture proof bags (no MSL rating)
o Approach to Tantalum is inconsistent (some packaged with dessicant; some not)
o Material issues
o Aluminum Polymer are rated MSL 3 for eutectic (could be higher for Pb-free)
o Sensitive conductive-polymer technology may prevent extensive changes
o Solutions
o Confirm Pb-free MSL on incoming plastic encapsulated capacitors (PECs)
o More rigorous inspection of PECs during initial build
37
Summary: Module 2
o Know when peak temperature indicates true temperature sensitivity
o Component manufacturer‟s peak temperature ratings deviate from J-STD-020
o Peak temperature ratings are very specific or nuanced in some fashion
o Ask component manufacturer for data confirming issues at temperatures below 260C
o Consider requiring MSL on the BOM for certain component packaging and technologies
o Focus on polymeric and large tantalum capacitors
Module 3:
Printed Circuit Boards –
Surface Finishes
Pb-Free Hot Air Solder Level
(HASL)
Solderability Plating: Pb-Free HASL
o Increasing Pb-free solderability plating of choice
o Primary material is Ni-modified SnCu (SN100CL)
o Initial installations of SAC being replaced
o Only Vicor recently identified as using SAC HASL (Electronic Design, Nov 2007)
o Co-modified SnCu also being offered (claim of 80 installations [Metallic Resources])
o Selection driven by
o Storage
o Reliability
o Solderability
o Planarity
o Copper Dissolution
Pb-Free HASL: Ni-modified SnCu
o Patented by Nihon Superior in March 1998
o Claimed: Sn / 0.1-2.0% Cu / 0.002-1% Ni / 0-1% Ge
o Actual: Sn / 0.7% Cu / 0.05% Ni / 0.006% Ge
o Role of constituents
o Cu creates a eutectic alloy with lower melt temp (227C vs.
232C), forms intermetallics for strength, and reduces copper
dissolution
o Ni suppresses formation of b-Sn dendrites, controls
intermetallic growth, grain refiner
o Ge prevents oxide formation (dross inhibitor), grain refiner
Note: Current debate if Sn0.9Cu or Sn0.7Cu is eutectic
Pb-free HASL: Storage
o PCBs with SnPb HASL have storage times of 1 to 4
years
o Driven by intermetallic growth and oxide formation
o SN100CL demonstrates similar behavior
o Intermetallic growth is suppressed through Ni-addition
o Oxide formation process is dominated by Sn element (similar
to SnPb)
o Limited storage times for alternative Pb-free platings
(OSP, Immersion Tin, Immersion Silver)
Pb-Free HASL: Intermetallic Growth
HASL and Flow: A Lead-Free Alternative, T. Lentz, et. al., Circuitree, Feb 2008,
http://www.circuitree.com/Articles/Feature_Article/BNP_GUID_9-5-2006_A_10000000000000243033
SN100C (150C for 1000 hrs)
SnPb (150C for 1000 hrs)
o Similar intermetallic thickness as SnPb after long-term aging and multiple reflows
Pb-Free HASL: Reliability
o Contract manufacturers (CMs) and OEMs have
reported issues with electrochemistry-based
solderability platings
o ENIG: Black Pad, Solder Embrittlement
o ImAg: Sulfur Corrosion, Microvoiding
o Some OEMs have moved to OSP and Pb-free HASL
due to their „simpler‟ processes
Pb-Free HASL: Solderability
o Industry adage: Nothing solders like solder
http://www.daleba.co.uk/download%20section%20-%20lead%20free.pdf
HASL and Flow: A Lead-Free Alternative, T. Lentz, et. al., Circuitree, Feb 2008,
http://www.circuitree.com/Articles/Feature_Article/BNP_GUID_9-5-2006_A_10000000000000243033
Discussions with CMs and OEMs seem to indicate satisfaction with Pb-free HASL performance Additional independent, quantitative data should be gathered
Improved solderability could improve hole fill
46
Pb-Free HASL: Planarity
Recommended minimum thickness
100 min (4 microns)
Lower minimums can result in exposed intermetallic
Primary issue is thickness variability
Greatest variation is among different pad designs
100 min over small pads (BGA bond pads); over 1000 min over large pads
Can be controlled through air knife pressure, pot temperatures, and nickel content
Pb-Free HASL: Planarity (cont.)
o Air knives
o Pb-free HASL requires lower air pressure to blow off excess solder
o Pot Temperatures
o SnPb: 240C to 260C
o SN100CL: 255C to 270C (air knife temp of 280C)
o Ni content
o Variation can influence fluidity
o Minimum levels critical for planarity
o Some miscommunication as to critical concentrations
Sweatman and Nishimura (IPC APEX 2006)
Pb-Free HASL (Composition)
o Minimum Ni concentrations need to be more clearly specified by licensees
o Nihon recommends >300 ppm
o Recommended maximum Cu concentrations range from 0.7 to 1.2wt%
o Increased bridging and graininess
o Nihon recommends <0.9wt%
Florida CirTech, www.floridacirtech.com/Databases/pdfs/SN100CL.pdf AIM Solder, www.advprecision.com/pdf/LF_Soldering_Guide.pdf
Balver Zinn, www.cabelpiu.it/user/File/Schede%20prodotto/schede%20nuove%20SN100CL-SN100CLe.pdf
Pb-Free HASL: Copper Dissolution
o To be discussed in detail in solder module
o Presence of nickel is believed to slow the copper dissolution process
o SAC HASL removes ~5 um
o SNC HASL removes ~1 um
www.p-m-services.co.uk/rohs2007.htm
www.pb-free.org/02_G.Sikorcin.pdf
www.evertiq.com/news/read.do?news=3013&cat=8 (Conny Thomasson, Candor Sweden AB)
Nihon Superior
Pb-Free HASL: Additional Concerns
o Risk of thermal damage, including warpage and influence on long term reliability (PTH fatigue, CAF robustness) o No incidents of cracking / delamination / excessive warpage
reported to DfR to date
o Short exposure time (3 to 5 seconds) and minimal temp. differential (+5ºC above SnPb) may limit this effect
o Compatibility with thick (>0.135”) boards o Limited experimental data (these products are not currently Pb-free)
o Mixing of SNC with SAC o Initial testing indicates no long-term reliability issues (JGPP)
Module 5:
PCB Robustness Overview
Cracking and Delamination
52
Printed Board Robustness
Concerns
Increased Warpage
PTH Cracks
Land
Separation
Solder Mask Discoloration Blistering
Delamination Pad Cratering
53
Printed Board Damage
Predicting printed board damage can be difficult Driven by size (larger boards tend to experience
higher temperatures)
Driven by thickness (thicker boards experience more thermal stress)
Driven by material (lower Tg tends to be more susceptible)
Driven by design (higher density, higher aspect ratios)
Driven by number of reflows
No universally accepted industry model
Printed Board Damage: Industry Response
o Concerns with printed board damage have almost
entirely been addressed through material changes or
process modifications
o Not aware of any OEMs initiating design rules or restrictions
o Specific actions driven by board size and peak
temperature requirements
Industry Response (cont.)
o Small, very thin boards
o Up to 4 x 6 and 62 mil thick
o Peak temperatures as low as 238ºC
o Minimal changes; most already using 150ºC Tg Dicy (tends to be sufficient)
o Medium, thin boards
o Up to 10 x 14 and 75 mil thick
o Tend to have moderate-sized components; limits peak temperatures to 245ºC-248ºC
o Rigorous effort to upgrade laminate materials (dicy-cured may not be feasible)
o Large, thick boards
o Up to 18 x 24 and 180 mil thick
o Difficulty in maintaining peak temperatures below 260ºC
o Very concerned
Rothshild, APEX 2007
56
PCB Robustness: Material Selection Board thickness IR-240~250℃ Board thickness IR-260℃
≤60mil
Tg140 Dicy
All HF materials OK ≤ 60mil
Tg150 Dicy
HF- middle and high Tg materials OK
60~73mil
Tg150 Dicy
NP150, TU622-5
All HF materials OK 60~73mil
Tg170 Dicy
HF –middle and high Tg materials OK
73~93mil
Tg170 Dicy, NP150G-HF
HF –middle and high Tg materials OK 73~93mil
Tg150 Phenolic + Filler
IS400, IT150M, TU722-5, GA150
HF –middle and high Tg materials OK
93~120mil
Tg150 Phenolic + Filler
IS400, IT150M, TU722-5
Tg 150
HF –middle and high Tg materials OK 93~130mil
Phenolic Tg170
IS410, IT180, PLC-FR-370 Turbo, TU722-
7
HF –middle and high Tg materials OK
121~160mil
Phenolic Tg170
IS410, IT180, PLC-FR-370 Turbo
TU722-7
HF –high Tg materials OK ≧131mil
Phenolic Tg170 + Filler
IS415, 370 HR, 370 MOD, N4000-11
HF –high Tg materials OK
≧161mil
PhenolicTg170 + Filler
IS415, 370 HR, 370 MOD, N4000-11
HF material - TBD ≧161mil
TBD – Consult Engineering for specific
design review
1.Copper thickness = 2OZ use material listed on column 260 ℃
2.Copper thickness >= 3OZ use Phenolic base material or High Tg Halogen free materials only
3.Twice lamination product use Phenolic material or High Tg Halogen free materials only (includes HDI)
4.Follow customer requirement if customer has his own material requirement
5.DE people have to confirm the IR reflow Temperature profile J. Beers, Gold Circuits
Printed Board Damage: Prevention
o Thermal properties of laminate material are primarily
defined by four parameters
o Out of plane coefficient of thermal expansion (Z-CTE)
o Glass transition temperature (Tg)
o Time to delamination (T260, T280, T288)
o Temperature of decomposition (Td)
o Each parameter captures a different material behavior
o Higher number slash sheets (> 100) within IPC-4101 define
these parameters to specific material categories
Thermal Parameters of Laminate
o Out of plane CTE (below Tg or Z-axis: 50ºC to 260ºC)
o CTE for SnPb is 50ppm - 90ppm (50C to 260C rarely considered)
o Pb-free: 30ppm - 65ppm or 2.5 – 3.5%
o Glass transition temperature (IPC-TM-650, )
o Characterizes complex material transformation (increase in CTE, decrease in modulus)
o Tg of 110ºC to 170ºC for SnPb
o Pb-free: 150ºC to 190ºC
o Time to delamination (IPC-TM-650, 2.4.24.1)
o Characterizes interfacial adhesion
o T-260 for SnPb is 5-10 minutes
o Pb-free: T-280 of 5-10 minutes or T-288 of 3-6 minutes
o Temperature of decomposition (IPC-TM-650, 2.3.40)
o Characterizes breakdown of epoxy material
o Td of 300ºC for SnPb
o Pb-free: Td of 320ºC
Thermal Parameters (cont.)
o Strong correlation between Td and T288
o Suggests cohesive failure during T288
o May imply poor ability to capture interfacial weaknesses
B. Hoevel, et. al., New epoxy resins for printed wiring board applications, Circuit World, 2007, vol. 33, no. 2
Industry Response: Material Selection
o OEMs are attempting to stay with FR-4 laminate
o Selecting phenolic, filled, higher functionality (higher Tg), CAF-
resistant
o Solutions to multiple issues (thermal robustness, Df/Dk) can
be found in
alternative materials
(BT, PPO) or blends
o Not cost justifiable
at this time
Moises Cases, IBM (PCB / OS Symposium 2007)
PCB Robustness: Material Selection
o The appropriate material selection is driven by the
failure mechanism one is trying to prevent
o Cracking and delamination
o Plated through fatigue
o Conductive anodic filament formation
Delamination / Cracking: Observations
o Morphology and location of the cracking and delamination can vary
o Even within the same board
o Failure morphology and locations
o Within the middle and edge of the PCB
o Within prepregs and/or laminate
o Within the weave, along the weave, or at the copper/epoxy interface (adhesive and cohesive)
Delamination / Cracking: Case Study
o Delamination marked by
red boxes
o Scalloped shape is due to
pinning at the plated
through holes (PTHs)
o Results from acoustic
microscopy confirmed
observations from visual
inspection
o No additional
delamination sites were
identified
A
B
Corner Delamination (cont.)
o Lack of adhesion to glass fibers (yellow outline)
o Could be initiation site
o May suggest wetting issues
Central Delamination
o Delamination appears to
span multiple layers
o Plated through holes pin the
expansion of the
delamination
Additional Observations
o Drivers
o Higher peak temperatures
o Increasing PCB thickness
o Decreasing via-to-via pitch
o Increasing foil thickness (1-oz to 2-oz)
o Presence of internal pads
o Sequential lamination
o Limited information
o Controlled depth drilling
o Extensive debate about root-cause
o Non-optimized process
o Intrinsic limit to PCB capability
o Moisture absorption Rothschild, IPC APEX 2007
Sequential Lamination
Delamination / Cracking: Root-Cause
o Non-Optimized Process
o Some PCB suppliers have demonstrated improvement through modifications to lamination process or oxide chemistry
o Some observations of lot-to-lot variability
o Limit to PCB Capability
o Difficult to overcome adhesion vs. thermal performance tradeoff (dicy vs. phenolic)
o High stresses developed during Pb-free exceed material strength of standard board material
o Moisture Absorption
Cracking and Moisture Absorption o Does moisture play a role?
o No
o DfR found delamination primarily around the edge and away from PTH sites after MSL testing
o IBM found minimal differences after a 24 hr bake of coupons with heavy copper (>2 oz)
o Delamination / cracking observed in board stored for short (<2 weeks) periods of time
o Yes
o DfR customer found improvement after 48 hrs at 125C
o A number of companies now require 5 – 24 hour bake before reflow
o IBM found improvement with coupons with nominal copper
o DfR observed more rapid degradation of boards exposed to moisture, even after multiple reflows
o Some customers specifying maximum moisture absorption
o Where does the moisture come from?
Cracking and Moisture (cont.)
o Storage of prepregs and laminates
o Drilling process
o Moisture is absorbed by the side walls (microcracks?)
o Trapped after plating
o Storage of PCBs at PCB manufacturer
o Storage of PCBs at CCA manufacturer
70
PCB Robustness: Qualifying Printed Boards
o This activity may provide greatest return on investment
o Use appropriate number of reflows or wave
o In-circuit testing (ICT) combined with construction analysis (cracks can be latent defect)
o 6X Solder Float (at 288C) may not be directly applicable
o Note: higher Tg / phenolic is not necessarily better
o Lower adhesion to copper (greater likelihood of delamination)
o Greater risk of drilling issues
o Potential for pad cratering
o Higher reflow and wave solder temperatures may induce solder mask delamination
o Especially for marginal materials and processes
o More aggressive flux formulations may also play a role
o Need to re-emphasize IPC SM-840 qualification procedures
Module 6:
PCB Robustness PTH Barrel Cracking
Conductive Anodic Filaments (CAF)
72
Plated Through Hole (PTH) Fatigue
PTH fatigue is the circumferential
cracking of the copper plating
that forms the PTH wall
It is driven by differential
expansion between the copper
plating (~17 ppm) and the out-of-
plane CTE of the printed board
(~70 ppm)
Industry-accepted
failure model
IPC-TR-579
73
PTH Fatigue: Pb-Free
PTH and Pb-Free (cont.)
o Findings
o Limited Z-axis expansion
and optimized copper
plating prevents
degradation
o Industry response
o Movement to
Tg of 150 - 170C
o Z-axis expansion
between 2.5 to 3.5%
Conductive Anodic Filaments (CAF)
o The migration of copper along a path internal to a
printed circuit board or laminate. Driven by
temperature, humidity, the applied voltage, and the
electric field strength
o CAF can cause current leakage, intermittent electrical
shorts and thermal damage
76
CAF: Examples
A
A A:A Cross-Section
77
CAF: Examples
78
CAF: Examples
79
CAF: Hollow Fibers
Hollow fibers, which form from
decomposed impurities in the
glass melt, are an alternate path
for CAF
80
CAF: Pb-Free Major concern in telecom/server industry
Frequency of events can increase by two orders of magnitude
Time to failure can drop from >750h to 50h
Initially, no “qualified” printed boards
Focus on specific designs
Large (>12x18) / multilayer (>10)
Fine pitch (0.8, 1.0 mm) ball grid arrays (BGAs)
Solutions?
CAF „resistant‟ laminate
Different epoxy formulations
Higher quality weaves
Phenolic cured epoxy (filled)
Can be much better
Sensitive to drilling
Increased price?
Sometimes, not always
Module 7:
PCB Robustness Pad Cratering
Electro-Chemical Migration (ECM)
82
Pad Cratering
Cracking initiating within the laminate during a dynamic mechanical event
In circuit testing (ICT), board depanelization, connector insertion, shock and
vibration, etc.
G. Shade, Intel (2006)
83
Pad Cratering
o Drivers
o Finer pitch components
o More brittle laminates
o Stiffer solders (SAC vs. SnPb)
o Presence of a large heat sink
o Difficult to detect using
standard procedures
o X-ray, dye-n-pry, ball shear, and
ball pull
Intel (2006)
84
Solutions to Pad Cratering
o Board Redesign o Solder mask defined vs. non-solder mask defined
o Limitations on board flexure o 750 to 500 microstrain
o Component dependent
o More compliant solder o SAC305 is relatively rigid
o SAC105 and SNC are possible alternatives
o New acceptance criteria for laminate materials
Laminate Acceptance Criteria
o Intel-led industry effort
o Attempting to characterize laminate material using high-speed
ball pull and shear testing
o Results inconclusive to-date
o Alternative approach
o Require reporting of fracture toughness and elastic modulus
86
Is Pad Cratering a Pb-Free Issue?
Paste Solder BallAverage Fracture
Load (N)Std Dev (N)
SnPb SnPb 692 93
SnPb 656 102
Sn4.0Ag0.5Cu 935 190Sn4.0Ag0.5Cu
35x35mm, 388 I/O BGA; 0.76 mm/min
Roubaud, HP
APEX 2001
87
Electro-Chemical Migration: Overview
o Insidious failure mechanism
o Self-healing: leads to large number of no-trouble-found (NTF)
o Can occur at nominal voltages (5 V) and room conditions (25C, 60%RH)
o Due to the presence of contaminants on the surface of the board
o Strongest drivers are halides (chlorides and bromides)
o Weak organic acids (WOAs) and polyglycols can also lead to drops in the surface insulation resistance
o Primarily controlled through controls on cleanliness
o Minimal differentiation between existing Pb-free solders, SAC and SnCu, and SnPb
o Other Pb-free alloys may be more susceptible (e.g., SnZn)
elapsed time
12 sec.
Cleanliness Recommendations
Ion Control Maximum
Fluoride N/A 1 mg/in2
Chloride 2 mg/in2 4.5 mg/in2
Bromide 10 mg/in2 15 mg/in2
Nitrates, Sulfates 2 – 4 mg/in2 6 – 12 mg/in2
WOAs 150 mg/in2 250 mg/in2
Module 8:
Solders Discussion of 2nd gen alloys (e.g., SN100C)
Intermetallic formation
Divergence in Solder Selection
o Considerations include
o PRICE!
o Insufficient performance
o Newly identified failure mechanisms
o Market still unsteady; proliferation and evolution of material sets
o Solder seeing the fastest increase in market share?
o SnCu+Ni (SNC)
SAC405
SAC305
SAC105
SACX
SNC
SnAg
SNCX
SnCu SnAgCu
??
The Current State of Lead-Free
o Component suppliers
o SAC305 still dominant, but with increasing introduction of low silver alloys (SAC205, SAC105, SAC0507)
o Solder Paste
o SAC305 still dominant
o Wave and Rework
o Sn07Cu+Ni (SN100C)
o Sn07Cu+Co (SN100e)
o Sn07Cu+Ni+Bi (K100LD)
o HASL PCB Coating
o Sn07Cu+Ni (SN100C)
Solder Trends
o SAC305 dominates surface mount reflow (SMT)
o SAC105 increasingly being used in area array components in mobile applications
o SNC pervasive in wave solder and HASL
o Increasing acceptance in Japan for SMT
o Intensive positioning for “X” alloys (SACX, SNCX)
K-W Moon et al, J. Electronic Materials, 29 (2000) 1122-1236
What are Solder Suppliers Promoting? Company Paste Wire / Wave
Senju ECO Solder (SAC305)
Nihon Genma NP303 (SAC305),
NP601 (Sn8Zn3Bi)
NP303 (SAC305),
NP103 (SAC0307)
Metallic Resources SAC305 SAC305,
SC995e (Sn05Cu+Co)
Koki
S3X (SAC305),
S3XNI58 (SAC305+Ni+In),
SB6N58 (Sn3.5Ag0.5Bi6In)
S3X (SAC305),
S03X7C (SAC0307+0.03Co)
Heraeus SAC405
Cookson / Alpha Metals SACX (SAC0307+Bi+0.1P+0.02RareEarth+0.01Sb)
Kester K100LD (Sn07Cu+0.05Ni+Bi)
Qualitek SN100e (Sn07Cu+0.05Co)
Nihon Superior SN100C (Sn07Cu+0.05Ni+Ge)
AIM SN100C (Sn07Cu+0.05Ni+Ge)
Indium Indium5.1AT (SAC305) N/A
Amtech SAC305, Sn3.5Ag, Sn5Ag, Sn07Cu, Sn5Sb
Shenmao SAC305 to SAC405, SAC305+0.06Ni+0.01Ge
Henkel No preference
EFD No preference
P. Kay Metals No preference
94
Intermetallic Basics
o Tin and copper bond to form intermetallics of Cu3Sn and Cu6Sn5
o Irreversible
o Occurs rapidly in the liquid state, but rate still appreciable in solid
state (even at room temperature)
o Total intermetallic thickness after all assembly and rework should be
between 1 to 4 um
o Elements
o Bi is in solid solution in the tin-rich phase or precipitates out (>1%)
o In will form binary intermetallic species with Ag and Cu and ternary
intermetallic species SnAgIn and SnCuIn
o Co seems to display similar behavior to Ni
95
Intermetallic Growth
Cu3Sn Layer
Cu6Sn5 Layer
Cu pad
Solder
Intermetallic Growth (cont.)
Sn3.8Ag0.7Cu / OSP
Yoon, JEM 2004
0 2 4 86 10 120
2
4
6
IMC
Th
ickn
ess (m
m)
t1/2 (hr1/2)
185C
130C, 150C
0 2 4 86 10 120
2
4
6
IMC
Th
ickn
ess (m
m)
t1/2 (hr1/2)
185C
130C, 150C
Sn3.5Cu0.7Cu / ENIG
Lim, ECTC 2003
Pang, JEM 2004
119C
143C
168C
E = 0.51, 0.53 eV Zheng, ECTC 2002
Liao, JEM 2004 E = 0.97 eV
Henshall, APEX 2001
IMC Thickness Model vs Measured Data
)/exp(0 kTEDD
DtZ
A
Fick‟s Law of
Diffusion:
Fitting the
original data set
to the derived
diffusion
coefficient (D0 =
5851) and
activation energy
(EA = 0.556eV/K)
shows strong
correlation 0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0 200 400 600 800 1000 1200
Hours Aged
um
of
IMC
100C
125C
150C
Predicted - 150C
Predicted - 125C
Predicted - 100C
Intermetallic Growth Effects
o Changes in electrical resistance
o Minimal
o Changes in shear strength
o Minimal
o Changes in pull strength
o Minimal
Sn0.5Cu / ENIG
Sn3.8Ag0.7Cu / OSP
Module 9:
Solders Copper Dissolution
Mixed Assembly
100
Solders: Copper Dissolution
The reduction or elimination of surface copper
conductors due to repeated exposure to Sn-based
solders
Significant concern for
industries that perform
extensive rework
Telecom, military,
avionics
Bath, iNEMI
ENIG Plating
60 sec. exposure
274ºC solder fountain
101
Solders: Copper Dissolution (cont.)
o PTH knee is the point of
greatest plating reduction
o Primarily a rework/repair
issue
o Celestica identified significant
risk with >1X rework
o Already having a detrimental
effect
o Major OEM unable to repair
ball grid arrays (BGAs) S. Zweigart, Solectron
Copper Dissolution (Contact Time)
o Contact time is the major driver
o Some indications of a 25-30 second limit
o Preheat and pot temp. seem to have a lesser effect
o Optimum conditions (for SAC)
o Contact time (max): 47 sec. (cumulative)
o Preheat temperature: 140-150°C
o Pot temperature: 260-265°C
A Study of Copper Dissolution During Pb-Free PTH Rework Using a
Thermally Massive Test Vehicle , C. Hamilton (May 2007)
Contact Time (cont.)
o Copper Erosion During Assembly By Lead Free Solder (HDPUG)
104
Solutions to Cu Dissolution
o Option 1: restriction on rework
o Number of reworks or contact time
o Option 2: solder material
o Indications that SNC can decrease dissolution rates
o Reduced diffusion rate through Sn-Ni-Cu intermetallics
o Option 3: board plating
o Some considering ENIG
o Some considering SNC HASL
A Study of Copper Dissolution During Pb-Free PTH Rework Using a
Thermally Massive Test Vehicle , C. Hamilton (May 2007)
105
Dissolution: Copper vs. Nickel
o Nickel (Ni) plating has a dissolution rate approximately
1/10th of copper (Cu) plating
o Given similar solder temperatures and contact times
Albrecht, SMTA 2006 Albrecht, SMTA 2006
106
Mixed Assembly
Primarily refers to Pb-free
BGAs assembled using SnPb
eutectic solder paste
Why?
Area array devices (e.g., ball
grid array, chip scale package)
with eutectic solder balls are
becoming obsolete
Military, avionics,
telecommunications, industrial
do not want to transition to Pb-
free…..yet
UIC
107
SnPb BGAs and the Component Industry
For certain device types, Hi-Rel dominates market share
Mil/Aero is ~10% of Hi-Rel
Hi-Rel products tend to be of higher value
Greater profit for part suppliers
Prismark, iNEMI SnPb-Compatible BGA
Workshop (IPC/APEX 2007)
108
SnPb BGAs – Supplier Response
Result is wide variation in SnPb BGA availability
Driven by market (Micron)
SDR SDRAM preferred by Hi-Rel (low Pb-free penetration)
DDR SDRAM preferred by Computers (high Pb-free penetration), though SnPb available past 2011
Driven by lifecycle (Freescale)
Legacy FC-BGAs are primarily SnPb; new FC-BGAs are primarily Pb-free
iNEMI SnPb-Compatible BGA Workshop
(IPC/APEX 2007)
109
Mixed Assembly: Reflow
Initial studies focused on peak temperature
Identified melt temperature of solder ball as critical parameter
217°C for SAC305
Ensured ball collapse and intermixing
Recommendations
Minimum peak reflow temperature of 220°C
Reflow temperatures below 220°C may result in poor assembly yields and/or inadequate interconnect reliability
For increased margin, >225 to 245°C peak
110
Mixed Assembly: Solder Joint Morphology
Motorola
111
Mixed Assembly: Peak Temp Statements
Cisco Systems: > 210°C
Formation of SnPbAg phase (Tm = 179°C) may allow for lower reflow temperatures
Intel: > 217°C
Infineon: 215 - 230°C
220°C peak used in exceptional circumstances
230°C peak recommended
IBM: 245°C
Minimum time above liquidus (TAL) of 80 seconds
Need to watch for voiding
Talk to your paste supplier
112
Mixed Assembly: Time Above
Liquidus
Effect is inconclusive Kinyanjui, Sanmina-SCI,
iNEMI SnPb-Compatible BGA
Workshop (IPC/APEX 2007)
113
Mixed Assembly: Solder Paste
Volume
Some conflict
Sanmina claims no effect
Celestica claims significant effect
Other factors may play a greater role
Additional investigation necessary Snugovsky, Celestica (2005)
Moderate solder paste volume
Large solder paste volume
Kinyanjui, Sanmina-SCI,
iNEMI SnPb-Compatible BGA
Workshop (IPC/APEX 2007)
114
Mixed Assembly: Effect of Pitch
Intel: reduced self alignment
Degree of difficulty: 0.5mm > 0.8mm > 1 - 1.27mm pitch component
Sanmina: improved mixing
Kinyanjui, Sanmina-SCI,
iNEMI SnPb-Compatible BGA
Workshop (IPC/APEX 2007)
115
Mixed Assembly: Temp Cycling Results
100 1,000 8,00010
0.03
0.3
3
30
99
SnAgCu/SnPb
SnAgCu/SnAgCu
SnPb
Cycles to FailureC
um
ula
tive
Fa
ilu
re (
%)
100 1,000 8,00010
0.03
0.3
3
30
99
SnAgCu/SnPb
SnAgCu/SnAgCu
SnPb
100 1,000 8,00010
0.03
0.3
3
30
99
100 1,000 8,00010
0.03
0.3
3
30
99
SnAgCu/SnPb
SnAgCu/SnAgCu
SnPb
Cycles to FailureC
um
ula
tive
Fa
ilu
re (
%)
HP: 0 to 100ºC, 214ºC Peak Temp
Mixed Assembly (Other)
o iNEMI recently reported issues with low silver (Ag) Pb-
free alloys
o SAC105, SAC0307, etc.
o High pasty range creates voiding and shrinkage cracks
o Mixed assembly with low-silver SAC is not recommended
117
Mixed Assembly: Conclusions
o A potentially lower risk than complete transition to Pb-
free
o Important note: more studies on vibration and shock
performance should be performed
o The preferred approach for some high reliability
manufacturers (military, telecom):
o Acceptance of mixed assembly could be driven by GEIA-STD-
0005-1
118
Mixed Assembly: Alternatives
o Other options on dealing with Pb-free BGAs other than mixing with SnPb
o Placement post-reflow
o Two flux options
o Application of Pb-free solder paste
o Application of flux preform
o Two soldering options
o Hot air (manual)
o Laser soldering (automatic)
