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Some examplesSome examplesSome examplesSome examples
Paolo PRINETTOPolitecnico di Torino (Italy)
University of Illinois at Chicago, IL (USA)
[email protected] [email protected]
www.testgroup.polito.it
Lecture
7.3
2 7.3
Goal
This lecture guides the students through the solution of some simple examples of manual synthesis of sequential networks.
4 7.3
Homework
Students are recommended to try to solve the exercise by themselves, before looking at the proposed solutions.
6 7.3
OutlineOutline
Example #7.3.1: rising edge detector
Example #7.3.2: palindrome string detector
Example #7.3.3: BCD big endian
Example #7.3.4: BCD little endian
Example #7.3.5: parity checker
Example #7.3.6: Ford Thunderbird light controller
Example #7.3.7: code checker
Example #7.3.8: sequence checker
7 7.3
Example #7.3.1: Example #7.3.1: rising edge detectorrising edge detector
A circuit is to be designed, having:
An input X
A clock signal CLK, which acts as a proper sampling signal of X, i.e., the frequency of CLK is such that it never happens that two transitions of X occur within a same CLK cycle
An output U, asserted for a clock cycle whenever a rising edge on the input X is detected.
STT
LL,0,0
H1H1,1,1
reset1
0
1
0
H0H0,0,0
0
1
state encoding
H0 00L 11
H1 10
0 1
H0 00 11 00 0
01 - - 0
L 11 11 10 0
H1 10 11 00 1
y[1:0]
x
Y[1:0] Z
20 7.3
STT
0 1
H0 00 11 00 0
01 - - 0
L 11 11 10 0
H1 10 11 00 1
y[1:0]
x
Y[1:0] ZY[1] = x’ + y[0]
Y[0] = x’
Z = y[1]y[0]’
22 7.3
OutlineOutline
Example #7.3.1: rising edge detector
Example #7.3.2: palindrome string detector
Example #7.3.3: BCD big endian
Example #7.3.4: BCD little endian
Example #7.3.5: parity checker
Example #7.3.6: Ford Thunderbird light controller
Example #7.3.7: code checker
Example #7.3.8: sequence checker
23 7.3
Example #7.3.2: Example #7.3.2: palindrome string detectorpalindrome string detector
On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle.
A circuit to be connected to the serial line is to be designed. It has an output U which is asserted whenever the last 4 values got in input forms a palindrome string.
24 7.3
Example #7.3.2: Example #7.3.2: palindrome string detectorpalindrome string detector
On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle.
A circuit to be connected to the serial line is to be designed. It has an output U which is asserted whenever the last 4 values got in input forms a palindrome string.
Examples:
ANNA – 3993 – 0110
28 7.3
--
00 11
0101 11110000 1010
011011 111111000000 100100
0 1
0 1 0 1
0
0
1
0
0
1
1
1
1 00
1
1 01 0
reset
29 7.3
--
00 11
0101 11110000 1010
011011 111111000000 100100
01100110 1111111100000000 10011001
0 1
0 1 0 1
0
0
1
0
0
1
1
1
1 00
1
1 01 0
0 1
1 01 0
0 1
U=0
U=1
reset
30 7.3
--
00 11
0101 11110000 1010
011011 111111000000 100100
01100110 1111111100000000 10011001
0 1
0 1 0 1
0
0
1
0
0
1
1
1
1 00
1
1 01 0
0 1
1 01 0
0 1
U=0
U=1
reset
31 7.3
OutlineOutline
Example #7.3.1: rising edge detector
Example #7.3.2: palindrome string detector
Example #7.3.3: BCD big endian
Example #7.3.4: BCD little endian
Example #7.3.5: parity checker
Example #7.3.6: Ford Thunderbird light controller
Example #7.3.7: code checker
Example #7.3.8: sequence checker
32 7.3
Example #7.3.3: Example #7.3.3: BCD big endianBCD big endian
On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit groups of 4 bits: each group corresponding to a BCD digit, transmitted MSB first (big endian)
A circuit to be connected to the serial line is to be designed.
It has an output U which is asserted, for 1 clock cycle, in correspondence of the 4th bit of each group, if the group itself is a correct BCD digit.
BCDBCD
33 7.3
Solution
When dealing with circuits that must consider groups of bits, it may be convenient to start from a set of states, one for each possible combination of the PO values.
BCDBCD
40 7.3
Solution
A,0A,0 E,1E,1
B,0B,0 F,0F,0
reset
0 11 0
C,0C,0
D,0D,0 I,0I,0
-
-
H,0H,0-
1
- -
BCDBCD
41 7.3
Solution
A,0A,0 E,1E,1
B,0B,0 F,0F,0
reset
0 1
0
1 0
C,0C,0 G,0G,00
D,0D,0 I,0I,0
-
-
H,0H,0-
1
1
- -
BCDBCD
42 7.3
OutlineOutline
Example #7.3.1: rising edge detector
Example #7.3.2: palindrome string detector
Example #7.3.3: BCD big endian
Example #7.3.4: BCD little endian
Example #7.3.5: parity checker
Example #7.3.6: Ford Thunderbird light controller
Example #7.3.7: code checker
Example #7.3.8: sequence checker
43 7.3
Example #7.3.4: Example #7.3.4: BCD little endianBCD little endian
Similar to the previous exercise, with the only difference that BCD digits are transmitted LSB first.
BCDBCD
44 7.3
Valid Sequences
0000 0 Y0001 8 Y0010 4 Y0011 12 N0100 2 Y0101 10 N0110 6 Y0111 14 N
1000 1 Y1001 9 Y1010 5 Y1011 13 N1100 3 Y1101 11 N1110 7 Y1111 15 N
BCDBCD
46 7.3
OutlineOutline
Example #7.3.1: rising edge detector
Example #7.3.2: palindrome string detector
Example #7.3.3: BCD big endian
Example #7.3.4: BCD little endian
Example #7.3.5: parity checker
Example #7.3.6: Ford Thunderbird light controller
Example #7.3.7: code checker
Example #7.3.8: sequence checker
47 7.3
Example #7.3.5: Example #7.3.5: parity checkerparity checker
On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit strings of 4 bits
A circuit to be connected to the serial line is to be designed.
It has an output Z which is asserted, for 1 clock cycle, in correspondence of the 4th bit of each string, if the string itself contains an odd # of 1’s.
PP44
52 7.3
B,-B,- C,-C,-
D,-D,- E,-E,-
F,-F,- G,-G,-
H,0H,0 I,1I,1
0
0
0
0
0
0
1
1
1
1
1
1
reset
eveneven oddodd
PP44
53 7.3
reset
B,-B,- C,-C,-
D,-D,- E,-E,-
F,-F,- G,-G,-
H,0H,0 I,1I,1
0
0
0
0
0
0
1
1
1
1
1
1
0 101
eveneven oddodd
PP44
54 7.3
OutlineOutline
Example #7.3.1: rising edge detector
Example #7.3.2: palindrome string detector
Example #7.3.3: BCD big endian
Example #7.3.4: BCD little endian
Example #7.3.5: parity checker
Example #7.3.6: Ford Thunderbird light controller
Example #7.3.7: code checker
Example #7.3.8: sequence checker
Example #7.3.6: Example #7.3.6: Ford Thunderbird light Ford Thunderbird light
controllercontroller
A circuit is to be designed to control the back lights of the Ford Thunderbird of 1965.
The car has,on its back, 6 lights,
turned on with different strategies to signal different operations:
Turn left Turn right Break Emergency
64 7.3
The circuit has:
4 inputs:
LEFT & RIGHT asserted when turning left or right, respectively
HAZ asserted to signal an emergency
BRAKE asserted when the driver is braking
6 outputs, one for each light:
Top level
LCLC LBLB LALA RARA RBRB RCRC
65 7.3
Input signals are assigned the following priority:
BRAKE has the highest priority
LEFT & RIGHT have the lowest priority
HAZ has an intermediate priority
Input priorities
66 7.3
Solution
To simplify the design, the BRAKE input can be implemented as follows, and thus not considered any longer in the sequel of the design:
FSMFSM
BRAKE
73 7.3
L3L3
IDLEIDLE
L2L2
L1L1
LR3LR3
LCLC LBLB LALA RARA RBRB RCRC
00
LEFT, RIGHT, HAZLEFT, RIGHT, HAZ
74 7.3
L3L3
IDLEIDLE
L2L2
L1L1
LR3LR3
LCLC LBLB LALA RARA RBRB RCRC
LEFT, RIGHT, HAZLEFT, RIGHT, HAZ
75 7.3
L3L3
IDLEIDLE
L2L2
L1L1
R1R1
LR3LR3
LCLC LBLB LALA RARA RBRB RCRC
010010
LEFT, RIGHT, HAZLEFT, RIGHT, HAZ
76 7.3
L3L3
IDLEIDLE
L2L2
L1L1
R2R2
R1R1
LR3LR3
LCLC LBLB LALA RARA RBRB RCRC
00
LEFT, RIGHT, HAZLEFT, RIGHT, HAZ
77 7.3
L3L3
IDLEIDLE
L2L2
L1L1
R3R3
R2R2
R1R1
LR3LR3
LCLC LBLB LALA RARA RBRB RCRC
00
LEFT, RIGHT, HAZLEFT, RIGHT, HAZ
78 7.3
L3L3
IDLEIDLE
L2L2
L1L1
R3R3
R2R2
R1R1
LR3LR3
LCLC LBLB LALA RARA RBRB RCRC
LEFT, RIGHT, HAZLEFT, RIGHT, HAZ
79 7.3
L3L3
IDLEIDLE
L2L2
L1L1
R3R3
R2R2
R1R1
LR3LR3
LCLC LBLB LALA RARA RBRB RCRC
11
11
LEFT, RIGHT, HAZLEFT, RIGHT, HAZ
80 7.3
L3L3
IDLEIDLE
L2L2
L1L1
R3R3
R2R2
R1R1
LR3LR3
LCLC LBLB LALA RARA RBRB RCRC
11
11
LEFT, RIGHT, HAZLEFT, RIGHT, HAZ
81 7.3
OutlineOutline
Example #7.3.1: rising edge detector
Example #7.3.2: palindrome string detector
Example #7.3.3: BCD big endian
Example #7.3.4: BCD little endian
Example #7.3.5: parity checker
Example #7.3.6: Ford Thunderbird light controller
Example #7.3.7: code checker
Example #7.3.8: sequence checker
82 7.3
Example #7.3.7: Example #7.3.7: code checker code checker
On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit groups of 5 bits. In each group, the first 3 bits are a data and the remaining 2 bits are a code associated to the data to detect transmission errors.
In particular, for each group of bits, the code encodes the number of bits equal to ‘1’ in the data of the same group. Codes are transmitted Most Significant Bit (MSB) first.
3|23|2
83 7.3
Example #7.3.7: code checker (cont’d)
A circuit to be connected to the serial line is to be designed, such that its output OK is asserted for one clock cycle iff, at the completion of a group, no transmission error has been detected.
3|23|2
87 7.3
STG
ko,0
reset
ok,10
#0,0
#0,0 #1,0
0
0
#0,0
#1,0
01
1
1
0
#1,0
1
0
1
#2,0
#2,0
#3,0
1
1 1
1 111
0
3|23|2
data
88 7.3
STG
ko,0
reset
ok,10
#0,0
#0,0 #1,0
0
0
#0,0
#1,0
01
1
1
0
#1,0
1
0
1
#2,0
#2,0
#3,0
1
1 1
A,0 B,0 C,0
1
0
1110 0 0
ok ko okko ko
0
0
1 -1 0code
3|23|2
89 7.3
OutlineOutline
Example #7.3.1: rising edge detector
Example #7.3.2: palindrome string detector
Example #7.3.3: BCD big endian
Example #7.3.4: BCD little endian
Example #7.3.5: parity checker
Example #7.3.6: Ford Thunderbird light controller
Example #7.3.7: code checker
Example #7.3.8: sequence checker
90 7.3
Example #7.3.8: Example #7.3.8: sequence checker sequence checker
On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit sequences of 1’s and sequences of 0’s.
In particular, sequences may have any length, but all the sequences of 1’s must contain an odd # of 1’s, whereas all the sequences of 0’s must contain an even # of 0’s.
A circuit to be connected to the serial line is to be designed, such that its output OK is asserted for one clock cycle whenever a transmission errors has been detected.
oddoddeveneven
91 7.3
Solution hint
Since the # of possible states is limited,
list the whole set of states first
fill up the transitions later
erase the unreachable states (if any)
oddoddeveneven
92 7.3
STG
#0 even, 0
reset
#0 odd, 0 #0 odd, 1
#1 even, 0 #1 odd, 0 #1 odd, 1
#0 even, 1
#1 even, 1
oddoddeveneven
93 7.3
STG
#0 even, 0
reset
#0 odd, 0 #0 odd, 1
#1 even, 0 #1 odd, 0 #1 odd, 1
0
0
0
0
0
0
1
1
1
11
1
#0 even, 1
#1 even, 1
oddoddeveneven
94 7.3
STG
#0 even, 0
reset
#0 odd, 0 #0 odd, 1
#1 even, 0 #1 odd, 0 #1 odd, 1
0
0
0
0
0
0
1
1
1
11
1
#0 even, 1
#1 even, 1
Unreachable states: they can be deleted
oddoddeveneven
95 7.3
STG
#0 even, 0
reset
#0 odd, 0 #0 odd, 1
#1 even, 0 #1 odd, 0 #1 odd, 1
0
0
0
0
0
0
1
1
1
11
1
oddoddeveneven