Charge-Trap NAND Flash MemoryCharge Trap NAND Flash Memory
Souvik Mahapatrap
E E Dept, IIT Bombay, India
C t ib ti S d C P Si h S G t K hitij A l kContributions: Sandya C, Pawan Singh, Suyog Gupta, Kshitij Auluck, Piyush Dak, Sandeep Kasliwal, Udayan Ganguly, Dipankar Saha, Gautam Mukhopadhyay, Juzer Vasi
1Support: Applied Materials, Intel Corporation, SRC/GRC
Outline
FG NAND Flash scaling challenges
SiN based charge trap flash – material dependence
P/E simulation of SiN Flash
Metal nanodot Flash
Scalability simulation of m-ND Flash
2
NAND Flash Background
BL DSL CG
CD 15nm ells
WL
CD 15nm
FG 50nm No.
of c
Figure: SamsungSL SSL
TO 9nm
L=35nm Memory stateSL
•Electron transfer between substrate & FG define memory state (write & erase)state (write & erase)
•FG surrounded by TO & CD acts as electron storage well (non-volatility, need 10yrs), though leak out occurs over time (retention loss)
3•Repeated Write/Erase (10-100K needed) causes memory wear out (cycling endurance)
NAND Flash Scaling•More memory, faster access, reduced cost
•Guideline (ITRS roadmap): L=35nm (2009)
CG
CD 15nm •Guideline (ITRS roadmap): L=35nm (2009), 28nm (2010/11), 22nm (2013/14)…
SLC (1bit/ ll) MLC (2 3 bit / ll) f hi hTO 9nmFG 50nm
•SLC (1bit/cell), MLC (2 or 3 bits/cell) for higher density, higher reliability issuesL=35nm
Scaling penalty:(1) Loss of CG – FG coupling (2) C ll t ll t lk
Solution: Discrete trap-based charge storage
(2) Cell to cell cross talk (3) Non-scaling of TO, FG and CD thickness
CG
CD, 12nmCD thickness (4) Non-scaling of operating voltage TO, 6nm
CD, 12nmSiN, 6nm
4(5) Higher reliability concern
Planer CTF
Devices & test chip demonstrated (Samsung)
•Memory window•Memory window close down with W/E cyclingcycling
•Data keeps leaking out (worse than FG!)out (worse than FG!)
•Loss of memory ti
5operation
CTF reliability worse than FG, no product yet
Retention Issue
Lateral or Vertical charge migrationg g
Trap depth of SiN is key to control charge migration6
Trap depth of SiN is key to control charge migrationSolution – to cut SiN above STI (Samsung, 2007)
NAND 3D Memory
3D CTF proposed as a way to move forward below p p y20nm node: BiCs (Toshiba), TCAT (Samsung)
7
Motivation
CTF reliability improvement needs:y p
Understanding impact of device processing on g p p gmaterial and electrical properties
Proper device design (structure, composition)
Detailed electrical characterization & modeling –feedback for intelligent manufacturingg g
8
SANOS Device Structure
Trap parameters:
ΦEc
Trap parameters:Nt,elec, Φt,elecNt,hole, Φt,hole
Gate
m)
Gate
m)
GateGate
m)12 nm
Φt,elec
Φ
c
Si+ N+
Al2O3
stan
ce (n
m
Si+ N+
Al2O3
stan
ce (n
m
Si+ N+
Al2O3Al2O3
stan
ce (n
m15 nm20 nm
Al2O3
SixNy SiO2
Φt,hole
EvTrap dist
Dis
Si+N+SixNy
Trap dist
Dis
Si+N+
Trap dist
Dis
Si+N+SixNy
3-6 nm6 nm
TOTrap dist.
(A.U.)Channel Trap dist. (A.U.)Channel Trap dist. (A.U.)ChannelChannel
Charge tunnel from substrate to SiN via TO, Al O used for leakage blocking
9
Al2O3 used for leakage blocking
P/E Transients
6
8 P/E at +18V/-18V10
12 P E Total memory window
Refr
R.I.
4
6
(V) N-rich
Si-rich6
8
dow
(V)
ractive Ind
0
2
ΔVFB
Si rich
0
2
4
W11 W2 W3 W6 W8 1 95P/E
Win
d
N1 N2 N3 N4N0
dex (R.I.) N+ Si+
10-8 10-5 10-2 101-4
-2
-4
-2
0 W11 W2 W3 W6 W8
2.152.102.052.001.95
P
10 10 10 10Time (s)
W11 W2 W3 W6 W8
SplitsHigh-k blocking dielectric:
Better coupling to channelLarger memory windows
10P / E state (memory window) depend on SiN composition
ISPP and ISPE
67
N0 56
N0N1N+ N+
456 N1
N2 N3 N4V) 2
34
N1 N2 N3 N4V)
123
V FB(V
101
V FB(VSi+ Si+
10 15 20 25-101
-3-2-1
N+ SiN
10 15 20 25Vg (V) 0 -5 -10 -15 -20 -25
-4
Vg (V)
Higher electron trapping efficiency Poor erase characteristics
Si+ SiN11
Si+ SiNLow P saturation levelsHigher erase efficiency
Charge loss (Retention)
5 0
5.5
0.8
0 4
0.5
E state lossP state loss
N+
4.5
5.0
FB (V
) N1 N2N3 0 4
0.6
0.3
0.4
ΔVFB(V
)
Si+N+
Si+
-1.9-1.8-1.7-1.6
V F N3 N4
0.2
0.4
0.1
0.2
(V)
ΔVFB
SiNN+
102 103 104-2.1-2.0
Time (s)1.95 2.00 2.05 2.10 2.150.0 0.0
0.1
R I
Si+
N+ SiNDeep electron traps - shallow hole traps
Si SiN
Time (s) R.I.
Si+ SiNShallow electron traps - deep hole traps
12P/E state retention dependent on SiN composition
Tunnel oxide thickness dependence
5 5
5.0
5.5
V)
2.5 3/6/12 5/6/12
VFB
(V
2.00.04
4/6/12 6/6/12
VFB= 2.5VV)
1 2 3 4-0.04
0.00FB
ΔV
FB (V
101 102 103 104
Time (s)
13Thinner TO Increased electron tunnel out from SiN
Retention – T dependence
0.0
VFB = 5.5V
1043
-0.4
ΔVFB
(V)
1033
1038
10 N1:Ea = 1.88 eV N2:Ea = 1.38 eV N3:Ea = 1.01 eV
0.0
-0.8
Δ
1023
1028
t r (s)
-0.4
VFB
(V) VFB = 2.5V
8
1013
1018
101 102 103 104-0.8
25oC 125oC 150oC 180oC
ΔV
25 30 35 40103
108
1/kT( V-1)10 10 10 10Time (s)
1/kT(eV 1)
14Higher activation energy in N+ → Deeper electron traps
Retention – E state TO thickness & T effect
0.425oC 125oC
E state retention loss
T independent 0.2
25oC 125oC 150oC 180oC
B(V
)
T independent No thermal emission of holes
0 0
0.2
ΔV
FB
VFB = -2.0V
TO independent for > 3nm
0.40.0
3/6/12 4/6/12 5/6/12 6/6/12)TO independent for > 3nm
No Trap to Band tunneling of holes
0.2
VFB = -2.0V
ΔV
FB(V
)101 102 103 104
0.0
Ti ( )
Δ
Different charge loss mechanisms15
Time (s)Different charge loss mechanismsfor electrons and holes
Endurance – SiN Composition
5
V)
5
3
4
ow, V
FB(V
N1N23
4
V)
2
3
y W
indo
N2 N3 N42
3
N1 N2N3
V FB(V
P 16V 5ms
0
1
Mem
ory N+
0
1 N4P 16V 5msE -15V 1ms
100 101 102 103 1040
P/E Cycles
Si+100 101 102 103 104
0
P/E Cycles
Si rich devices cycle with negligible erase state degradationEndurance degradation SiN composition dependent
16
Si-rich devices cycle with negligible erase state degradation
Summary
• Comparison of SiN Compositions
Parameter N+ Si+
Electron trap depth Deep Shallow
Hole trap depth Shallow DeepHole trap depth Shallow Deep
Hole trap density Very low High
Split window operation
Not possible
Possible
Endurance degradation
High Low
17
P/E Simulation of SiN Flash
D l Si l ti f k bl f idi• Develop a Simulation framework capable of providing useful insight into the physics involved during Program /Erase (P/E) operations/Erase (P/E) operations.
• Accurately predicting P/E behavior of SANOS/SONOS y p gmemories
Si l ti t l ti i t t l bi• Simulation up to long time instants, large biases
• For different gate stack dimensions• For different gate stack dimensions
• For different Nitride Compositions18
p
Simulation Methodology
•Set P/E bias•Compute Poisson throughout•Compute Poisson throughout gate stack•Assume TO and CD as pureAssume TO and CD as pure tunnel barriers, compute tunneling currents in and out of SiN•Compute transport, continuity and SRH (trapping detrapping)and SRH (trapping detrapping) in SiN•Compute trapped charges, Co pute t apped c a ges,update Poisson•Continue till end of P/E time
19
Simulation Flow
20
Key Models Incorporated
Tsu-Esaki tunneling formulation
Field dependent capture cross sectionp p
Poole Frenkel detrapping from traps
T t b d t liTrap to band tunneling
21
P/E: Stack Energy Band Diagrams
22
SANOS sample stack properties
Gate Stack
SiN type
Si2H6/N3
flow ratio
Dep. Temp RI
Gate Stack Dimensions
(nm)type flow ratio(°C)
TO SiN CD
N2 0 005 650 2 006 4 6 15N2 0.005 650 2.006 4 6 15N2 0.005 650 2.006 6 6 12N2 0 005 650 2 006 4 6 12N2 0.005 650 2.006 4 6 12
N0 0.01 800 1.987 4 6 12
N0 More N rich SiN; N2 More Si rich SiNDiff t t k di i d t h k b t
23Different stack dimensions used to check robustness
ISPP Matching
Less than 1V change in VT (or VFB) for every 1V
6.5
7.5ExpField dep. σ (n = 3)σ = const (n = 0)
LowerVfb Shift
VT (or VFB) for every 1V increment in applied VG(ISPP slope <1V/V) 4.5
5.5
V)
σ = σ0/(1+(E/Esat)n)
Employing the field d d t bl
2.5
3.5
Δ V
fb (V
Lowerdependent σ enables accurate prediction of ISPP 0.5
1.5
LowerISPP Slope
ISPP
5 10 15 20-0.5
0.5
Vg (V)
24
Vg (V)
ISPP Matching
Good matching with ISPP data for varying 7 5
8.5
9.5 Exp: N2 (4/6/15nm)Exp: N2 (4/6/20nm)Exp: N0 (4/6/12nm)ISPP data for varying
gate stack thickness and nitride 5.5
6.5
7.5
V)
σ = σ0/(1+(E/Esat)3)
N2
compositions
S t3.5
4.5
Δ V
fb (V
Same parameter values used during P/E transient matching (to 0 5
1.5
2.5
Symbol : Exp
N0
transient matching (to follow)
4 6 8 10 12 14 16 18 20 22-0.5
0.5
Normalized Vg (V)
Symbol : ExpLine : Sim
25
g ( )
P/E MatchingP/E Matching
5.5Symbol: ExpLine: Sim 5
6
3.5
4.5
(V)
Line: Sim
3
4
5
(V)
1.5
2.5
Δ V
fb (
Vg : 12V-16V1
2Δ V
fb
Vg : -17V - -12V
10-6
10-5
10-4
10-3
10-2
10-1
100
-0.5
0.5
10-6
10-5
10-4
10-3
10-2
10-1
100
-1
0
Time (s)
Symbol: ExpLine: Sim
Time (s) Time (s)
Program and Erase transients (N2-4/6/12 nm SANOS)26
g ( )
P/E Matching (Change in TO)
5.5Symbol: ExpLine: Sim
6
3.5
4.5
V)
Line: Sim
3
4
5
V)
1.5
2.5
Δ V
fb (
1
2
3
Δ V
fb (V
Vg : -18V - -13V
10-6
10-5
10-4
10-3
10-2
10-1
100
-0.5
0.5Vg : 12V-17V
10-6
10-5
10-4
10-3
10-2
10-1
100
-1
0 Symbol: ExpLine: Sim
Time (s) 10 10 10 10 10 10 10Time (s)
Program and Erase transients (N2 6/6/12 nm SANOS)27
Program and Erase transients (N2-6/6/12 nm SANOS)
P/E Matching (Change in CD)
6.5Symbol: Exp
7
3 5
4.5
5.5
V)
Line: Sim
4
5
6
V)
1.5
2.5
3.5
Δ V
fb (V
1
2
3
Δ V
fb (V
Vg : -18V - -13V
10-6
10-5
10-4
10-3
10-2
10-1
100
-0.5
0.5Vg : 13V-18V
10-6
10-5
10-4
10-3
10-2
10-1
100
-1
0
1
Symbol: ExpLine: Sim
10 10 10 10 10 10 10Time (s)
10 10 10 10 10 10 10Time (s)
Program and Erase transients (N2 4/6/15 nm SANOS)28
Program and Erase transients (N2-4/6/15 nm SANOS)
P/E Matching (Change in SiN)
6.5
7.5Symbol: ExpLine: Sim 6
7
3 5
4.5
5.5
b (V
)
3
4
5
Vfb
(V)
1.5
2.5
3.5
Δ V
fb
Vg : 12V-17V
1
2Δ V
Vg : -17V - -13V
S b l E
10-7
10-6
10-5
10-4
10-3
10-2
10-1
100
-0.5
0.5
Time (s)
Vg : 12V 17V
10-6
10-5
10-4
10-3
10-2
10-1
100
-1
0
Time (s)
Symbol: ExpLine: Sim
N0-4/6/12nm
( )
Program and Erase transients (N0-4/6/12 nm SANOS) 29
g ( )
Extracted parameters (SiN dependence)
Parameter N0 N2 Parameter N0 N2Parameter N0 N2 Parameter N0 N2
Electron trap depth (eV)
1.8 1.63 Hole Trap Depth (eV) 1.73 1.95( )
Electron trap density (1019cm-3)
3.3 3.9Hole Trap Density
(1019cm-3)1.6 2.6
Electron σ const. , σ-0
(10-12 cm2)5.7 5.7
Hole σ const. , σ-0
(10-10 cm2)8 8
(10 cm ) (10 cm )
Trap-band emission f (1013 1)
4 4Saturation electric field
E (105 V/ )6.25 6.25
freq. υ-tbt(1013 s-1) Esat (105 V/cm)
Values of carrier effective masses band gaps and30
Values of carrier effective masses, band gaps and dielectric constants taken from published literature
Summary
N d l f l t i fi ld d d t t• New models for electric field dependent capture cross section has been proposed which gives excellent agreement with experimental resultsexcellent agreement with experimental results
• The robustness of the simulator is verified across different stack thicknesses and different nitride compositions to accurately predict the P/E and ISPP transients
31
Metal Nanodot (m-ND) Flash: Motivation• Floating Gate Cell
– poly-Si storage gateNanodot Cell
discrete nanodots as– poly-Si storage gate – discrete nanodots as storage node
C t l Di l t iControl Gate
Floating GateNanodots
Control Dielectric
e e e e e
Source DrainCh l
e e e e e e e Tunnel Dielectric
Source DrainCh l
e e e e e
Defect in Tunnel OxideComplete charge loss Only part of stored
Channel Channel
Charge storage in discrete nanodots increases
Complete charge loss y pcharge is lost
32immunity to tunnel oxide defects
m-ND Flash Process Flow
SL DLSL DLWafer CleanTunnel Oxide 40ǺMetal DepositionAnneal
ILD deposition
--
ILD depositionMetal
Deposition Si SiAnneal
Control Oxide: 120Ǻ Al2O3Post Deposition Anneal Si l L (SL) D l L (DL)Post Deposition AnnealMetallization: 1000Ǻ Pt
Single Layer (SL) Dual Layer (DL)
33
Pt Nanodot formation
500oC 700oC 900oC
5Å
Initial Deposited Thickness
10Å10Å
Anneal Temperature
Optimization of deposition and annealing processes results in large density( 12 2) ( ) ( %)
34(~4x1012cm-2), small size (~3nm) and large area coverage (~30%)
Cross-Section TEM
CD
ILD
CD
ILD
TOTO
Si
TO
Discrete SL and DL nanodot formation clearly visible35
y
SL Memory Window
8 +18V -> +20V 7 SL-S1
4
6
(V) 5
6
ow (V
)
SL S1 SL-S3
T = 10ms
0
2
4
V FB
Virgin VFB
2
3
4
ory
Win
do
10-5 10-4 10-3 10-2 10-1
-2
0
INT
-18V -> -20V
0
1
2
Mem
o
10 10 10 10 10
INTTime (s)
17 18 190
Gate Voltage (V)
Large Memory window & significant over erase (split window possibility)
36
( p p y)
Memory Window: SL vs. DL
4
6 12nm(b) SL
810
)
2
4
n V FB
(V) 17nm
Improvement :A hi d 38%
Improvement in i
468 DL
V FB (V
)
-2
0
atur
atio
n Achieved: 38%Expected: 42%
memory window over SL
202
urat
ion
16 17 18 19 20 21 22-6
-4Sa
Thick CD SplitT =10ms
17 18 19 20 21 22-4-2
Satu
• 90% improvement in DL window over SL due to
16 17 18 19 20 21 22Eq. Gate Voltage (V)
17 18 19 20 21 22Eq. Gate Voltage (V) (w.r.t SL)
• 90% improvement in DL window over SL due to increased CD thickness and charge storage in 2nd layer
• Memory window improvement only with thick CD: 38%, 37
y p y ,expected (40%)
High Temperature Retention
9 8 0 4
678
6
8
o
DL0.00.20.4
(V)
E-stategain
345
2
4
V FB (V
) 25oC 80oC150oC SL
VFB
(V -0.4-0.2
ΔV FB
P-stateloss
012
2
0
V 150 C
V)
DL1 0
-0.8-0.6 DL-S1
DL-S2 DL-S3DL-S9
100 101 102 103 104 -2
Time (s)
-1.0150oC80oC
Retention Temperature (oC)25oC
DL S9
Insignificant retention loss Retention better than SiN memory due to deeper
38
Retention better than SiN memory due to deeper potential well for m-ND’s
SL vs. DL P/E Endurance
6 6
345
4
5
6
) DL-S1
123
V FB (V
) Solid: SL-S1Open: SL-S3
2
3
V FB (V
) DL S1 DL-S2 DL-S3DL-S9
-101V
0
1DL-S9
100 101 102 103 104
# P/E Cycles100 101 102 103 104
# P/E Cycles
Better endurance for DL w.r.t SL
39No window closure till breakdown
P/E Endurance (DL-S9)( )
68
45
4
6
V) 234
V) 6V
0
2
V FB (V 6V
012
V FB(V 75000
6V
100 101 102 103 104
-2
100 101 102 103 104 105
-10
• 104 cycles with 6V and 7V memory window, 2x103 cycles
10 10 10 10 10# P/E Cycles
10 10 10 10 10 10# P/E Cycles
0 cyc es t 6 a d e o y do , 0 cyc eswith 8V memory window
• Maximum endurance seen when P/E-states are within 40
+6V/-2V• No window closure till breakdown
MLC Operation (DL-S9)
4 11 4
2
3
4
10VPASS= 6V
2
3 T = 80oC
0
1
2
01V FB(V
)
0
1
V FB(V
)
-2
-1
0
00 -2
-1
10-2 10-1 100 101 102 103
2
Disturb Time (s)100 101 102 103 104
2
Retention Time (s)
Excellent separation maintained between the P/E levels after read disturb and high-T retention stress
41
g
Summary
• Single and dual layer Pt metal Nanodot memory gate stacks demonstrated
• Excellent memory window, cycling endurance (>10K ith 6V i d ) d t li(>10K with 6V window), pre- and post-cycling retention
• MLC capabilities• MLC capabilities• No fundamental reliability show stopper for metal
dots in gate stackdots in gate stack• Need feasibility demonstration in scaled (sub
20nm node) cells20nm node) cells
42
Simulation of m-ND Flash
• To demonstrate viability of m-ND cells in sub 20nm cells (impact of cell size no of dots area coverage(impact of cell size, no. of dots, area coverage, fluctuations, missing dots, dot to dot leakage…..)
• Full 3D electrostatics and tunneling implementation
S l L l f t ti l & l t i fi ld i t t k• Solve Laplace for potential & electric field in gate stack
• Non-local tunneling implementation (Tsu-Esaki) forNon local tunneling implementation (Tsu Esaki) for charging of dots (substrate to dot, dot to gate, dot to dot)
• Calculate charges in iterative manner
P t d t h i i l t d i i l t d i43
• Port dot charges in equivalent device simulated using Sentaurus Device for VT calculation
Potential, E-field, Tunnel current (2D cuts)
44
Charge Transients
45
Prediction….
Area coverage, Channel length, No. density, Missing dots…
46
Summary
• Full 3D electrostatics – tunneling framework to study m-ND Flash viability below 20nm node
Immunity to fluctuations (good)• Immunity to fluctuations (good)
• Memory window reduction with L scaling (issue)Memory window reduction with L scaling (issue)
• Cells becomes edge critical (issue)
47