Sp09 CMPEN 411 L18 S.1 CMPEN 411 VLSI Digital Circuits Spring 2009 Lecture 16: Static Sequential...

Sp09 CMPEN 411 L18 S.1

CMPEN 411VLSI Digital Circuits

Spring 2009

Lecture 16: Static Sequential Circuits

[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]


A Chip Example

Type Gate_Count Area ----------------------------NAND 70232 425102AND 44417 310227OR 21652 139790NOR 43635 361006XOR 17095 211430XNOR 9699 127071INV 78870 269643MUX 34505 422824REG 112805 2737435 MEM 138 17937962 OA 37878 379645AO 40396 480452ADD 4185 87885 ------------------------total gate count 502597total gate count for combinatorial 389654total area 23,766,927 um2total area for combinatorial 3,091,530 um2

87% of the area are memory and registers


Sequential Logic

CombinationalLogic

clock

Outputs

Sta

teR

egis

ters

NextState

CurrentState

Inputs


Timing Metrics

clock

In

Out

datastable

outputstable

outputstable

time

time

time

clock

D QIn Out

tsu thold

tc-q


System Timing Constraints

CombinationalLogic

clock

Outputs

Sta

teR

egis

ters

NextState

CurrentState

Inputs

T tc-q + tplogic + tsutcdreg + tcdlogic thold

T (clock period)


Static vs Dynamic Storage

Static storage preserve state as long as the power is on have positive feedback (regeneration) with an internal

connection between the output and the input useful when updates are infrequent (clock gating)

Dynamic storage store state on parasitic capacitors only hold state for short periods of time (milliseconds) require periodic refresh usually simpler, so higher speed and lower power


Latches vs Flipflops

Latches level sensitive circuit that passes inputs to Q when the clock is

high (or low) - transparent mode input sampled on the falling edge of the clock is held stable

when clock is low (or high) - hold mode

Flipflops (edge-triggered) edge sensitive circuits that sample the inputs on a clock

transition- positive edge-triggered: 0 1

- negative edge-triggered: 1 0

built using latches (e.g., master-slave flipflops)


Positive and Negative Latches

clock

D QIn Out

clock

D QIn Out

clk

Out

In

clk

Out

In


Review: The Regenerative Property

If the gain in the transient region is larger than 1, only A and B are stable operation points. C is a metastable operation point.

A

Vi2 Vo2

Vi1 = Vo2

Vi2

= V

o1

B

C

Vo1Vi1

cascaded inverters

Sp09 CMPEN 411 L18 S.11

Bistable Circuits

The cross-coupling of two inverters results in a bistable circuit (a circuit with two stable states)

Have to be able to change the stored

Two approaches used cutting the feedback loop (mux based latch) overpowering the feedback loop (as used in SRAMs)

Vi1

Vi2

Sp09 CMPEN 411 L18 S.14

MUX Based Latches

Q

D

clk

0

1

Positive Latch

Q

D

clk

1

0

Negative Latch

Q = !clk & Q | clk & DQ = clk & Q | !clk & D

feedback

transparent when the clock is low

transparent when the clock is high

feedback

Change the stored value by cutting the feedback loop

Sp09 CMPEN 411 L18 S.15

TG MUX Based Latch Implementation

Q

D

clk

clk

!clk

!clk

clk

input sampled(transparent mode)

feedback(hold mode)

clk

D L

atch

QD

Sp09 CMPEN 411 L18 S.16

PT MUX Based Latch Implementation

QD

clk !Q

!clk

!clk

clk

input sampled(transparent mode)

feedback(hold mode)

Reduced area and clock load, but a threshold drop at output of pass transistors so reduced noise margins and performance

Sp09 CMPEN 411 L18 S.17

Latch Race Problem

CombinationalLogic

clk

Sta

teR

egis

ters

clk

B B’

Two-sided clock constraint

T tc-q + tplogic + tsu

Thigh tc-q + tcdlogic

B

Which value of B is stored?

Sp09 CMPEN 411 L18 S.18

Master Slave Based ET Flipflop

QMD 0

1 Q1

0

SlaveMaster

QMD

clk

0

1 Q

clk

1

0

SlaveMaster

clk

QM

Q

D

clock

D F

F

QD

clk = 0 transparent hold

clk = 01 hold transparent

Sp09 CMPEN 411 L18 S.19

MS ET Implementation

Q

D

clk

QM

I1

I2 I3

I4

I5 I6T2

T1T3

T4

Master Slave

!clk

clk

Sp09 CMPEN 411 L18 S.20

MS ET Implementation

Q

D

clk

QM

I1

I2 I3

I4

I5 I6T2

T1T3

T4

Master Slave

!clk

clk

master transparentslave hold

master holdslave transparent

Sp09 CMPEN 411 L18 S.22

MS ET Timing Properties

Assume propagation delays are tpd_inv and tpd_tx, that the contamination delay is 0, and that the inverter delay to derive !clk is 0

Set-up time - time before rising edge of clk that D must be valid

Propagation delay - time for QM to reach Q

Hold time - time D must be stable after rising edge of clk

tsu = 3 * tpd_inv + tpd_tx

tc-q = tpd_inv + tpd_tx

thold = zero

Sp09 CMPEN 411 L18 S.23

Set-up Time Simulation

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.2 0.4 0.6 0.8 1

Vo

lts

Time (ns)

D clk

Q

QM

I2 out

tsu = 0.21 ns

works correctly

tsetup

Sp09 CMPEN 411 L18 S.24

Set-up Time Simulation

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.2 0.4 0.6 0.8 1

Vo

lts

Time (ns)

D clk

Q

QM

I2 out tsu = 0.20 ns

fails

tsetup

Sp09 CMPEN 411 L18 S.25

Propagation Delay Simulation

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5

Vo

lts

Time (ns)

tc-q(LH) = 160 psec

tc-q(HL) = 180 psectc-q(LH) tc-q(HL)

Sp09 CMPEN 411 L18 S.26

Power PC Flipflop

D Q

!clk

clk

clk

!clk

01

10 1

!clk

clk

Sp09 CMPEN 411 L18 S.27

Power PC Flipflop

D Q

!clk

clk

clk

!clk

01

10 1

!clk

clk



01 01

Sp09 CMPEN 411 L18 S.29

Non-Ideal Clocks

1-1 overlap

0-0 overlap

!clk

clk

Ideal clocks

!clk

clk

Non-ideal clocksclock skew

Sp09 CMPEN 411 L18 S.30

Example of Clock Skew Problems

D

clkX

!clk

!Q

!clk Q

clk

B

AP1

P2

P3

P4

I1 I2I3 I4

Race condition – direct path from D to Q during the short time when both clk and !clk are high (1-1 overlap)

Undefined state – both B and D are driving A when clk and !clk are both high

Dynamic storage – when clk and !clk are both low (0-0 overlap)

Sp09 CMPEN 411 L18 S.31

Pseudostatic Two-Phase ET FF

D

clk1X

clk2

!Q

clk2 Q

clk1

B

AP1

P2

P3

P4

I1 I2I3 I4

clk2

clk1



dynamicstorage

tnon_overlap

Sp09 CMPEN 411 L18 S.32

Two Phase Clock Generator

clk

clk1

clk2

A

clk

A

B

B

clk1

clk2

Sp09 CMPEN 411 L18 S.33

Review (from CSE 271): SR Latch

S R Q !Q

0 0 Q !Q memory

1 0 1 0 set

0 1 0 1 reset

1 1 0 0 disallowed

S

RQ

!Q

Sp09 CMPEN 411 L18 S.39

6 Transistor CMOS SR Latch

clkclk

SR

M1

SR

clk

!QQ

M2

M3

M4

M5M6

clk

Will see this structure in SRAM design

Sp09 CMPEN 411 L18 S.40

Next Lecture and Reminders Next lecture

Dynamic sequential circuits - Reading assignment – Rabaey, et al, 7.3, 7.7

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