2 | Spark-102 HW user manual V2.0
Contents 1 Scope ..................................................................................................................................................... 4
1.1 SoM introduction ............................................................................................................................. 4
2 Block diagram ........................................................................................................................................ 5
3 SOM integration – system aspects........................................................................................................ 5
3.1 Power considerations ...................................................................................................................... 5
3.1.1 VCCBAT – FPGA Encryption Key power ................................................................................... 5
3.1.2 Spark Power scheme ............................................................................................................... 6
3.2 Reset sources ................................................................................................................................... 7
3.3 Clocks scheme .................................................................................................................................. 8
3.4 Temperature sensor......................................................................................................................... 8
3.5 JTAG ................................................................................................................................................. 8
4 HPS system and Interfaces .................................................................................................................... 9
4.1 HPS Memories scheme .................................................................................................................... 9
4.1.1 QSPI NOR memory ................................................................................................................ 10
4.1.2 EEPROM................................................................................................................................. 10
4.1.3 eMMC (iNAND) ...................................................................................................................... 10
4.1.4 SD/eMMC interface............................................................................................................... 10
4.1.5 DDR memory ......................................................................................................................... 10
4.2 Boot options ................................................................................................................................... 11
4.3 FPGA Firmware configuration options ........................................................................................... 12
4.4 Interrupt & I/O Table ..................................................................................................................... 13
4.5 HPS interfaces ................................................................................................................................ 14
4.5.1 HPS USB Interfaces ................................................................................................................ 14
4.5.2 Ethernet port ......................................................................................................................... 14
4.5.3 UART ...................................................................................................................................... 15
4.5.4 CAN ........................................................................................................................................ 15
4.5.5 I2C .......................................................................................................................................... 16
4.5.6 SPI .......................................................................................................................................... 16
5 SOC FPGA part ..................................................................................................................................... 17
5.1 FPGA Banks .................................................................................................................................... 17
5.2 FPGA IOs ......................................................................................................................................... 18
3 | Spark-102 HW user manual V2.0
5.3 FPGA IOs variation according to FPGA size .................................................................................... 18
5.4 Transceivers ................................................................................................................................... 19
5.5 FPGA configuration ........................................................................................................................ 19
5.5.1 Configuration via byte blaster ............................................................................................... 19
5.5.2 Configuration via Software ................................................................................................... 19
5.6 Industrial Ethernet module ............................................................................................................ 20
5.7 CSEL Configuration ......................................................................................................................... 22
6 SMARC interface Pin assignment ........................................................................................................ 22
7 Mechanical considerations ................................................................................................................. 23
7.1 SMARC connector .......................................................................................................................... 24
Appendix 1 - Hardware devices used on the SOM ..................................................................................... 26
Appendix 2 – Hardware configuration summary ........................................................................................ 27
Appendix 3 – Qsys parameters for the Spark ............................................................................................. 28
Document Revision History
Revision Date Description
1.0 2.2.2016 Initial version
1.1 22.8.2016 Add internal Ethernet PHY connectivity to the FPGA, add phy reset description.
1.2 28.9.2016 Add support for Spark-102v2
2.0 21.5.2017 Pin out was taken to another documnet
4 | Spark-102 HW user manual V2.0
1 Scope The purpose of this document is to provide a guide for integrating the Spark-102 into the target
hardware in an easy and fast way to shorten and simplify the development process.
The guide is divided into two parts, the first guide you through the integration process, giving design
samples based on the CB-52 development board (schematics can be provided by Shiratech via
[email protected] ), the second part provides a more detailed description of the Spark-102
system.
In order to simplify the integration process we recommend the following process:
1. Read through the integration guide about the required interfaces.
2. Use Shiratech’s Pin configuration tool to define the solution
3. Use the CB-52 as a reference design and schematics to shorten the development process.
For more details if needed, review the Cyclone V user manual.
1.1 SoM introduction The Spark-102 is an industrial embedded System-On-Module (SoM) based on Altera new Cyclone V SoC.
The Spark-102 offers a unique combination of a high performance ARM core containing one or two
Cortex-A9 cores combined with a large FPGA offering up to 110KLE.
The Spark-102 enables the end user to create a tailored solution made of the ARM processor variety of
interfaces combined with additional "Soft Core" interfaces based on the FPGA. The unique
interconnection between the FPGA and ARM core enables the ARM processor to access the FPGA based
interfaces as regular slave interfaces.
For industrial automation product development the Spark offers built-in Industrial Ethernet core
including dedicated Ethernet ports, built-in FPGA IP and full Linux support reduce R&D efforts, risk and
time.
The Spark-102 supports the SMARC standard developed by SGET (www.sget.org) utilizing a 314 interface
connector providing a rich and flexible interface towards the carrier board.
The module has several configuration options for supporting the various Altera SOC sizes and variations
along with different memory sizes to support the various project's needs.
5 | Spark-102 HW user manual V2.0
2 Block diagram The following diagram provides an overview of the SOM. The following paragraphs will provide detailed
description of the various parts of the SOM and how to use them in order to build a product based on it.
Figure 1 – SOM main building blocks
3 SOM integration – system aspects
3.1 Power considerations The Spark-102 uses a single 5V power input from which all the other required voltages are taken. The
Inlet power should be
Rise time: <= 3ms
Input voltage range: 5V +/- 5%
3.1.1 VCCBAT – FPGA Encryption Key power
The Altera SOC has an option to maintain an encryption key for FPGA configuration even if the system
power is down. For that pin S147 of the SMARC interface should be connected to a power source
(between 1.2V - 3V). If the option is not used connect pin S147 to 2.5V. The interface is connected to
VCCBAT (D7) pin of the SOC.
ECAT BLOCK
ARM 9
CORE
eMMC
4-64 GB
MM
C D
[0..
7]
Serial
NOR
QS
PI
(CS
0)
PWR
Mng.
P
I
N
M
U
X
GE
PHYRGMII
S
M
A
R
K
TX/RX
USB OTG
SPI 0,1 (4 x CS)
I2C 0,1
USART 0 (RX/TX)
CAN 0,1
PWR_En, WKUP, Idle, Sleep
FPGA
DDR3
D[0
-31]
SD
MUX
FE
PHY
FE
PHY
B
A
N
K
3
A
/
B
CPLD
(AUT)
EEPROM
BANK8A/5B
BANK4A
BANK5A
USB
PHY
QSPI (CS1)
UMTI
MMCD[0..3]
TRANS
Clock
Driver
uDS
MII
MII
I2C
I/O
S
M
A
R
K
100BT
100BT
DIFF. CLK
6 x SER/DES
64 I/O, 4 CLK
LVDS DISPLAY, 16 I/O
CSI 2 LANE, I/O
Clock
Driver
6 | Spark-102 HW user manual V2.0
3.1.2 Spark Power scheme
The SPARK-102 has flexible power architecture to support the ARM core and the FPGA's power
requirements. The following figure describes the power architecture:
Figure 2 – SOM internal power scheme
The SOM uses both fixed and configurable power converters for powering the HPS and FPGA IO banks.
The following table describes the power levels of available for each I/O bank:
FPGA IO banks:
FPGA bank
Number of
I/O
Voltage
supported
Remarks
Bank 3A 16 1.8V Not available to the user
Bank 3B 32 1.8V Not available to the user
Bank 4A 68 1.8V, 2.5V The selection is done by hardware and
cannot be changed during operation.*
Bank 5A 16 2.5V Fix
1.1V, (3A)
Core
TPS54318
1.5V, (3A)
DDR3
TPS54318
2.5V,0.6A
EP5358HQI
3.3V,0.6A
EP5358HQI
1.8V,0.6A
EP5358HQI
Vin 5V
HPS Core
FPGA VCC
HPS DDR3, DDR3
FPGA PLL, OSC, I/O
VCCPD
FPGA VCCIO
Peripherals
Peripherals
FPGA VCCIO
FPGA VCCIO
Bank 4A
PG
1.8/2.5V,0.6A
EP5358HQI
7 | Spark-102 HW user manual V2.0
Bank 5B 7 2.5V Fix
Bank 8A 6 2.5V Fix
*Notes:
Bank 4A power level is controlled via a dedicated pin on the SMARC interface, Bank 4A VCC IO
located on P106.
- When connected to GND then VCCIO is set 1.8V, when connected to VCC then VCCIO is set to 2.5V.
- The pin setting cannot be based on I/O controlled by software! the pin state should be stable
at power up and cannot be changed after power up.
HPS IO banks:
HPS bank Voltage supported Remarks
Bank 6 1.5V Internal bank for DDR
7A 1.8V Various interfaces,
7B, 7C 3.3V Various interfaces, like SD and USB
3.2 Reset sources The SPARK-102 supports three reset sources:
Cold reset (Power On Reset - RESET_IN# – P127 on the SMARC interface) o Used to ensure the HPS is placed in a default state sufficient for software to boot o Triggered by a power-on reset and other sources e.g. push buttons on carrier board o Resets all HPS logic that can be reset o Affects all reset domains
Warm reset (FORCE_RECOV# - S155 on the SMARC interface) o Occurs after HPS has already been through a cold reset o Used to recover system from a non-responsive condition o Resets a subset of the HPS state reset by a cold reset o Only affects the system reset domain, which allows debugging (including trace) to operate
through the warm reset
Debug Reset o Occurs after HPS has already been through a cold reset o Used to recover debug logic from a non-responsive condition o Only affects the debug reset domain
The cold and warm resets are controlled by voltage supervisors which guarantee the reset duration.
Both signals are available on the SMARC connector. The FPGA can be reset by the SOC ARM core or by
an IO pin on the FPGA fabric.
8 | Spark-102 HW user manual V2.0
Note:
When using the 128 MB QSPI Flash memory as a boot source the warm reset does not work
automatically due to configuration issues of the QSPI memory. For more details:
http://www.rocketboards.org/foswiki/Documentation/SocBoardQspiBoot
For 32MB QSPI Flash memory configuration the problem is resolved.
3.3 Clocks scheme The SPARK-102 contains a single clock buffer which distributes a 25 MHz clock to the HPS core, the FPGA
clock input 1 and 2 and to the Industrial Ethernet PHY devices. The following figure describes the clock
architecture.
Figure 3 – SPARK-102 Clock Architecture
3.4 Temperature sensor The Spark has a build in temperature sensor based on TI Digital Temperature Sensor TMP 108. The
device is controlled via I2C1 bus.
3.5 JTAG A 10 pins JTAG connector for byte blaster connectivity is available on the SOM, the connector will be
available for development when the SOM is provided with the evaluation board or as an ordering
option.
Fan Out
Buffer
25 MHz
HPS CLK1
HPS CLK2
FPGA CLK1
FPGA
SMARC CONNECTOR
HPS
FPGA CLK2CLKI0_p
CLKI1_p
Transceiver CLKI
Transceiver CLKI
Single ended 25 MHz
100, 125, Other Differential
Single End, Differential
Local OSC
25 MHZ
CL
KI2
_n
/p
CLK
CLK
CL
KI3
_n
/p
CL
KI4
_n
/p
CL
KI5
_n
/p
Basic Clock
CL
KI6
_n
/p
CL
KI7
_n
/p
Fast Ethernet
(ECAT)
Fast Ethernet
(ECAT)
9 | Spark-102 HW user manual V2.0
4 HPS system and Interfaces The Spark-102 can be ordered with one or two ARM cores running at 800Mhz or 925Mhz (grade 6). The
SOM offers a variety of interfaces from the HPS (ARM core) such as USB, Ethernet, I2C, SPI, UART and
more. The following paragraphs describe the various interfaces available along with recommendations
on how to connect them to the carrier board.
4.1 HPS Memories scheme The SPARK-102 includes several options for non-volatile memories for booting and data storage,
including:
- A QSPI NOR memory (32MB or 128MB), can be used for a small footprint Linux version or RTOS.
- Internal eMMC device of 4GB up to 8GB(for larger size please contact Shiratech), used for both
software and storage.
- A small I2C memory 128x8 EEPROM, used for card details and can be used for system
parameters.
Figure 4 – SPARK-102 Non-Volatile Memory
10 | Spark-102 HW user manual V2.0
4.1.1 QSPI NOR memory
The Spark supports a QSPI NOR memory. The memory is connected to the QSPI interface of the HPS
offering:
4 bits Data bus.
Up to 108MHz clock.
32Mbytes - optional.
4.1.2 EEPROM
The Spark-102 is supports an internal I2C memory device Atmel AT24C01Ce, located on I2C0 bus of the
HPS offering:
1Kbit I2C memory.
Can be used as secure boot.
Can be used as MAC address for the GE interface. Note: part of the memory is internally used for card parameters.
4.1.3 eMMC (iNAND)
The Spark supports a 4GByte eMMC device offering:
Up to 8 data bits.
Up to 50 MHz clock. An 8GByte option is available as an ordering option.
4.1.4 SD/eMMC interface
The SPARK-102 has a single SD/MMC bus connected to the HPS. The HPS is connected via an internal
multiplexer (TXS02612 - SDIO Port Expander by TI) to either an internal 4/8 bits wide eMMC or to an
external 4 bits SD interface.
The control of the mux is via an external pin P123 in the SMARC interface, ‘0’ – eMMC, ‘1’ - external SD,
or via software using GPIO 44 of the HPS.
4.1.5 DDR memory
The SPARK-102 integrates 32 bit wide DDR3 running at 400 MHz. The basic configuration is two chips of
256MBx16 (1GB solution). There is also an ordering options for 128MBx16 (512MB solution) and
512MBx16 (2GB solution).
11 | Spark-102 HW user manual V2.0
Figure 5– SPARK-102 DDR support
4.2 Boot options The Altera SOC offers several boot options. These options are selected according to three pins (Bsel 2-0).
The Spark support only part of these options Bsel
The pins are connected to the SMARC interface,
- Bsel 0 is P123
- Bsel 1 is P124,
- Bsel 2 is P125
Offering the following options:
Bsel value
Boot source Support
000 Reserved Not supported
001 FPGA (HPS-to-FPGA bridge) Supported both pins should be set '0'
010
1.8 V NAND flash memory Not supported
011
3.0 V NAND flash memory Not supported
100 1.8 V SD/MMC flash memory with external transceiver
Not supported
101 3.0 V SD/MMC flash memory with internal transceiver*
Supported, Bsel 1 should be tight to '0'
110 1.8 V SPI or quad SPI flash memory
Not supported
111 3.0 V SPI or quad SPI flash memory Supported, both pins should be left open
Note: on all BSEL there is an internal pull up is assembled on the SOM.
HPS DDR3
16 Bits
2Gb – 8Gb
DDR3
16 Bits
2Gb – 8Gb
D[0..15]
D[16..31]
A[0..15]
BA[0..2]
CS[0,1], ODT[0,1], CK[0,1]
DDR3
Controller
12 | Spark-102 HW user manual V2.0
Figure 6 - Boot & FPGA Configuration
4.3 FPGA Firmware configuration options The Spark-102 supports FPGA configuration via the ARM processor. The module supports only FPP 16
mode if security and/ or compression are required these modes can be enabled via SW1 which controls
MSEL 0 and MSEL 1. MSEL 4-2 are set to '0'.
The MSEL pins are available on the SMARC connector in the following pins:
- Msel 0 is P104
- Msel 1 is P105
The following MSEL modes are supported:
- 00000 Fast Parallel 16 bits - 00001 Fast Parallel16 bits /Security enabled - 00010 Fast Parallel16 bits /Compressed enabled - 00011 Fast Parallel/Security enabled /Compressed enabled
Note- since the BSEL pins have alternate function after POR, the PD resistor should be 1.5K.
HPS
FPGA
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
BSEL0
BSEL1
BSEL2
Vcc
ModuleCarrier
1.5K
Vcc Vcc
VccVcc
0 Ohm
0 Ohm
0 Ohm
Assembly
Option
Assembly
Option
13 | Spark-102 HW user manual V2.0
4.4 Interrupt & I/O Table The following table describes the role of the various HSP IO used on the Spark:
Signal I/O Description Remarks
SD_MMC_SEL GPIO44 Select between eMMC on SOM and
uSD on carrier
0 – eMMC
1 - uSD
SD_PWR_EN GPIO37 Enable power to the carrier uSD card Active High
GE Interrupt GPI2 Giga Ethernet Interrupt from PHY Active Low
TEMP_ALM GPI3 Temperature Sensor Alarm Active Low
FE Interrupt GPI1 Fast Ethernet Interrupt Active Low
RTC ALARM GPI0 Real Time Clock Alarm Active Low
14 | Spark-102 HW user manual V2.0
4.5 HPS interfaces
4.5.1 HPS USB Interfaces
The SPARK-102 supports a single Host/Device (USB OTG) USB interface. The following figure describes the USB interface in the SPARK-102.
Figure 7 - HPS USB Interfaces
A USB PHY (Microchip's USB3300) is used to convert the HPS ULPI interface into a USB OTG interface.
The USB OTG and Host interfaces can control a power distributer on the carrier board. The following
figure describes the USB control signals.
Figure 8 - HPS USB Control Signals
To save signals space over the SMARC connector the SPARK-100 ECAT USB interfaces use a single line to
support both, power enable and over current. The carrier power distributer MUST use a high level
enable pin and open drain low active "Over-Current" signal.
In this way a level high will enable the power distribution while a level low from the HPS or the
Overcurrent signal will disable the power distribution.
4.5.2 Ethernet port
The SPARK-102 supports a Giga Ethernet interface. The Giga Ethernet uses the HPS RGMII interface. The
following figure describes the Giga Ethernet interface.
HPS
USB PHY
OTG
(USB3300)
Data[0..7]
Ctrl
USB 0
USB Power
USB_EN
USB_EN_OC# USB_EN_OC#
OC#
ENVOUT
SOM Carrier
Vcc
15 | Spark-102 HW user manual V2.0
Figure 9 - Giga Ethernet Interfaces
The 1G Ethernet PHY is Micrel's KSZ9031. It uses an RGMII interface running at 125 MHz. The 125 MHz
clock is generated by the KSZ9031 Giga Ethernet PHY.
The 1G Ethernet PHY analog signals (TX+/-, RX+/-) are connected to the SMARC edge connector. Two led
signal from the GE PHY are also connected to the SMARC edge connector.
MDC/MDIO - The Ethernet MDC/MDIO signals are connected to the internal phy and are not available
on the SMARC connector.
4.5.3 UART
The SOC offer one or two UARTs. Each UART includes Rx, Tx , CTS and RTS. The HPS supports up to two
UART interfaces. UART 0 is usually used for Linux CLI interface. Some of the UART signals share the same
pins as the SPI interfaces which available on the SMARC connector.
UART0 TX/RX signals are available on the SMARC SER3 interface.
Programmable character properties, such as number of data bits per character, optional parity bits, and number of stop bits.
Programmable baud rate.
Automatic flow control mode per 16750 standards. The maximum UART baud rate is 6.25 mega symbols per second.
4.5.4 CAN
The HPS offers up to two CAN controllers based on the Bosch® D_CAN controller and offer the following
features:
Compliant with CAN protocol specification 2.0 part A & B.
Programmable communication rate up to 1 Mbps.
Holds up to 128 messages.
Supports 11-bit standard and 29-bit extended identifiers.
Programmable interrupt scheme.
HPS
Micrelksz9031
RGMII4 x TX
4 x RX
Controls
125 Mhz
25M
Int.
NReset
LEDS LEDS
GE Analog
CarrierModule
16 | Spark-102 HW user manual V2.0
Direct access for host processor.
DMA controller may be used for large transfers.
4.5.5 I2C
The SPARK-102 supports two I2C master interfaces out of the HPS:
I2C0 is used as I2C_GP (SMARC standard).
I2C1 is used as I2C_PM (SMARC standard). On the Spark there are two I2C devices:
Serial EEPROM (AT24C01C by Atmel) which is located on I2C0 and is used for card parameters and user specific data and
A temperature sensor which is located on I2C1. The following figure describes the I2C interfaces.
Figure 10 - SPARK-102 I2C Interfaces
According to the SMARC standard there are two additional I2C interfaces, I2C_CAM and I2C_LCD. These
interfaces can be implemented in the FPGA if required.
The following table describes the I2C addresses mapping.
4.5.6 SPI
The SPARK-102 supports up to two SPI interfaces connected to the HPS. Each port offers:
Single CS signal for each SPI interface.
Programmable master serial bit rate up to 50 MHZ.
Serial master
Programmable data item size of 4 to 16 bits Note – When the SPI interfaces are not in use, the pins can be configured as a GPIOs.
Ref. Chip I2C Port Address A Port Address B Description
Ux Temp Sens 1 1 0 0 1 0 0 0 RW 48H Temperature Sensor
Ux EEPROM 0 1 0 1 0 0 0 0 RW 50H EEPROM
HPS
Temp
Sens
I2C0
I2C1
CarrierModule
I2C_CAM
I2C_GP
I2C_PM
I2C_LCD
eeprom
FPGA
17 | Spark-102 HW user manual V2.0
5 SOC FPGA part The Spark 102 offer a range of FPGA sizes starting from 25KLEs and up to 110KLEs, supporting both SE
and SX SOC variations. The Spark offers 102 FPGA I/Os on the SOM interface along with 6 high speed
transceivers.
5.1 FPGA Banks Most of the FPGA banks are available at the SMARC interface for general purpose use. The banks that
are not available are used internally for the Industrial Ethernet (IE) module.
- Bank 3A and Bank 3B are used for the IE and are not available for the user(set to 1.8V)
- Bank 4A is fully available to the user with a configurable voltage level (2.5v or 1.8V).
- Bank 5A is available to the user as LVDS interface (2.5V).
- Bank 5B and Bank 8A are available to the user (2.5V). The Banks IO number is dependent on the
FPGA size. (Check the SOC data sheet and paragraph 5.3 for details).
- Up to 6 transceivers (SX version).
Figure 11 - FPGA Banks
ECAT BLOCK
FPGA
FE
PHY
FE
PHY
B
A
N
K
3
A
/
B
CPLD
(AUT)
EEPROM
BANK8A/5B
BANK4A
BANK5A
TRANS
Clock
Driver
MII
MII
I2C
I/O
S
M
A
R
K
100BT
100BT
DIFF. CLK
6 x SER/DES
64 I/O, 4 CLK
LVDS DISPLAY, 16 I/O
CSI 2 LANE, I/O
Clock
Driver
18 | Spark-102 HW user manual V2.0
5.2 FPGA IOs The following FPGA I/Os are available on the SMARC interface:
FPGA bank Number of I/O Voltage supported
Bank 4A 68 1.8V, 2.5V*
Bank 5A 16 2.5V
Bank 5B 7** 2.5V
Bank 8A 6** 2.5V
Notes:
All FPGA GPIO which can be differential pairs are routed as pairs to the SMARC connector.
*The selection pin is available at the SMARC interface.
** The number of IO in Bank5A and Bank8A are dependent on the FPGA size
5.3 FPGA IOs variation according to FPGA size The Spark-102 support several SOC variations starting from 25KLE and up to 110KLE for both SE and SX
series. Altera offers the same package for all variations however there are differences between the pin
out of the different FPGA sizes and types. The 110KLE and 85KLE (A6/A5) share the same pin out while
the 40KLE and 25KLE (A2/A4) share different pin out.
The following pins are should be tied to ground for the A5/A6 devices so in case the solution should
support also A2 and A4 parts, these pins should not be used a and should be connected to ground.
PIN_H4 GND
PIN_H5 GND
PIN_H6 GND
PIN_K8 GND
PIN_L8 GND
PIN_L9 GND
PIN_L10 GND
The following pins are available for the A6 and A5 only when using an A2 or A4 device they should be
connected as follows:
PIN_W19 Not connected, leave open
PIN_W20 GND
PIN_W21 GND
PIN_W24 GND
PIN_W25 Not connected, leave open
PIN_Y24 GND
19 | Spark-102 HW user manual V2.0
It means that for a design which uses both FPGA sizes these pins should not be used!
An additional variation is between the SX and SE devices, the difference is the transceivers which are
available on the SX devices. When using a Spark with SE device the following should be done:
The transceivers received lines should be tied to ground.
The transmit lines should be left open.
5.4 Transceivers
The Cyclone V SX family provides 6 transceivers at 3.125 Gigabits per second (Gbps). These transceivers
comply with a wide range of protocols and data rate standards.
On the Spark the transceivers are routed as differential pairs to support high speed applications. The
Spark also provide optional low jitter differential clock using a build in clock generator, with an option to
provide differential clocks.
5.5 FPGA configuration The FPGA can be configured in several ways:
5.5.1 Configuration via byte blaster
The Spark has an option for a build in 10 pins JTAG connector for connecting the byte blaster (for
development boards only. ordering option).
5.5.2 Configuration via Software
The FPGA can be easily configured via Software. The FPGA configuration file should be placed in the FAT
part of the SD used for software. The FPGA file should be in FPP 16(Fast parallel 16 bits), security
disable, compression disable, RBF format, the file should be called fpga.rbf. The FPGA will be programed
by the boot software, which means that FPGA download can be done without any customization of the
SW thus provides total decoupling between the SW and HW development.
20 | Spark-102 HW user manual V2.0
5.6 Industrial Ethernet module A Master/Slave Industrial Ethernet (IE) module is available as an ordering option on the SOM. The
module utilize Industrial Ethernet FPGA firmware (From Softing
http://company.softing.com/en/startpage.html ) providing various standard interfaces like EtherCAT,
Profinet and others.
The module includes the following items:
Two Fast Ethernet PHY (Microchip KZS8081MNX).
Clock distribution to support the ECAT timing requirement.
An authentication EPLD to enable the FPGA Firmware supporting all relevant protocols.
EEPROM needed by the ECAT to store parameters. The following figure describes the ECAT module.
Figure 12 – Industaril Ethernet Module
The Fast Ethernet PHYs are connected to the FPGA Bank3A and Bank3B. via MII interface to enable
minimal delay in the PHY (No need for a FIFO) as required by the IE standard.
The Authentication CPLD for the IP and the EEPROM are also connected to Bank3A.
FPGA
Micrel
KSZ8081
MII
4 x TX
4 x RX
Controls
LEDS
LEDS
FE Analog
CarrierModule
LINK
Clock
Buffer
25 MHz
Con. &
Mag.
Micrel
KSZ8081MII
4 x TX
4 x RX
ControlsLEDS
LEDS
FE Analog
LINK
Con. &
Mag.
CPLD License
Authentication
EEPROMECAT
Parameters
BANK3A/
BANK3B
21 | Spark-102 HW user manual V2.0
BANK Diff. Pair Pin Description
VREFB3BN0 DIFFIO_RX_B26n AE9 CPLD_CLK_SHIFT
VREFB3BN0 DIFFIO_RX_B26p AD10 CPLD_CHAL_VAL
VREFB3BN0 DIFFIO_RX_B30n AE11 CPLD_CHAL_DATA
VREFB3BN0 DIFFIO_RX_B30p AD11 CPLD_RESP_VALID
VREFB3BN0 DIFFIO_RX_B38n AD12 CPLD_RESP_DATA
VREFB3BN0 DIFFIO_RX_B38p AE12 CPLD_RST_SYSTEM_n
VREFB3BN0 DIFFIO_RX_B27n U11 ECAT_I2C DATA
VREFB3BN0 DIFFIO_RX_B27p T11 ECAT_I2C CLK
VREFB3BN0 DIFFIO_TX_B25n AF4 PHY1 TXD0
VREFB3BN0 DIFFIO_TX_B32p AF5 PHY1 TXD1
VREFB3BN0 DIFFIO_TX_B32n AF6 PHY1 TXD2
VREFB3BN0 DIFFIO_TX_B33p AF7 PHY1 TXD3
VREFB3BN0 DIFFIO_TX_B25p AE4 PHY1 TX_CLK
VREFB3BN0 DIFFIO_TX_B28p AE7 PHY1 TX_EN
VREFB3BN0 DIFFIO_TX_B36n AH2 PHY1 RXD0
VREFB3BN0 DIFFIO_TX_B36p AH3 PHY1 RXD1
VREFB3BN0 DIFFIO_TX_B37n AH4 PHY1 RXD2
VREFB3BN0 DIFFIO_TX_B40p AH6 PHY1 RXD3
VREFB3BN0 DIFFIO_TX_B28n AF8 PHY1 RX_DV
VREFB3BN0 DIFFIO_TX_B29n AF9 PHY1 RX_ER
VREFB3BN0 DIFFIO_TX_B33n AG6 PHY1 RX_CLK
VREFB3BN0 DIFFIO_RX_B34n AF10 PHY1 CRS
VREFB3BN0 DIFFIO_RX_B34p AF11 PHY1 COL
VREFB3BN0 DIFFIO_TX_B29p AE8 PHY1 LINK STATUS
VREFB3AN0 DIFFIO_RX_B1n Y8 PHY2 TXD0
VREFB3AN0 DIFFIO_RX_B1p W8 PHY2 TXD1
VREFB3AN0 DIFFIO_RX_B3n T8 PHY2 TXD2
VREFB3AN0 DIFFIO_RX_B3p U9 PHY2 TXD3
VREFB3AN0 DIFFIO_RX_B5p U10 PHY2 TX_CLK
VREFB3AN0 DIFFIO_RX_B5n V10 PHY2 TX_EN
VREFB3AN0 DIFFIO_TX_B6n AD4 PHY2 RXD0
VREFB3AN0 DIFFIO_TX_B6p AC4 PHY2 RXD1
VREFB3AN0 DIFFIO_TX_B4n AB4 PHY2 RXD2
VREFB3AN0 DIFFIO_TX_B4p AA4 PHY2 RXD3
VREFB3AN0 DIFFIO_TX_B8p AD5 PHY2 RX_DV
VREFB3AN0 DIFFIO_TX_B2p Y5 PHY2 RX_ER
VREFB3AN0 Y4 PHY2 RX_CLK
VREFB3AN0 DIFFIO_RX_B7n AA11 PHY2 CRS
VREFB3AN0 DIFFIO_RX_B7p Y11 PHY2 COL
VREFB3AN0 DIFFIO_TX_B8n AE6 PHY2 LINK STATUS
VREFB3BN0 DIFFIO_RX_B35p T13 FE MDC
VREFB3BN0 DIFFIO_RX_B35n T12 FE MDIO
VREFB3BN0 DIFFIO_TX_B37p AG5 FE_CLKO (25 MHz)
CPLD
EEPROM
Fast Ethernet 1
Fast Ethernet 2
Misc.
The following table provides the pins used for Ethernet connectivity to the FPGA.
Phy Reset and Phy configuration:
After the FPGA is loaded, an active low reset should be asserted to the Phy devices for proper operation. The Phy
reset is provided for both Phy devices. The Phy devices reset should be assigned AG5 of the FPGA for Spark102v1
and to pin AH5 for spark-102v2.
22 | Spark-102 HW user manual V2.0
During reset the phy config pins should be set to '0' (CRS, Collision and RXDV).
5.7 CSEL Configuration There are two signals CSEL0 and CSEL1 that define the FPGA internal clock architecture. These signals
are not available to the user and are defined as default on the SOM.
6 SMARC interface Pin assignment The connector offers 314 pins which are used for:
Power
GPIOs
Fixed interfaces like GE and USB
RFU - unused pins reserved for future use.
The full pin out of the Spark is available in a dedicated document “SPARK pin out definition” available on
the Shiratech web site.
The SPARK-102 supports the SMARC standard connector. The pin out is defined in the following
document:
http://www.shiratech.com/wp-content/uploads/SPARK-102-Connector_V2.xlsx
23 | Spark-102 HW user manual V2.0
7 Mechanical considerations The mechanical dimensions are according to the SMARC standard, the full details are available at
http://www.sget.org/standards/smarc.html .
The following figures are taken from the standard to show the physical dimensions of the module and
the required layout of the carrier board. Note that the Spark is using the smaller option of 82x50.
24 | Spark-102 HW user manual V2.0
7.1 SMARC connector The SMARC connector is available from several vendors, below are the part list from Foxconn, other part
numbers from other vendors are available in the SMARC HW specification.
Vendor Vendor P/N Stack Height
Body Height
Contact Plating
Foxconn AS0B821-S43B - *H 1.5mm 4.3mm Flash Black
Foxconn AS0B821-S43N - *H 1.5mm 4.3mm Flash Ivory
Foxconn AS0B826-S43B - *H 1.5mm 4.3mm 10 u-in Black
Foxconn AS0B826-S43N - *H 1.5mm 4.3mm 10 u-in Ivory
Foxconn AS0B821-S55B - *H 2.7mm 5.5mm Flash Black
25 | Spark-102 HW user manual V2.0
Foxconn AS0B821-S55N - *H 2.7mm 5.5mm Flash Ivory
Foxconn AS0B826-S55B - *H 2.7mm 5.5mm 10 u-in Black
Foxconn AS0B826-S55N - *H 2.7mm 5.5mm 10 u-in Ivory
Foxconn AS0B821-S78B - *H 5.0mm 7.8mm Flash Black
Foxconn AS0B821-S78N - *H 5.0mm 7.8mm Flash Ivory
Foxconn AS0B826-S78B - *H 5.0mm 7.8mm 10 u-in Black
Foxconn AS0B826-S78N - *H 5.0mm 7.8mm 10 u-in Ivory
26 | Spark-102 HW user manual V2.0
Appendix 1 - Hardware devices used on the SOM
Chip Vendor Details MT29F1G01AAADD Micron NOR Flash Memory - Serial Peripheral Interface (SPI)
TXS02612 TI SDIO port expander with voltage level translation
AT24C01C Atmel I2C-Compatible (2-wire) Serial EEPROM 1-Kbit (128 x 8)
USB3300 Microchip High speed USB host device or OTG phy
TMP108 TI Low Power Digital Temperature Sensor With Two-Wire Serial Interface in WCSP
KSZ9031RN
Micrel 1G Ethernet Physical layer chip
KSZ8081MNXCA Micrel 10/100 Ethernet Physical layer chip (Used for Industrial Ethernet)
24LC16BT Microchip EEPROM for EtherCAT
M570F11NCA Altera Authentication CPLD
27 | Spark-102 HW user manual V2.0
Appendix 2 – Hardware configuration summary
Signal Description Default
BSEL [2..0] HPS Boot select
101 eMMC on SOM
111 QSPI on SOM
100 SD card on Carrier board
011 SPI on carrier board
Switches on Carrier board
MSEL [4..0] FPGA FW downloads (Only MSEL0 and MSEL1 are
available.
00000 Fast Parallel
00001 Fast Parallel/Security
00010 Fast Parallel/Compressed
00011 Fast Parallel/Security/Compressed
Switch on Carrier board
CSEL[1..0] Select the internal clock scheme for booting.
Depend on the boot chip.
Fixed, internal.
Bank 4A VCC IO Select power for BANK4A VCCIO
0 VCCIO = 1.8V
1 VCCIO = 2.5V
Switch on Carrier board
28 | Spark-102 HW user manual V2.0
Appendix 3 – Qsys parameters for the Spark The following paragraph provides the HPS configuration used in the demo version provided for the
Spark.
30 | Spark-102 HW user manual V2.0
The user can modify the configuration according to need. Care must be taken for interfaces which are
connected to hardware devices located on the module like USB, GE, I2C etc…
For interfaces which are connected directly connected to Spark interface, the configuration is open, can
should be taken to the power level provided to these interfaces.