SPI Interface and Use in a Daisy-chain Bus Configuration

- 1 -

N e v e r s t o p t h i n k i n g .

Automotive Power

Application Note, V 1.2, Feb 2002

SPI interface and use in adaisy-chain bus

configuration

by Hannes Estl

S P I i n t e r f a c e u s e d i n a d a i s y - c h a i n

Application Note 1 V1.2, 2002-02

1. AbstractThis Application Note describes the basicprinciple of the Serial Peripheral Interface (SPI)used in many Smart Power ICs and the differentways in which it can be used for communicationwith different ICs. The "daisy chain" busconfiguration will be described in detail.

2. IntroductionComplex integrated Smart Power devices cannot only control (turn on/off) the power outputstages, they can also provide configurablefunctions and detailed diagnostic of various faultconditions. To handle all this by direct controllines or hardwired configuration would mean alot of external components and pins. Toincrease functionality and at the same timereduce the amount of additional components aSerial Peripheral Interface is integrated inmodern Smart Power ICs. This SPI is asynchronous serial bus interface for receivingand sending data. If more than one IC with SPIis controlled by, e.g., a µC there are differentways to connect them, depending on therequirements of the application.

3. The SPI3.1. GeneralThe SPI is a synchronous serial interface forcontrol and data transfer between a master andseveral slaves. The interface consists of 4ports:

Serial Clock (CLK): Input for the master clocksignal. The clock signal determines the speedof the data transfer and all receiving andsending is done synchronous (clocks theinternal SPI shift register and the output driver)to this signal.

Chip Select (CS): CS activates the SPIinterface. As long as CS is high, the IC will notaccept the clock signal or data and the outputSO is in tristate. Whenever the pin is in a logiclow state, data can be transferred from the µCand vice versa (low active signal).

Serial Input (SI): Serial input port of the SPIshift register. SI information is read in on therising edge of CLK into the internal shift register.On the rising edge of the CS the input data islatched into the internal registers of the logic.

Serial output (SO): Serial output port of theSPI shift register. Diagnostic data bits areshifted out serially at this pin. SO is in a highimpedance state until the CS pin goes to a logiclow state. New diagnostic data will appear at theSO pin following the falling edge of CLK .

3.2. Functional descriptionThe "core" of the SPI is the shift register that isused to receive the data from the µC and towrite back the diagnostic information. Thisregister can be of different lengths (e.g. 8 Bit ).Two basic concepts can be distinguished.I. The SPI is only using one shift register

that is connected serial to SI/SO andparallel to the internal logic anddiagnostic registers of the IC.

II. Two independent shift registers fordata-input (SI) and data-output (SO) areused. Topology b) cannot be used indaisy chain applications and will not be

described here.The second important topic the use in a daisy-chain configuration is the behavior of the SPIwhile the input data is clocked in (CS=L).

CLKSICSSO

Serial PeripheralInterface (SPI)

Fig. 1: SPI internal logic registers

diagnosis register

n Bit SPI shift-registerSI

SO

Two basic SPI concepts

One common shift register Two independant shift registers

internal logic registers

diagnosis register

n Bit SPI shift-registerSI

SOn Bit SPI shift-register

Fig. 2: Basic SPI register topologies



A) As long as CS is "low" the SPI register isworking as a simple shift register andshifting through the SI data withoutinterpreting the different command and databits. When the CS goes back to "high" thebits in the SPI register are interpreted andthe SPI logic is activated. Diagnosticinformation is loaded when CS goes to lowand cannot be influenced in this write cycle.

B) The SPI logic does immediately checksevery incoming bit while CS is "low" (real-time arbitration). With this SPI configurationthe IC logic works (e.g. preparing specialoutput information) while the CS is low andcan therefore not be used in a daisy-chainconfiguration. It is not possible to use theSPI as a simple shift register.

In the following document only SPI topologyI)+A) is described.

3.3. Functional description

CS = H : Any signals at the CLK and SI pins areignored and SO is in high impedance state.

CS = HL :• diagnostic information is transferred

(parallel) from the diagnostic register intothe SPI shift register.

• serial input data can be clocked into the SPIshift register.

• SO changes from high impedance state tologic high or low state corresponding to theSO bits.

CS = L : SPI is working like a shift register. Witheach clock signal the actual state of the SI isread into the SPI shift register and onediagnostic bit is written out of SO.

CS = LH: • transfer of SI bits from SPI shift register into

the internal logic registers• reset of diagnostic register (optional)• SO goes back to tristate

To avoid any false clocking the serial clock inputpin SCLK should be logic low during high to lowtransition of CS.

internal logic registers

diagnosis register

n Bit SPI shift-registerSI SO

CS

CS

MSB

MSB

LSB

LSB

Serial inputdata MSB first

Serial output(diagnosis) dataMSB first

Fig. 3: SPI functional blocks for topology I)+A)

internal registerse.g. diagnosis register

internal logic of the IC

nBit SPI shift register

CLK

CS

SI

SO

high

tristateFig. 4: SPI passive while CS = H

CLK

CS

SI

SO0 1 0 1 1 1 10

0 1 0 1 1 1 10

Fig. 5: activate SPI, load diagnostic

1 1 0 1 1

CLK

CS

SI

SO0 1 0 1 1 1 10

0 1 1 0 0 1 000 1 1

low

Fig. 6: SPI active; reading and writing data



This is the basic concept of a serial peripheralinterface using one central shift register. For theuse in a daisy-chain different functions can beadded to increase the functionality or to grant asafe data transfer, but they always follow thisbasic principle.

4. Possible Bus concepts withSPI

4.1. Independent individual controlEach IC with an SPI is controlled individuallyand independently by an SPI master, as in a bi-directional point–to–point communication.

The port requirements for this topology are thegreatest, because for each controlled IC anindividual SPI at the µC is needed (CLK, CS; SI;SO). All ICs can be addressed simultaneouslywith the full SPI bandwidth.

4.2. SPI Bus with several slave ICsTo reduce the number of needed driver ports,the ICs and one SPI master can be connectedto a common bus. In this configuration themaster and all controlled ICs share the samedatalines (SO resp. SI) and clock line (CKL).Variant a): The addressing of a single IC isdone by an individual chip select line. Only onechip at the time can be active, but with the fullSPI bandwidth.

Variant b) of this bus configuration is describedin Fig. 10. Here all ICs also share the sameCS line.

Addressing of a single chip is done by the firstbits of the command word. This topology is onlypossible if all ICs check the command wordduring writing (arbitration) and SO remains intristate until the addressing is over. ICs used in

CLK

CS

SI

SO

0 1 1 0 1 0 01

Reset

0 1 1 0 00 1 1

Fig. 7 : SPI deactivated, process data, (optional:reset diagnostic)

SI

SO

CLK

CSOutput lines

SI

SO

CLK

CSOutput lines

CLK

Tx a1

Tx b1

Tx a2

Rx a1

Tx b2

Rx b1

Number of addressed ICs = n

Number of necessary control and data ports = 4 n

CLK

SPI 1

SPI n

Individual ICs are addressed by the Chip Select

Fig. 8: Individual independentcontrol of each IC with SPI (A)

SI

SO

CLK

CSOutput lines

SI

SO

CLK

CSOutput lines

CLK

Tx a

Tx b

Tx 1

Rx 1


Number of necessary control and data ports = 3 + n

Individual ICs are addressed by the Chip Select

Fig. 9:Individual Chip select andcommon data lines for all ICs (B)

SI

SO

CLK

CSOutput lines

SI

SO

CLK

CSOutput lines

CLK

Tx a

Tx 1

Rx 1


Number of necessary control and data ports = 4

Individual ICs are addressed by the command word

Fig. 10:Common SPI bus all ICs (C)



such a bus configuration cannot be used in a"daisy-chain" configuration and vice versa. Onlyone chip a time can be active and SPIbandwidth is reduced because of the addressbits.

4.3. Daisy-chain configurationThe connection of different ICs and a µC asshown in Fig 11 is called a daisy-chain. For thistype of bus-topology only one SPI interface ofthe µC for two or more ICs is needed.

All ICs share the same clock and chip selectport of the SPI master. That is all ICs are activeand addressed simultaneously. In contrary to a"classical" bus, the SO and the SI lines are notconnected together. The Data Out of the µC isconnected only to the SI of the first IC in theline. Each SO of an IC is connected to the SI ofthe next IC in the line and the SO of the last ICis then connected to the Data In of the µC. Alldata lines form a closed chain for the datatransfer with the individual ICs as chain links.The price for the low wiring effort is the reducedcommunication frequency because in one writecycle the data for all ICs in the daisy-chain hadto be transferred

4.4. Listing of the 4 conceptsThe following table provides a comparison for n(4) ICs that are controlled by a 4Mhz SPI (all 4have a 16Bit SPI and the same priority).

µC I/OPorts

max total data-ate [Mbit/s]

data rate/IC [Mbit/s]

usable bits/IC

A 4*n=16 n*5=20 5 16B n+3=7 5 5 16C 4 5 5 16-addressD 4 5/4=1,25 5/n=1,25 16

5. Basics of a daisy-chain:For applications where fast accessibility of asingle IC is not critical and where high switchingfrequencies are not necessary, the daisy-chainis a bus concept that can drastically reduce thenumber of needed µC ports and wiring effort. Ifthe individual ICs use an SPI as described in3.3. only then they can be connected in a daisy-chain configuration (Fig. 12)

In the daisy chain configuration, all ICs areaddressed by the same chip select and receiveclock signals from the same clock. They allwork synchronously.

SI

SO

CLK

CSOutput lines

SI

SO

CLK

CSOutput lines

CLK

Tx a

Tx 1

Rx 1


Number of necessary control and data ports = 4

All ICs are addressed by the common Chip Select

Fig. 11 SPI bus all ICs in a "daisy-chain" configuration (D)

TLE 6220 GP

Vs

SISO

GND

Fault

CLKCS

IN 1

IN 4

ResetPRG

OUT 1

OUT 4

TLE 6236 G

Vs

SISO

GND

Fault

CLKCS

IN 1

IN 4

Reset

OUT 1

OUT 8

TLE 6240 GP

Vs

SISO

GND

Fault

CLKCS

IN 1

IN 8

ResetPRG

OUT 1

OUT 16

µC

5V

5V

5V

5V

SPISISO

CLKCS

Fig. 12 SPI bus for 3 ICs in a "daisy-chain" configuration



The µC feeds the data and instruction bits into the SI of IC1 (first IC in the chain). The bits coming fromthe SO of IC1 are directly shifted into the SI of IC2 and the bits coming from the SO of IC2 are directlyshifted into the SI of IC3. The SO bits of IC3 (last IC in the chain) are then returned to the µC. As long asthe chip select is inactive (high) all three IC SPIs ignore the clock (CLK) and input signals (SI) and alloutputs (SO) are in tristate.

At the chip select transition to active (high low) the diagnostic data or the data requested in theprevious SPI cycle is loaded into the SPI shift register.

As long as the chip select is active the SPI register works as a simple shift register. With each clocksignal one input bit is shifted into the SPI register (SI), each bit in the shift register moves one positionfurther within the register, and the last bit in the SPI shift register is shifted out of SO. This continues aslong as the chip select is active and clock signals are applied. For example after 11 clock cycles 11diagnostic bits of IC3 have been returned to the µC. The diagnostic word of IC2 is in the middle of theshift register of IC3 and the diagnostic word of IC1 is half in IC2 and half in IC3. The command and dataword for IC3 is partly in IC2 and IC1.

After 26 clock cycles the diagnostic information of IC3 and IC2 has been fully returned to the µC, thediagnostic information of IC1 is still partly in the shift register of IC3. The command words for all 3 ICsare "in-between" the different SPIs.

After 32 clock cycles (8 + 8 + 16) all the diagnostic information had been returned to the µC and thecorrect command and data bits are in the shift register of the respective ICs. With the chip selecttransition from active to inactive (low high) all the data that is actually in the SPI shift register is loadedinto the internal logic and processed. Now the IC will react to the commands and data, SI and CLK willnot accept input signals, and SO will change to tristate.



This example also shows the danger of a invalidnumber of clock cycles. If in this preceding notexactly 32 clock signals are sent the dataloaded into the logic of the ICs will be not validand can cause problems, especially if the bits inthe SPI shift register accidentally "look like" avalid command. Unwanted behaviour of the ICcan be the result. To avoid such an unwantedbehavior (e.g. caused by a spike on the clockline or wrong number of clock cycles) a "modulocounter" can be added to the SPI. Then the SPIwill accept and process input data (at the risingCS edge) only if the number of clock signalswas a integer multiple of the modulo counter(e.g. 8 or 16). To work in a daisy-chainconfiguration the µC must send and receive xbits (x = sum of SPI bit-length of each IC in thedaisy-chain; in case 32) in a row withoutchanging the CS signal. The command anddata for the last IC in the chain (IC3 in theexample) must be the first in the bitstream fromthe µC, while the command and data for the firstIC (IC1) must be the last. The µC will receivethe diagnostic bits from the last IC in the chain(IC3) first, and the diagnostic bits from the firstIC last.

6. Application example:Daisy-chain with 3 Smart Multichannel LowsideSwitches

1x TLE 6240GP1x TLE 6220GP1x TLE 6236G

IC1 : TLE6220GPThe TLE6220GP is a 4-channel, 400mΩ SmartPower Switch with 8-bit SPI for control anddiagnostic. In addition the IC has 4 parallelinputs for control of the power stages. In thisexample the channels 1 and 2 should be turnedon in "OR" mode (SPI bit and parallel input ofthe corresponding channel are logical ORed),channel 3 and 4 should be off in "OR" mode.The load of channel 3 is disconnected and the

channel turned off in the previous cycle. Thismeans in the fault register of channel 3 OpenLoad is stored. For this operation the followingcommand / data should be sent to IC1(TLE6220GP).MSB 6 5 4 3 2 1 LSB

control data0 0 1 1 0 0 1 1

The previous command wasMSB 6 5 4 3 2 1 LSB

control data0 0 1 1 0 0 0 0

The diagnostic the IC will send back looks like:MSB 6 5 4 3 2 1 LSB

Ch 4 Ch 3 Ch 2 Ch 11 1 0 1 1 1 1 1

IC2 : TLE6236GThe TLE6236G is a 8-channel, 2,3Ω SmartPower Switch with 8-bit SPI for control anddiagnostic. In addition the IC has 4 parallelinputs for control of the power stages 1 to 4. Inthis example channels 1 to 4 and 7 should beturned on, while channels 5, 6 and 8 should beoff. The load of channel 4 and 5 is shorted(channel 4 was "on" in the previous cycle,channel 5 was off), this means in the faultregister of channel 4 the fault condition short isstored. No fault condition is stored in theregister of channel 5 because overload cannotbe detected in "off" state!.The necessary command word is :MSB 6 5 4 3 2 1 LSBCh 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1

0 1 0 0 1 1 1 1The previous command was:MSB 6 5 4 3 2 1 LSBCh 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1

1 1 0 0 1 1 1 0

The actual diagnostic word is:MSB 6 5 4 3 2 1 LSBD 8 D 7 D 6 D 5 D 4 D 3 D 2 D 11 1 0 0 0 1 1 0

Under normal operation of the channel, thediagnostic bit of a channel has the same stateas the SPI input bit. In case of a fault the databit has the inverted state. The diagnosticinformation always refers to the previouscommand, not to the command actually sent!

IC2 : TLE6240GPThe TLE6240GP is a 16-channel, 1,3Ω /400mΩ Smart Power Switch with 16-bit SPI forcontrol and diagnostic. In addition, the IC has 8parallel inputs for control of the power stages 1to 4 and 9 to 12. In this example the diagnosticfor channels 1 to 8 should be requested (in theprevious command channel 1 to 4 was turnedon with Boolean "AND" and diagnosticinformation for channel 1 to 8 was requested.

µC

RD

TD SI

SI

SO

SO

TLE 6220 GPIC1 SI SO

TLE 6236 GIC2

TLE 6240 GPIC3

8 Bit 8 Bit

16 Bit

Fig. 13 Daisy-chain with 3 ICs (8Bit + 8Bit+16Bit)



Channels 5 to 16 are off). We assume thatchannel 1 has an overload condition andchannel 5 an open load.The necessary 16-bit command / data word is :MSB 14 13 12 11 10 9 8

Command0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 LSBData

x x x x x x x x

The previous command was:MSB 14 13 12 11 10 9 8

Command1 1 1 1 0 0 0 0

7 6 4 3 2 1 LSBData

0 0 0 0 1 1 1 1

The actual-16 bit diagnostic word is:MSB 14 13 12 11 10 9 8

Ch 8 Ch 7 Ch 6 Ch 511 1 1 1 1 1 0 1

7 6 5 4 3 2 1 LSBCh 4 Ch 3 Ch 2 Ch 1

1 1 1 1 1 1 1 0

These were the commands, data and diagnostichow they are sent when only one chip isaddressed by SPI. In our example 3 ICs areused in a daisy-chain. In this case the threecommand / data words have to be lined up andsent within one single chip select active cyclewith 32 clock signals (8 + 8 + 16). Thediagnostic info received will also be one singlequeue with 32 bits of diagnostic data.For this special application example with all theabove mentioned conditions the bitstreamshowed in Feg.14 has to be sent to the first IC(and in this way to the whole daisy-chain).

7. ConclusionFor applications with slow or infrequent SPI datatransfer the daisy-chain is a Bus topology thatcan reduce the communication I/O needs to 4pins, independent of the number of addressedICs. The only requirement is a µC that can sendand receive a bitstream of variable bit countwithin one chip select cycle (according to theSPI timings) .

For this specialapplication example withall the previouslymentioned conditions thefollowing bitstream has tobe sent to the first IC (andsimilarly to the wholedaisy-chain): (x ... don't care)

15 MSB 0

14 30 0

13 29 0

12 28 0

11 27 0

10 26 0

9 25 0

8 24 0

7 23 x

6 22 x

5 21 x

4 20 x

3 19 x

2 18 x

1 17 x

0 16 x

7 15 0

6 14 1

5 13 0

4 12 0

3 11 1

2 10 1

1 9 1

0 8 1

7 7 0

6 6 0

5 5 1

4 4 1

3 3 0

2 2 0

1 1 1

0

LSB 1

Fig. 14 32 bitdownstream data

The bitstream comingfrom the last IC in thechain (the diagnostic fromall ICs in the chain) lookslike this

15 MSB 1

14 30 1

13 29 1

12 28 1

11 27 1

10 26 1

9 25 0

8 24 1

7 23 1

6 22 1

5 21 1

4 20 1

3 19 1

2 18 1

1 17 1

0 16 0

7 15 0

6 14 1

5 13 0

4 12 0

3 11 0

2 10 1

1 9 1

0 8 0

7 7 1

6 6 1

5 5 0

4 4 1

3 3 1

2 2 1

1 1 1

0

LSB 1

Fig.15 32 bitupstream data



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SPI Interface and Use in a Daisy-chain Bus Configuration

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