SPICE Analysis of Low-Loss Control IC-Power MOSFET

Chipset for High-Frequency DC-DC Converter Design

Jeff Berwick, John Huang,

Wayne Grabowski and Richard K. WilliamsSiliconix, Inc

Intusoft, IncCharles Hymowitz and Steve Sandler

Overview:

High frequency power supply design Motivation and Challenges Methodology: Having the right tools for the job

Selecting a MHz-range MOSFET Use of the “power loss curve” Performance of the new Si6801 high speed

complementary power MOSFET pair

Overview (Continued) System Modeling in IsSpice

The new Si9145 controller macromodel Detailed modeling example Behavioral modeling example

1MHz Buck simulation schematic

Simulation Results Startup Step Response Efficiency

Conclusions

High Frequency Challenges:

Efficiency Decreases MOSFET selection is more difficult Layout Parasitics are critical Measurements are limited PC Breadboard modifications are difficult

Better Design Tools are Needed

1MHz SMPS Design Tools

Power Loss Curve For MOSFET Selection Gate Charge and RDSON determine efficiency

IsSpice For System Design & Evaluation IsSpice Models for Power FETs, Control IC

PC Breadboarding for Calibration & Tuning

Selecting a MOSFET Power Switch Loss vs. VGS :

P = I2RMS RDS D + QG VGS f

Si6801 Power Loss, QG, RDS vs VGS

0

5

10

15

20

25

30

35

40

0 1 2 3 4 5 6 7VGS

Po

we

r L

os

s (

mW

)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

RD

S O

N (

Oh

ms

)

RDS ONQG

1MHz

1.4 MHz

500 KHz

Ga

te C

ha

rge

(n

C)

3

0

12

6

9

Si6801 Power Loss, QG, RDS vs VGS

0

5

10

15

20

25

30

35

40

0 1 2 3 4 5 6 7VGS

Po

we

r L

os

s (

mW

)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

RD

S O

N (

Oh

ms

)

RDS ONQG

1MHz

1.4 MHz

500 KHz

Ga

te C

ha

rge

(n

C)

3

0

12

6

9

MOSFET Loss Comparison

Technology Comparison: 1 MHz Power Loss

10

20

30

40

50

1 2 3 4 5 6 7

VGS

Co

nd

uc

tio

n +

Ga

te C

ha

rge

L

os

s (

mW

)

Si6801: High Frequency

Si6552: Low VT

Si6542: Conventional

Technology Comparison: 1 MHz Power Loss

10

20

30

40

50

1 2 3 4 5 6 7

VGS

Co

nd

uc

tio

n +

Ga

te C

ha

rge

L

os

s (

mW

)

Si6801: High Frequency

Si6552: Low VT

Si6542: Conventional

Si6801 High Frequency MOSFET: Maximum Gate Bussing Reduces Distributed RG

System Modeling in IsSpice

Power MOSFET Models with accurate QG

Pulse-by-pulse Controller Model Detailed models for output stages Behavioral models for digital functions

Passive Component Models Nonlinear Magnetics Capacitors with ESR

PC Board Parasitics: R,L,C

Si9145 Controller Macromodel

BehavioralLogic

Detailed Output Stage

Si9145/Si6801 Pch Switching Speed

2

1

33.50U 33.55U 33.60U 33.65U 33.70U

WFM.1 V(22) vs. time in

6.000

4.000

2.000

0

-2.000

V(2

2) in

V

olts

6.000

4.000

2.000

0

-2.000

V(4

2) in

V

olts

DrainGate

DrainGate

18nS

Measured

Simulated

18nS

Variable Delay Comparator Model

IDEAL COMPARATOR

DIFFERENCE: K(V1 - V2) ABS

VARIABLE RES

VIN

VOUT

IsSpice Results: Delay vs. O.D.

100N 300N 500N 700N 900N

COMP DELAY vs. OVERDRIVE

TIME (SEC.)

0

3V

-VIN

+VIN

VOUT

100mV 10mV500mV

+/- Overdrive:

1MHz Sync Buck Schematic

Non-linear Magnetics

ESR

Input

Output

Si9145

Si6801

IsSpice Transient Simulation Results

Measured vs. Simulated: Startup transient Step response Steady-state efficiency

Si9145 Oscillator Startup

0 100uS 200uS

Measured

Simulated

300mA Load Step Response:

Measured

Simulated

0 100uS50uS

Measured

Simulated

MultilayerCeramic

COUT(25m ESR)

TantalumCOUT

(500m ESR)

Vertical: 100mV/DivHorizontal: 10uS/Div

Steady-State Efficiency AnalysisSi9145/Si6801 Simulated vs. Measured Efficiency @ Vin = 4V

60

65

70

75

80

85

90

95

100

0 200 400 600 800 1000

Output Current (mA)

Eff

icie

ncy

%

IsSpice4

Measured

Simulated Input Power Partitioning % Power loss vs. Input power @ Vin=4V

Conclusions:

High Frequency shifts design challenge MOSFET selection requires RDS and QG Parasitics affect performance critically

Power Loss partitioning depends on ILOAD

Low ILOAD emphasizes gate loss, bias currents High ILOAD emphasizes switch RDS, RWINDING

Pulse-by-pulse simulation is now practical