SPIE Proceedings [SPIE Microlithography 2003 - Santa Clara, CA (Sunday 23 February 2003)] Advances...

Resist Reflow for 193nm Low K1 Lithography Contacts

Patrick Montgomery, Kevin Lucas1, Kirk Strozewski1, Lena Zavyalova1, Grozdan Grozev2, Mario Reybrouck2, Plamen Tzviatkov3, Mireille Maenhoudt4

Motorola Digital DNA Labs EMEA assigned to IMEC, Leuven, Belgium

1 Motorola Advanced Products Research & Development Lab, Austin, TX 78721 2 ARCH Chemicals assigned to IMEC, Leuven, Belgium

3 ARCH Chemicals, Rhode Island 4 IMEC, Leuven Belgium

ABSTRACT

Contact patterning for advanced lithography generations is increasingly being viewed as a major threat to the continuation of Moore's Law. There are no easy patterning strategies which enable dense through isolated contacts of very small size. Lack of isolated contact focus latitude, high dense contact mask error factor and incredibly low defectivity rate requirements are severe issues to overcome. These difficulties mean that new and complex patterning methods for contacts at the 90nm and 65nm device generations are being considered. One possible option for improving the process window of contact patterning is resist reflow. Resist reflow can supplement almost any other optical extension method for contact lithography. Previous results have shown the significant benefits of this method for CD control on semi-dense and isolated contact for the 100nm device generation [1]. This work extends the previous work by investigating very dense pitch through isolated contact patterning at 193nm low K1 lithography regimes. The encouraging overall CD control and process window of reflowed contacts using the ARCH TIS2000 bilayer resist system is analyzed through pitch for different imaging options. An investigation of the capability of resist reflow in combination with optimized reticle and illumination for the 65nm device generation is also presented as are details of defectivity levels for reflowed contacts on 90nm device products.

1. Introduction Although good 193 nm resists are available for 90 nm node front-end lithography, back-end lithography is still a challenge using standard single layer resist processes. Currently the International Technology Roadmap for Semiconductors (ITRS) lists the contact resist CD for 65nm device technologies as 100 nm [2]. Even with high NA (>0.7) 193 nm exposure tools, simulations indicate that these contact hole sizes will be difficult with standard processing techniques. Therefore, we investigate the feasibility of using a resist reflow technique to obtain small contact hole sizes. Resist reflow is a very simple technique by which the resist is baked above the glass transition temperature (Tg) after the typical contact hole pattern has been developed. This causes resist flow which results in smaller final contact hole dimensions. The reflow process offers improved focus/exposure latitudes because it allows the standard lithography contact processes to target larger initial (before reflow) dimensions on the wafer. These process window improvements are illustrated by experiments in a later section. Furthermore, in this work we investigate illumination optimization, through pitch performance, process window improvement, proximity effects on SRAM, defectivity, and CD uniformity for 100nm-130nm CDs at 200nm pitch and above. Most work reporting on this subject describes resists and processes that are specifically designed for resist reflow [3,4,5,6]. We however, want to work with a resist which is also suitable for gate applications, standard contact hole printing and trench printing. For this work the Thin Imaging System 2000 from ARCH Chemicals (TIS2000) is chosen for investigation. This resist provides good process latitudes and excellent etch selectivity and has a much lower Tg (approximately 120ºC) compared to standard single layer 193 nm resists which have Tg's of approximately 170-200ºC and require very high temperatures to flow the resist [3]. In this work we focus on the use of reflow with a standard binary intensity mask. The mask has no special design elements such as sub-resolution assist features.

Advances in Resist Technology and Processing XX, Theodore H. Fedynyshyn, Editor,Proceedings of SPIE Vol. 5039 (2003) © 2003 SPIE · 0277-786X/03/$15.00

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2. Principle of TIS 2000 The process flow for TIS2000 is shown in figure 1a [1]. For comparison purposes the process flow for a single layer resist on organic BARC process is shown as well (figure 1b). TIS2000 consists of a relatively thick underlayer and a thin imaging layer. The underlayer is based on a polymer that crosslinks when it is baked. The n and k-values of the underlayer are optimized in order to have optimal reflection suppression [7]. The imaging layer contains an imageable polymer with silicon. First the imaging layer is exposed and wet developed as a standard photoresist. Then the underlayer is dry etched using O2- or O2/SO2- chemistry. Using this etch chemistry, the imaging layer etches typically 10 times slower than the underlayer due to the silicon in the imaging layer. Due to the high selectivity, the imaging layer can be thin and the underlayer relatively thick. Therefore this system is proven to be a good candidate for dual damascene processing in order to overcome severe topography [8,9]. After the underlayer etch, the substrate is etched. The underlayer is designed to have excellent etch resistance to poly and oxide etch chemistries. In a single layer approach (figure 1b) the resist is designed to have good imaging capabilities and substrate etch resistance. Since both BARC and the resist are hydrocarbon based, without any silicon, the etch selectivity between BARC and resist is almost 1:1. For this reason the thickness of the BARC must be kept minimal in order to retain enough resist thickness after the BARC etch to withstand the substrate etch. Comparing the process flow of TIS2000 with the flow of a conventional resist system, it can be seen that the TIS2000 flow is not more complex than the flow for a single layer on BARC approach.

figure 1a: TIS200 process figure 1b: Standard resist process

Baking the resist above the Tg results in flowing of the resist. The flow properties are used to shrink the dimension of the contact hole: after the typical contact hole pattern has been developed, the resist is baked. The resist flow results in smaller final dimensions. Standard 193 nm single layer resists employ polymers with Tg-values higher than 170ºC, requiring exceptionally high bake temperatures to induce resist flow. Moreover, in many cases the window between the polymer-Tg and its thermal decomposition temperature is quite narrow. In contrast, the Tg of the polymer used in TIS2000IL-5 is about 80°C lower than its thermal decomposition temperature. The low polymer-Tg of 120ºC ensures

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that the flow bake can be done on a low temperature hotplate for which track vendors can guarantee better temperature control.

3. Reflow Bake Optimization Though previous work was done to determine the flow properties of this formulation of TIS 2000, supplementary experiments were done to verify earlier findings for application to smaller CDs and pitches [1]. Experiments were done at IMEC on an ASML PAS5500/950 with 0.63NA and conventional illumination with 0.5σ. Because the resist formulation is the same as in previous work, we investigate a small window of temperature settings that yield good results for larger feature sizes and pitches. Starting with a 140nm CD before reflow at 280nm and isolated pitches both 129°C and 131°C result in workable time/temperature combinations to produce a ~30-40nm CD shrink (figure 2a and b). Both of these temperatures also yield good CD uniformity results that will be presented in this work. For all experimental data to follow we use a reflow bake of 129°C for 60 seconds as this combination yields >30nm of reflow bias for both dense and isolated pitches. For a bake temperature of 131°C we find the iso-dense bias becomes large, and the reflow bias for isolated contacts becomes uncontrollable. The 131°C bake temperature results in closed contacts for 90s and 120s bake times. Closed contacts were not observed for any of the 129°C bakes.

figure 2a: CD Shrink vs. Bake Time at 129°C figure 2b: CD Shrink vs. Bake Time at 131°C

4. Illumination Optimization Aerial image simulations were carried out to assist in determining the optimum illumination for pitches from 200nm to isolated with 0.63NA. Normalized image log slope (NILS) simulations in figure 3a illustrate that conventional illumination will likely suffer in exposure latitude for pitches ≤ 250nm while annular illumination (figure 3b) appears to be feasible for the 250nm pitch and above. This also holds true for the most aggressive outer sigma annular setting at 0.63NA. Regardless of the illumination setting, the use of 0.63NA and a binary mask does not offer enough resolution to image 200nm pitch contacts with significant process latitudes. Image CD simulations show that annular illumination will require substantial mask biases for pitches greater than ~300nm as compared to conventional illumination (figure 4). Experimental data with a binary mask shows little difference in process latitudes for annular illumination settings of 0.87σo/0.57σi, 0.85σo/0.5σi, and 0.8σo/0.5σi (figure 5). Experimental and simulation data led us to choose an illumination setting that would offer some compromise in process latitudes between fully dense and semi-dense/isolated pitches. The majority of experimental data presented is, therefore, produced with annular illumination 0.8σo/0.5σi. Though the reflow process can help to achieve 100nm contacts at these illumination conditions, higher NA will be needed to resolve pitches below ~250nm.

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figure 3a: NILS vs. Partial Coherence Conventional figure 3b: NILS vs. Inner sigma Annular as a function of pitch as a function of pitch

Image CD vs Pitch

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200 250 300 350 400 450 500 550 600 650 700 750 800Pitch (nm)

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Annular 0.87/0.57 Annular 0.85/0.5Annular 0.8/0.5 Annular 0.8/0.3Conventional 0.8 Conventional 0.7Conventional 0.6 Target CD

figure 4: Image CD vs. Pitch as a function of illumination AI simulations, 125nm CD Targeted at 250nm Pitch



figure 5: Experimental process Windows for 130nm CD, 260nm and isolated pitches

5. Results and Disscussion

5.1 Process Window Improvement The foremost goal of this work is to produce improvements in focus and exposure latitude at a given CD vs. those obtainable without reflow. This benefit can be seen through pitch, but for demonstration purposes we look specifically at the 325nm pitch. Annular illumination NILS simulations show a dip at this pitch, and aerial image contrast begins to suffer as well. Our experiments indeed confirm that this pitch yields only marginal process latitudes without reflow, but the process window area increases dramatically after the reflow process. Notably depth of focus at 10% exposure latitude increases from 0.4µm to 0.63µm, or 57% (figure 6). Similar increases in process window area are seen through pitch. This effect is due to the growth in process window of an upsized contact. Figure 7 demonstrates this effect for 100nm contacts at 200nm pitch imaged in 300nm of a single layer state-of-the-art resist without reflow.

figure 6: Exposure latitude vs. depth of focus for figure 7: Exposure latitude vs. depth of focus for 130nm contacts at 325nm pitch with and without 100nm and 120nm contacts at 200nm pitch for a single resist flow. 0.8/0.5 annular, 0.63NA. layer resist. 0.75NA, 0.8/0.5 quasar illumination.



At tight pitches a number of interdependent factors can limit the ability of the reflow process to enhance process window area. Our experiments with a 265nm thick imaging layer demonstrate that at a pitch of 250nm targeting a final CD of 130nm in resist, there is not enough resist to flow, and thus little process window benefit is obtained. If the resist thickness is increased, the minimum pitch that can benefit from reflow will decrease. Nonetheless, there will always be a minimum pitch that is relative to the starting CD. 5.2 Defectivity and Proximity Effects for SRAMs For the 90nm node contact level reflow is well defined and understood using ARCH TIS2000. All process characterization work indicates that reflow enhances process latitudes where feature geometries allow contact upsizing at lithography. It is, therefore, prudent to move on to characterizing issues relative to yield of real devices. We have run an analysis of defectivity and proximity effects on a 90nm node pilot line production wafers. Defectivity levels for the 90nm node must be below one failure per billion contacts/vias for acceptable device yield. In production fabs and pilot lines much effort is devoted to ensuring that this defectivity goal is reach. Any new nonstandard process that negatively affects defectivity lacks credibility and will not be used regardless of the benefits to lithography. Our goal is to compare the reflow process to a non-reflow process, and determine if there is any statistical difference in the defectivity levels of the two processes. We compared wafers with post develop bake temperatures of 100°C, 110°C, 120°C, 125°C, 130°C, and normalized them all to the mean defectivity density level of the 100°C PDB temperature, i.e. no reflow. Using a state-of-the-art pattern defect inspection system we see that the reflow process does not statistically add to defect density (figure 8). We also used the inspection system to search for oversized (un-reflowed) contacts, and this problem was not seen.

figure 8: Defectivity statistics, pattern defect density versus bake temperature. A 90nm node pre-production SRAM bitcell is then examined as this design contains a representative range of proximity sensitive pitches. The SRAM will also demonstrate how well our current OPC works with the reflow processes. The images in figure 9 show no proximity issues. Moreover it is evident that the contacts scale quite well after reflow making the need for large OPC changes unnecessary. We also find that due to the single or bidirectional dense pitch nature of real devices, tighter pitches will benefit more from the use of resist flow than standard test arrays where the pitch is the same in many directions.



figure 9: SRAM top down CD SEM images before and after etch, with and without reflow

5.3 CD Uniformity for 100nm Contacts From our defectivity study we know that there are no extreme cases of CD non-uniformity. The next step is to measure CD uniformity across uniformly patterned wafers. The feasibility of using reflow in production is reliant on maintaining or improving our standard process CD uniformity. We consider three time/temperature combinations of post develop bake. For each of the bake settings three wafers are measured. One reference wafer without reflow is exposed. 195 points across each wafer are measured at 280nm and isolated pitches with a 140nm starting CD. Uniformity is reported as a 3 sigma deviation from the mean CD. The matrix of tested conditions is shown in figure 10.

Post Develop Bake Time Post Develop Bake Temperature 1 Wafer No Bake 1Wafer No Bake 60 seconds 3 Wafers 129°C (2X), 3 Wafers 131°C 90 seconds 3 Wafers 129°C

figure 10: Reflow conditions used for CD uniformity study. Our standard time and temperature setting of 129°C/60s was exposed twice with about 2 weeks separation to look at medium term repeatability. Figure 11 shows that the repeatability is fair with a 2% increase in dense mean CD and 3% in isolated mean CD. Dense contact uniformity worsened with a 3σ value increase of 5.5%, while isolated uniformity improved with a 4% decrease in 3σ. We have learned through this process that our standard time/temperature combination yields slightly worse CD uniformity as compared to a non-reflow process. Other tested time/temperature combinations produced positive results as can be seen in figure 11. The 129°C/90s bake, which has a similar iso/dense bias as the 60s bake, yields a 17% improvement in CD uniformity for dense contacts, and 22% improvement for isolated. If a larger iso/dense bias is acceptable, the 131°C/60s bake is beneficial because of the 23% improvement in dense contacts CD uniformity and 58% improvement for isolated. Moreover the reflow data demonstrates that, given optimized bake parameters, CD uniformity can be improved over a standard non-reflow process.



figure 11: CD Uniformity and mean CD vs. reflow bake time/temperature

5.4 Proximity for 100nm Contacts Due to the nature of OPC, it is not possible to correct all feature size and shape errors independent of the process. We study proximity induced CD errors by comparing a non-reflow CD vs. Pitch curve to curves obtained with various reflow bake time/temperature combinations. Our data encompasses pitches from 280nm to isolated at a starting CD of 140nm targeted at the dense pitch. All curves are normalized to the non-reflow CD at 280nm pitch. At a reflow bake temperature of 129°C we investigate bake times of 40s, 90s, 120s, and 150s. At bake times from 40s to 90s no significant difference is seen in CD range through pitch versus the non-reflow process. If we focus on a partial range of CDs from dense to ~425nm, we see an improvement in proximity over a process without reflow. At bake times longer than 90s we observe a marked increase in proximity induced CD deviation from the target. For a bake temperature of 131°C only 40s and 60s bake times were studied due to contact closure at longer bake times. The results for this temperature are very similar to those of the 129°C bake (figures 12a and b).

figure 12a: Normalized (to no reflow CD) deviation figure 12b: Normalized (to no reflow CD) deviation from mean CD at 280nm pitch vs. Pitch as a function from mean CD at 280nm pitch vs. Pitch as a function of reflow bake time at 129°C. of reflow bake time at 131°C.



6. Ongoing and Future Work

Recent work concentrates on obtaining smaller CDs and pitches to target representative features for the 65nm node. Exposures at IMEC on an ASML PAS5500/1100 with 0.75NA and Quasar illumination 0.89σo/0.65σi target 100nm CDs before reflow at 200nm pitch. We obtain 0.45µm depth of focus at a single energy dose (figure 13). If this CD is upsized to the optimized CD to be flowed down to 100nm, we will obtain increased process latitudes that could be feasible for process characterization. We, however, are investigating smaller final CDs, and desire a 100nm starting CD. New formulations of the imaging layer are being investigated as they have optical properties better suited to 65nm node dimensions. The new resist formulations have different thermal properties from those used in this work, and will require further experimentation to determine the materials’ flow properties.

figure 13: 100nm CD at 200nm pitch through focus without reflow

7. Conclusions Our work has emonstrated significant process latitude improvements using the TIS 2000 bilayer resist system in combination with resist reflow. Experiments with a binary mask yield ~50% improvement in depth of focus at 10% exposure latitude for 130nm contacts at 325nm pitch. Similar benefits to process window are observed through pitch as well as at smaller contact hole sizes. Practically any contact or via process can benefit from this process. It is ideal for processes that provide marginal latitude under standard patterning conditions. At the 90nm node, binary masks may offer sufficient process window area to provide an effective solution, but feature sizes and pitches required at the 65nm node are likely too aggressive for a simple binary mask exposed with ArF. Costly and complicated mask designs are one method of overcoming the problem, but resist flow is potentially a cost effective way to achieve the same result. Common concerns for employing a novel process to produce functional devices such as CD uniformity, proximity and defectivity have been addressed. Through process optimization, we demonstrated that across wafer CD uniformity can be improved. Proximity was studied in both test arrays and on a real device design. Proximity through pitch did not yield a statistically significant difference in defect density as compared to a non-reflow process. SRAM contact patterns on pilot line production wafers were analyzed after being processed through etch using the reflow process, and no proximity issues arose. In fact, real designs seldom suffer from the close proximity of multiple contacts that is common in test arrays. This close proximity can cause the benefit offered by the resist flow process to be pitch-limited. We find that in a test array we are limited to a certain pitch relative to the starting CD because there is not enough resist in regions adjacent to the contact hole. A smaller pitch can potentially benefit from reflow in a device design that incorporates contacts with only two (2) or even three (3) nearest neighbors. Finally defectivity was shown not to suffer as a function of resist flow.



It is evident that NA >0.7 is needed to gain enough resolution for the minimum pitch of the 65nm node. We find that a pitch of 200nm with 100nm contacts is possible with current resist formulations. The thermal properties are well understood, so it is expected that 100nm CDs showing good process windows can be produced with the reflow process from upsized contacts. As newer materials are being characterized that offer better optical properties relative to feature sizes of the 65nm node, we see strong potential for utilizing resist flow at the 65nm node.

8. References [1] V. Van Driessche, et. al. 100nm generation contact patterning by low temperature 193 nm resist reflow process. Proc. of SPIE Vol. 4690, 2002. [2] 2001 ITRS ASIC Lithography Roadmap. [3] K. Lucas, M. Slezak, M. Ercken. F. Van Roey, ‘193nm contact photoresist reflow feasibility study’, Proc. of SPIE, Vol. 4345 (2001). [4] B. Kim, S. Lee, D. Yeop, J. Lee, J. Nam, ‘The control of resist flow process for 120 nm small contact hole by latent image’, Proc. of SPIE, Vol. 4344 (2001). [5] Y. Kang, S. Woo, S. Choi, J. Moon, ‘Development of resists for thermal flow applicable to mass production’, Proc. of SPIE, Vol. 4345 (2001). [6] J. Kim, J. Jung, C. Koh, K, Baik, K. Shin, ‘Novel Routes towards Sub-70 nm Contact Windows by using new KrF photoresist’, Proc. Of SPIE, Vol. 4345 (2001). [7] M. Neisser, J. Biafore, P. Foster, G. Spaziano, T. Sarubbi, V. Van Driessche, G. Grozev and P. Tzviatkov, ‘Adjustment of Bilayer Optical Properties and the Effect on Imaging and Etching Performance’, Proc. of SPIE, Vol. 4000, p. 942 (2000). [8] I. Pollentier, M. Maenhoudt, V. Wiaux, D. Vangoidsenhoven and K. Ronse, ‘Dual Damascene Back-End Patterning Using 248 and 193 nm Lithography.’, Proc. of ARCH Interface, p. 265 (2000). [9] M. Maenhoudt, V. Wiaux, I. Pollentier, D. Vangoidsenhoven, K. Ronse, M. Vanhove, ‘Lithography aspects of dual damascene interconnect technology’, Proc. of SPIE, Vol. 4404 (2001).



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