Hideo Ohno1,2,3,4
1 Laboratory for Nanoelectronics and Spintronics, Res. Inst. of Electrical Communication, Tohoku University2 Center for Spintronics Integrated Systems, Tohoku University
3 Center for Innovative Integrated Electronic Systems, Tohoku University4 WPI-AIMR, Tohoku University
http://www.csis.tohoku.ac.jp/
Spintronics Nano-Devices for VLSIs
5th international Conference on Superconductivity and MagnetismApril 24 – 30, 2016, Fethiye, Turkey
Work supported in part by the FIRST Program from JSPS, ImPACT from JST,and by the R & D for Next-Generation Information Technology of MEXT
Collaborators: S. Fukami, C. Zhang, T. Anekawa, H. Sato, S. Kanai,F. Matsukura, S. Ikeda, T. Hanyu and T. Endoh
研究開発の目的
PC
Network server
Logic LSIs
Car electronics
Game machine
TV
Digital Radiography
Aircraft
Artificial satellite
Mobile phone
Tomographic equipment
Rocket
$141 billion($20 billion)
Car
Tablet PC
Audio-VideoEquipment
$227 billion($16 billion)
Audio-VideoEquipment
$227 billion($16 billion)
Automobile
$1773 billion($340 billion)
Automobile
$1773 billion($340 billion)
SpaceAircraft
$338 billion($14 billion)
SpaceAircraft
$338 billion($14 billion)
Medical, HealthEquipment
$273 billion($23 billion)
Medical, HealthEquipment
$273 billion($23 billion)
SmartCommunity
$104 billion($15 billion)
SmartCommunity
$104 billion($15 billion)
Computer
Computer Communication
Equipment
$552 billion($37 billion)
Videocamera
Digital camera
Information source:Hitachi Techno-Information Services, Ltd
Logic VLSIs
WW Market in 2012(JPN Market in 2012)
Smart City
Renewable energy
Electric generation
Electricity storage
IOT
IOT(Internet of Things)
$1300 billion($111 billion)
IDC Japan http://www.idcjapan.co.jp/Press/Current/20150205Apr.html(also 20141118/Apr. html)
Challenges VLSI Technology Face
Power Consumption
MP
U P
ow
er
Consu
mption(W
)
Year
Interconnect wiring
Memory
Logic
Logic
Leakage Current
Signal bottleneck
Memory
Interconnection Delay
Active power
Standby power by leakage current
Toward Nonvolatile CMOS VLSI
Logic‐in‐Memory Architecture by fusion between logic circuits and MTJs (Reduction of device number and interconnect wiring length)
Zero standby power of memory by non‐volatile spintronics devices
Low Power Consumption
Low Power, High Performance, Low Cost
Spintronics Logic‐in‐Memory VLSIs
Logic VLSIs with Spintronics Memory
Present Logic VLSIs
Logic
Logic
Logic
Volatile memory
Leakage current
Si sub.
Si sub.
Si sub.
Non‐volatile memory
Non‐volatile memory
Nonvolatile Memories
Magnetic Tunnel Junction (MTJ)
Low resistance “0”
High resistance “1”
Features of non‐volatilefor memory device
Flash FRAM Spin Device
Access Speed
Non destructive Read
Write Endurance ×
Scalability
Operation Voltage ×
Comparison: ReRAM, PCRAM, and STT‐MRAM (Spin)
ReRAM PCRAM STT-MRAM
Program Current
Program Time
Read Time
Retention
Endurance
10-4A 10-4A 10-5A
50ns 100ns 0.5ns-10ns
< 5ns < 5ns < 5ns
10yrs 10yrs 10yrs
109 - 1012106 1015
6
Nonvolatile Memories
E E
Half Metal
2
2
12(TMR) istanceMagnetoRes Tunnel
PP
RRR
P
PAP
Ferromagnet 1 Ferromagnet 2Insulator
Room temperature TMR: Miyazaki and Tezuka (Tohoku U.), J. Mag. Mag. Mat. 1995 and Moodera et al. Phys. Rev. Lett. 1995.
Magnetic Tunnel Junction
Parallel
Antiparallel
Required Properties
High tunnel magnetoresistance ratio > 100%
High thermal stability = E/kBT > 60
Unlimited endurance
Low switching current
High speed read and write
High temperature tolerance ~ 400 oC
Scalability 40 nm → 20 nm → 10 nm
TMR ratio of MTJs
0
100
200
300
400
500
600
700
1994 1996 1998 2000 2002 2004 2006 2008 2010
トンネル磁気抵抗比
(%)
年
AlOx‐barrier
CanonANELVA & AIST
MgO‐barrier
AIST
Tohoku‐Hitachi
604%(1144%@5K)
IBMAIST
AIST
@ RT
TMR
ratio
(%)
year
0
10
20
30
40
50
60
70
80
90
100
0 0.01 0.02 0.03 0.04 0.05
α
E/kT
Ic0=50uA
Ic0=100uA
Ic0=200uA
α=0.0165α=0.033
0
10
20
30
40
50
60
70
80
90
100
0 0.01 0.02 0.03 0.04 0.05
α
E/kT
Ic0=50uA
Ic0=100uA
Ic0=200uA
α=0.0165α=0.033
Ic0 and =E/kBT
in-plane
*0
*
2eff
C effB
eff eff
E K V
eI K Vg
K K
E
Parallel Antiparallel
Thermal fluctuationkBT
E
Parallel Antiparallel
Thermal fluctuationkBT
perpendicular
E
Parallel Antiparallel
Thermal fluctuationkBT
E
Parallel Antiparallel
Thermal fluctuationkBT E
Parallel Antiparallel
Thermal fluctuationkBT
E
Parallel Antiparallel
Thermal fluctuationkBT
Ic0 and =E/kBT
VKKE ecrystallinshape
02
eff
C effB
eff eff
E K V
eI K Vg
E
K K
Comparison of MTJs (early 2010)
Type Stack structure(nm)
Size(nm)
MR (%)
RA(Ωμm2)
JC0(MA/cm2)
IC0(μA) ∆=E/kBT IC0/∆ Ta (oC) Ref.
i-MTJ CoFeB(2)/Ru(0.65)/CoFeB(1.8) SyF 100x200 >130 ~10 2 ~400 65 ~6.2 300-
350J. Hayakawa et al., IEEE
T-Magn., 44, 1962 (2008)
p-MTJL10-
FePt(10)/Fe(t)/Mg(0.4)/ MgO(1.5)/L10-FePt(t)
Blanket 120(CIPT)
11.8k - - - - 500M. Yoshizawa et al.,
IEEE T-Magn., 44, 2573 (2008)
p-MTJL10-
FePt/CoFeB/MgO(1.5)/ CoFeB/Co based
superlattice
Blanket 202(CIPT)
- - - - - -H. Yoda et al.,
Magnetics Jpn. 5, 184 (2010) [in Japanese].
p-MTJ [Co/Pt]CoFeB/CoFe/MgOCoFe/CoFeB/TbFeCo Blanket 85-97
(CIPT)4.4-10 - - - - 225 K. Yakushiji et al., APEX
3, 053033 (2010)
p-MTJ [CoFe/Pd]/CoFeB/MgO/CoFeB/[CoFe/Pd]
800x800N
100(113)
18.7k(20.2k) - - - - 350
(325)K. Mizunuma et al.,
MMM&INTERMAG2010
p-MTJ CoFeB (1)/ TbCoFe (3) 130 φ ~15 4.7 650 107 6.08 - M. Nakayama et al., APL 103, 07A710 (2008)
p-MTJ L10-alloy 50-55 φ - - - 49 56 0.88 - T. Kishi et al., IEDM 2008
p-MTJ Fe based L10 (2)/CoFeB (0.5) - - - - 9 - - -
H.Yoda et al., Magnetics Jpn. 5, 184 (2010) [in
Japanese].
p-MTJ CoFeB(~1.7) 40 φ 124 18 3.9 49 43 1.14 350S. Ikeda et al.,
Nat. Mat.9 (2010) 721.
FePtFePt & Co-based SLCo/Pt & TbFeCoCoFe/PdTbFeCoL10 alloyFe-based L10
Perpendicular MgO-CoFeB MTJ
interface perpendicularanisotropy
JC0 = 3.8 MA/cm2
(IC0 = 48 μA) E/kBT ~ 40TMR ratio = 110%Ta = 350oC
S. Ikeda et al., Nature Mat. 9, 721 (2010)
1.6 nm0.9 nm1.0 nm
Co20Fe60B20
K. Nakamura et al., Phys. Rev. B, 81, 220409(R) (2010)
Perpendicular anisotropy at the CoFeB/MgO interface
15
Co‐Fe atoms on O sites in MgO
MgO(2.1nm) crystal
[110]
crystal[100]
FeCo
(100)(100)
5 Å
OMg
FeCo
Collaborative work with Prof. Ikuhara‐Lab., Nano Lett. 16, 1530 (2016).
MgO‐Fe system
• High TMR ratio and interfacial anisotropy are predicted by first‐principles calculation.W. H. Butler et al., Phys. Rev. B 63, 054416 (2001). J. Mathon et al., Phys. Rev. B 63, 220403 (2001).K. Nakamura et al., Phys. Rev. Lett. 102, 187201 (2009).
Structural analysis for high performance CoFeB‐MgO MTJ stack confirmed that Fe(Co) atoms sit on top of O atoms
Recordinglayer
Device structure (full stack)
16Si/SiO2 sub.
CoFeB(1.6)
MgOTa/Ru
MgO
CoFeB(1.0)Ta(0.4)
[Co(0.4)/Pt(0.4)]x6
CoFeB(1.0)Ta(0.3)
[Co(0.4)/Pt(0.4)]x2Ru(0.4)Co(0.4)
Co(0.4)
Double (SyF)
Referencelayer
H. Sato et al., Appl. Phys. Lett. 101, 022414 (2012), IEDM 2013, p. 3.2.1., Appl. Phys. Lett. 105, 062403 (2014).
=E/kBT, IC0 and efficiency
17
Perpendicular MTJ
0
12
2( )
( )
S K eff
C effB
E M H V K V
eI K Vg
Eg
0 30 60 900
1
2
3
0.008
0.012 = 0.016
/I C
0 (A
-1)
Junction diameter (nm)
H. Sato et al., Appl. Phys. Lett. 101, 022414 (2012).H. Sato et al., IEDM 2013, p. 3.2.1.H. Sato et al. Appl. Phys. Lett. 105, 062403 (2014).
0 20 40 600
20406080
100
Series A Series B
Junction diameter (nm)
11 nmMTJ (smallest MTJ)
-150 -100 -50 0 50 100 150100
200
300
-8 -6 -4 -2 0 2 4 6 80.0
0.5
1.0
R (k
)
0H (mT)
11 nmTMR = 107 %
P
I (A)
11 nm = 28 IC0 = 13 A
H. Sato et al. Appl. Phys. Lett. 105, 062403 (2014).
10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2
-150
-100
-50
0
50
100
150
200
AP to P
I C (
A)
(s)
P to AP
Switching current versus switching time
MTJ stack on 300mm wafers
300 mm waferTa = 360-400oC for 1hr
Si/SiO2 sub.
CoFeB (1.4)
Ta/Ru
MgO(1.2, 1.3) CoFeB (1.2)
Ta(0.4)
Co/Pt based SyFReference layer
Ta/Ru/Ta/Pt
Ta(0.4)CoFeB (1.0)MgO(1.0)
0
10
20
30
40
250 300 350 400 450
RA
(m
2 )
Ta (oC)
0
50
100
150
200
250 300 350 400 450
TMR
ratio
(%)
Ta (oC)
300 mm wafer@CIES
300 mm wafer@CIES
3in wafer3in wafer
0.0
1000.0
2000.0
3000.0
4000.0
5000.0
6000.0
7000.0
R (a
.u)
H (a.u)
40 nm
S. Ikeda, et al. IEDM2014
Required Properties
High tunnel magnetoresistance ratio > 100%
High thermal stability = E/kBT > 60
Unlimited endurance
Low switching current
High speed read and write
High temperature tolerance ~ 400 oC
Scalability 40 nm → 20 nm → 10 nm
Required Properties
High tunnel magnetoresistance ratio > 100%
High thermal stability = E/kBT > 60
Unlimited endurance
Low switching current
High speed read and write
High temperature tolerance ~ 400 oC
Scalability 40 nm → 20 nm
Two and three terminal devices
two terminal(spin-transfer torque)
(electric-field)
three terminal(domain wall)
(spin-orbit torque)
Nonvolatile, fast, low voltage and high endurance
Domain Wall
Advantage of 3‐terminal device
V
Readmargin
Writemargin
TDDBWriteRead
EM
Writemargin
V
V
Readmargin
TDDBRead
Write
• TDDB : Time‐dependent dielectric breakdown• EM : Electromigration
The third switching scheme
Type X may serve as– tool to explore the physics of SOT switching– option for device applications
25
M // z ‘Type Z’ M // y ‘Type Y’ M // x ‘Type X’
Similar mechanismto Type Z
Same materialto Type Y
S. Fukami, HO et al., Nature Nanotech. doi: 10.1038/2016.29 (2016).
26
Antiferromagnet (AFM) for SOT switching
W. H. Meiklejohn et al., Phys. Rev. 102, 1413 (1956).
W. Zhang et al., PRL 113, 196602 (2014).
Exchange‐bias Inverse spin Hall effect
FM
AFM
S. Fukami, HO et al., Nature Mater. doi: 10.1038/nmat4566 (2016).
Film stack & m‐H loop
Perp easy axis is obtained for all the tPtMn. Bias field increases with tPtMn (≥ 7 nm).
27
-60 -40 -20 0 20 40 60
-1.0
-0.5
0.0
0.5
1.0
m (T
nm)
0H (mT)-60 -40 -20 0 20 40 60
0H (mT)
0 2 4 6 8 100
5
10
15
20
0|Hbi
as| (
mT)
tPtMn (nm)
Z
YX
tPtMn = 6 nm tPtMn = 8 nm
dc/rf magnetron sputtering Post annealing
(300C, 2h, 1.2 T)
Hbias
tPtMn = 2, 4, 5, 6, 7, 7.5, 8, 8.5 nm
S. Fukami, HO et al., Nature Mater. doi: 10.1038/nmat4566 (2016).
Switching by current under various HX
Field‐free switching is observed for exchange‐biased device. Switching current density is ~1010 A/m2
… comparable to previous non‐magnet/ferromagnet structures28
-40 -30 -20 -10 0 10 20 30 40 -40 -30 -20 -10 0 10 20 30 40
0HX (mT)
Resistance
Current (mA) Current (mA)
No bias (tPtMn = 6 nm) With bias (tPtMn = 8 nm)
S. Fukami, HO et al., Nature Mater. doi: 10.1038/nmat4566 (2016).
-40 -30 -20 -10 0 10 20 30 40
ICH (mA)
RH
0.02
-40 -30 -20 -10 0 10 20 30 40
ICH (mA)
RH
0.02 START END
tPtMn = 8 nm
H=0 Switching in Co/Ni‐PtMn
• Spin Hall effect from an antiferromagnet• Switching without magnetic filed
S. Fukami, HO et al., Nature Mater. doi: 10.1038/nmat4566 (2016).
Non‐volatile CMOS VLSIs with spintronics
First Auto Design Tool for
Spintronics CMOS (2011)
Nonvolatile FPGAwith TSV
(First 3D Spintronics CMOS Processor)
(VLSI 2012)
600MHzMTJ/CMOS Latch
(Fastest nonvolatile latch)(IEDM 2011)
Nonvolatile TCAM(Most compact TCAM
cell, 4T-2MTJ) (VLSI 2011)
1.5nsec / 1Mbit Embedded MRAM(Fastest nonvolatile
1Mbit memory)(VLSI 2013)
Nonvolatile GPU(Largest Scale
Spintronics Random Logic 500kgate/chip)
(ISSCC 2013)
1Mb Array Three Terminal DW Cell(High endurance)
(VLSI 2012)
Nonvolatile microcomputer(First nonvolatile microcomputer)(ISSCC 2014)
0.98mm
1.44mm3.39mm
2.05mm3.1m
m
3.5mm
1
Power Con
sumption
-99%
CMOS‐based Spintronics0.01
1-97%
0.03
※in case of used for full text search system ※ in case of implementation to a typical application
x 11.7x ≦
129
11.5
164x 1
2x ≦1321 1
64x 1x ≦
11001 1
64(area)(power)(delay)
1-97%
0.03
※in case of typical cash operation
Non‐volatile VLSIs for search engine for big data
Non‐volatile field programmable gate array (FPGA)
Non‐volatile cash memoryembedded in high speed CPU
NV‐TCAM NV‐FPGA STT‐MRAM NV‐MPU
4.79mm
4.79mm
1-98%
0.02
x 1x ≦1801 1
64
Non‐volatile microcontroller forbattery‐driven sensor device
※in case of use in a wireless sensor device
Power Con
sumption
Power Con
sumption
Power Con
sumption
Delay×Power×Area Ratios
CMOS‐based Spintronics
(area)(power)(delay)
CMOS‐based Spintronics
(area)(power)(delay)
CMOS‐based Spintronics
(area)(power)(delay)
2013 Symposium. on VLSI Circuits 2013 IEICE Electronics Express 2014 IEEE ISSCC2012 Symposium. on VLSI Circuits
31
On 300 mm wafers
Paradigm Shift of VLSI by Spintronics
High Speed High power
Storage capacity Low power