Spring 2006

Lillevik 437s06-l16 1University of Portland School of Engineering

EE 437

Advanced ComputerArchitecture

Lecture 16

Cache design exampleData/tag

Controller

Spring 2006

Lillevik 437s06-l16 2University of Portland School of Engineering

EE 437

Cache design example

• CPU: B2Logic model

• Memory– 256 x 8, RAM (no ROM)– 4X slower then cache, Rdy signal

• Cache: direct mapped, write-through– Data: 16 x 8, RAM (no delay)

– Tag: 16 x 4 RAM (no delay)

Spring 2006

Lillevik 437s06-l16 3University of Portland School of Engineering

EE 437

System schematic

Spring 2006

Lillevik 437s06-l16 4University of Portland School of Engineering

EE 437

General memory design

Main

Cache

Control

Driver

Driver

enable

enable

R/W#

R/W#

hit

System

Bus

Spring 2006

Lillevik 437s06-l16 5University of Portland School of Engineering

EE 437

Memory system schematic

Spring 2006

Lillevik 437s06-l16 6University of Portland School of Engineering

EE 437

RAM schematic

G1 initiates a memory

operation

Rdy indicates access time complete

Spring 2006

Lillevik 437s06-l16 7University of Portland School of Engineering

EE 437

Cache block diagramTrw#

Crw#

Data

Address

Hit

A

DinDout

A

4

8

4

8

4

Dout

Din

4

R/W#

16 x 4 tag

16 x 8 cache

low

high

low

R/W#

Match4 high

Spring 2006

Lillevik 437s06-l16 8University of Portland School of Engineering

EE 437

Cache schematic

tag

data

Spring 2006

Lillevik 437s06-l16 9University of Portland School of Engineering

EE 437

Controller description

• Read hit: read cache data and drive it onto bus

• Write hit: write data/tag into cache and data into memory

• Read miss: read data from memory, drive it onto bus, write data/tag into cache

• Write miss: same as write hit (we will use this fact later in the design)

Spring 2006

Lillevik 437s06-l16 10University of Portland School of Engineering

EE 437

State diagram

000

c

bd ReadyReady

Write

ReadHitReadMiss Ready

ReadyReset

Missing outputs

Spring 2006

Lillevik 437s06-l16 11University of Portland School of Engineering

EE 437

Find states?

• a = 000, idle

• b = 001, write

• c = 010, read hit

• d = 100, read miss

Spring 2006

Lillevik 437s06-l16 12University of Portland School of Engineering

EE 437

Find next state table?Read Write Hit Rdy PS NS

0 0 0 0 a a

1 a b

1 1 a c

1 0 a d

1 b a

0 b b

c a

1 d a

0 d d

Wr

RdHit

RdMiss

Spring 2006

Lillevik 437s06-l16 13University of Portland School of Engineering

EE 437

Find output table?

State Ack Cben Crw# Mben Mrw# Mg1

0 Idle 0 0 1 0 1 0

b Write Rdy 0 0 0 0 1

c RdHit 1 1 1 0 1 0

d RdMiss Rdy 0 0 1 1 1

Spring 2006

Lillevik 437s06-l16 14University of Portland School of Engineering

EE 437

Complete state diagram?

000

ReadyReady

Write

ReadHitReadMiss Ready

ReadyReset

Spring 2006

Lillevik 437s06-l16 15University of Portland School of Engineering

EE 437

Controller schematic

Spring 2006

Lillevik 437s06-l16 16University of Portland School of Engineering

EE 437

Program

• Write to memory– Address: 0x00, 0x10, 0x20, 0x30– Data: 0x11, 0x22, 0x33, 0x44

• Read misses, hits

Spring 2006

Lillevik 437s06-l16 17University of Portland School of Engineering

EE 437

Find controller states?Instruction Access State

60011 Write-hit 1

61022 Write-miss 1

62033 Write miss 1

63044 Write miss 1

53000 Read hit 2

52000 Read miss 4

52000 Read hit 2

51000 Read miss 4

51000 Read hit 2

50000 Read miss 4

50000 Read hit 2

Spring 2006

Lillevik 437s06-l16 18University of Portland School of Engineering

EE 437

Sample trace

Spring 2006

Lillevik 437s06-l16 19University of Portland School of Engineering

EE 437

Sample trace, continued.

Spring 2006

Lillevik 437s06-l16 20University of Portland School of Engineering

EE 437

Spring 2006

Lillevik 437s06-l16 21University of Portland School of Engineering

EE 437

Find states?

• b = 001, write

• c = 010, read hit

• d = 100, read miss

Spring 2006

Lillevik 437s06-l16 22University of Portland School of Engineering

EE 437

Find next state table?Read Write Hit Rdy PS NS

0 0 0 0 a a

1 a b

1 1 a c

1 0 a d

1 b a

0 b b

c a

1 d a

0 d d

Wr

RdHit

RdMiss

Spring 2006

Lillevik 437s06-l16 23University of Portland School of Engineering

EE 437

Find output table?

State Ack Cben Crw# Mben Mrw# Mg1

0 Idle 0 0 1 0 1 0

b Write Rdy 0 0 0 0 1

c RdHit 1 1 1 0 1 1

d RdMiss Rdy 0 0 1 1 1

Spring 2006

Lillevik 437s06-l16 24University of Portland School of Engineering

EE 437

Complete state diagram?

000

010

001100 ReadyReady

Write

ReadHitReadMiss Ready

Ready

Ack

Mrw#

Crw#

Cben

MbenAck=ReadyAck=Ready

Reset

Crw#

Spring 2006

Lillevik 437s06-l16 25University of Portland School of Engineering

EE 437

Find controller states?Instruction Access State

60011 Write 1

61022 Write 1

62033 Write 1

63044 Write 1

53000 Read Hit 2

52000 Read Miss 4

52000 Read Hit 2

51000 Read Miss 4

51000 Read Hit 2

50000 Read Miss 4

50000 Read Hit 2