Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 3 Summary of Last Lecture l How would you write a 1 to bit 9 in word 107 of a memory? l What command would you use to load a memory for simulation? Where would you put this command?
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Spring 2009 W. Rhett Davis NC State University ECE 406 Slide 1 ECE 406 – Design of Complex ECE 406 – Design of Complex Digital Systems Digital Systems Lecture 12: Intro to Lecture 12: Intro to the LC-3 Micro-architecture the LC-3 Micro-architecture Spring 2009 Spring 2009 W. Rhett Davis W. Rhett Davis NC State University NC State University with significant material from Paul Franzon, Bill with significant material from Paul Franzon, Bill Allen, & Xun Liu Allen, & Xun Liu
Transcript
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 1
ECE 406 – Design of Complex ECE 406 – Design of Complex Digital SystemsDigital Systems
Lecture 12: Intro to Lecture 12: Intro to the LC-3 Micro-architecturethe LC-3 Micro-architecture
Spring 2009Spring 2009W. Rhett DavisW. Rhett Davis
NC State UniversityNC State Universitywith significant material from Paul Franzon, Bill Allen, & Xun with significant material from Paul Franzon, Bill Allen, & Xun
LiuLiu
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 2
Announcements
HW#5 Due Thursday» Lab Attendance Required for Q6
Project #1 Posted» Due in less than 4 weeks» Print out assignment and bring to class
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 3
Summary of Last Lecture How would you write a 1 to bit 9 in word 107 of a
memory?
What command would you use to load a memory for simulation? Where would you put this command?
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 4
Today’s Lecture
Block-Diagram of the LC3
LC3 Controller State Machine
Control Signals» Controller» Fetch» Execute
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 5
Preliminaries What is a micro-architecture?
What’s the point of going to all the trouble to build a micro-controller? Why do we care?
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 6
Microarchitecture The von Neumann Model » Memory» Processor» Input» Output» Control
memory
processor
control
input output
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 7
ALU Register File Program Counter Status Register Instruction Register Logic to direct
operands to/from ALU
Logic to interface to Memory
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 8
Conventions Control signals are omitted for simplicity» Makes the diagram easier to read» Usually far fewer control signals than data signals
Wire bundles» A set of nets going from one block to another
is represented as» When a set of nets contains signals that go
in both directions (both input and output for a block), we use
» A set of nets on a shared bus (a bus with multiple drivers) is represented as
» If a block only reads or writes one signal on a shared bus, we use
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 9
Simplified LC3 Microarchitecture
Memory
Controller
Fetch
MemAccessWriteback
Decode
Execute
ALU
RegFile
IR
PSR
PC
State
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 10
Detail of Memory Bus
clock
din[15:0]
state[4:0]addr[15:0]
M_Control
MemAccess
clock
reset
state[3:0]
pc[15:0]
npc[15:0]
rd
taddr[15:0]
br_taken
Fetch
clock
addr[15:0]
dout[15:0]
complete
din[15:0]
rd
Memory
global reset
global clock
global clock
M_Data[15:0]
M_Addr[15:0]
memout[15:0]
dout[15:0]
rd
complete
from Controller
from Execute
from Execute
global clock
from Controller
from Decode
to Writeback & Execute
shar
ed a
ddre
ss b
us
shar
ed re
ad li
ne
to Decode
to Controller
from Decode
from Execute
to Writeback
Memory Bus Lines
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 11
Memory
Controller
Fetch
MemAccessWriteback
Decode
Execute
ALU
RegFile
IR
PSR
PC
State
Controller
Maintains the master state-machine for the system Distributes this state to the rest of the system (not
shown)
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 12
Memory
Controller
Fetch
MemAccessWriteback
Decode
Execute
ALU
RegFile
IR
PSR
PC
State
Fetch
Maintains the program counter (PC) for the system Communicates with Memory to make sure instruction is
made available to Decode block Master of the shared Memory bus during the all states
but the “Read Memory”, “Write Memory”, and “Indirect Address Read” states.
Receives the next address from the Execute block (if a branch is taken)
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 13
Memory
Controller
Fetch
MemAccessWriteback
Decode
Execute
ALU
RegFile
IR
PSR
PC
State
Decode
Maintains the Register File (R0…R7) for the system Maintains Instruction Register (IR)
and Processor Status Register (PSR) Receives instruction word from Main Memory Provides operands to Execute and MemAccess blocks Receives the value to write-back to the RegFile from the Writeback block Decodes every instruction and provides control signals to most blocks
(not shown)
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 14
Memory
Controller
Fetch
MemAccessWriteback
Decode
Execute
ALU
RegFile
IR
PSR
PC
State
Execute
Directs operands from the Decode block to the Arithmetic Logic Unit (ALU)
Sends result to the Writeback block (for storage in Register File), or Fetch block (with the next address on a branch)
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 15
MemAccess
Receives Address to be read/written from Execute block Receives Data to be written from Decode block Master of the shared Memory bus during the
“Read Memory”, “Write Memory”, and “Indirect Address Read” states.
Provides Data read from Memory to Writeback block
Memory
Controller
Fetch
MemAccessWriteback
Decode
Execute
ALU
RegFile
IR
PSR
PC
State
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 16
Writeback
Decides which value will be written back to the Register file Receives output of ALU from Execute Block Receives contents of Memory from MemAccess Block Sends result to Decode Block for storage in Register File
Memory
Controller
Fetch
MemAccessWriteback
Decode
Execute
ALU
RegFile
IR
PSR
PC
State
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 17
Today’s Lecture
Block-Diagram of the LC3
LC3 Controller State Machine
Control Signals» Controller» Fetch» Execute
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 18
Simplified State Machine
Update PC
Compute Memory Address
Fetch Instruction Decode
Write Memory
ExecuteALU
OperationsCompute Target PC
Update Register
File
Indirect Address
ReadRead Memory
complete==0
complete==0
complete==0
Instruction Type==0
Instruction Type==1
Instruction Type==2
Invalid State
Store PC==0
Store PC==1
Memory Access Mode==3
Memory Access Mode==2
complete==0
Memory Access Mode==0Memory Access
Mode==1
Load==1
Load==0
complete==1
complete==1
complete==1
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 19
Update PC
Compute Memory Address
Fetch Instruction Decode
Write Memory
ExecuteALU
OperationsCompute Target PC
Update Register
File
Indirect Address
ReadRead Memory
complete==0
complete==0
complete==0
Instruction Type==0
Instruction Type==1
Instruction Type==2
Invalid State
Store PC==0
Store PC==1
Memory Access Mode==3
Memory Access Mode==2
complete==0
Memory Access Mode==0Memory Access
Mode==1
Load==1
Load==0
complete==1
complete==1
complete==1
Execution of ADD/AND/NOT1. Fetch Unit loads
instruction from memory
2. Decode Unit determines the operands
3. Execute Unit applies operands to ALU
4. Result stored in Register File
5. PC incremented
1 2
3
4
5
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 20
Update PC
Compute Memory Address
Fetch Instruction Decode
Write Memory
ExecuteALU
OperationsCompute Target PC
Update Register
File
Indirect Address
ReadRead Memory
complete==0
complete==0
complete==0
Instruction Type==0
Instruction Type==1
Instruction Type==2
Invalid State
Store PC==0
Store PC==1
Memory Access Mode==3
Memory Access Mode==2
complete==0
Memory Access Mode==0Memory Access
Mode==1
Load==1
Load==0
complete==1
complete==1
complete==1
Execution of BRx/JMP/RET
1. Fetch2. Decode3. Execute
computes new PC
4. PC updated
1 2
34
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 21
Update PC
Compute Memory Address
Fetch Instruction Decode
Write Memory
ExecuteALU
OperationsCompute Target PC
Update Register
File
Indirect Address
ReadRead Memory
complete==0
complete==0
complete==0
Instruction Type==0
Instruction Type==1
Instruction Type==2
Invalid State
Store PC==0
Store PC==1
Memory Access Mode==3
Memory Access Mode==2
complete==0
Memory Access Mode==0Memory Access
Mode==1
Load==1
Load==0
complete==1
complete==1
complete==1
Execution of JSR/JSRR
1. Fetch2. Decode3. Execute
computes new PC
4. PC stored in R7
5. PC updated
1 2
35
4
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 22
Update PC
Compute Memory Address
Fetch Instruction Decode
Write Memory
ExecuteALU
OperationsCompute Target PC
Update Register
File
Indirect Address
ReadRead Memory
complete==0
complete==0
complete==0
Instruction Type==0
Instruction Type==1
Instruction Type==2
Invalid State
Store PC==0
Store PC==1
Memory Access Mode==3
Memory Access Mode==2
complete==0
Memory Access Mode==0Memory Access
Mode==1
Load==1
Load==0
complete==1
complete==1
complete==1
Execution of LD/LDR1. Fetch 2. Decode3. Execute Unit
computes address
4. MemAccess Unit reads Memory
5. Write to Register File
6. PC incremented
1 2
3
4
5
6
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 23
Update PC
Compute Memory Address
Fetch Instruction Decode
Write Memory
ExecuteALU
OperationsCompute Target PC
Update Register
File
Indirect Address
ReadRead Memory
complete==0
complete==0
complete==0
Instruction Type==0
Instruction Type==1
Instruction Type==2
Invalid State
Store PC==0
Store PC==1
Memory Access Mode==3
Memory Access Mode==2
complete==0
Memory Access Mode==0Memory Access
Mode==1
Load==1
Load==0
complete==1
complete==1
complete==1
Execution of ST/STR1. Fetch 2. Decode3. Execute Unit
computes address
4. MemAccess Unit writes Memory
5. Update PC
1 2
3
4
5
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 24
Update PC
Compute Memory Address
Fetch Instruction Decode
Write Memory
ExecuteALU
OperationsCompute Target PC
Update Register
File
Indirect Address
ReadRead Memory
complete==0
complete==0
complete==0
Instruction Type==0
Instruction Type==1
Instruction Type==2
Invalid State
Store PC==0
Store PC==1
Memory Access Mode==3
Memory Access Mode==2
complete==0
Memory Access Mode==0Memory Access
Mode==1
Load==1
Load==0
complete==1
complete==1
complete==1
Execution of LDI1. Fetch 2. Decode3. Compute
address4. Read Memory
for Indirect Address
5. Read Memory6. Update Register
File7. PC incremented
1 2
3
45
6
7
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 25
Update PC
Compute Memory Address
Fetch Instruction Decode
Write Memory
ExecuteALU
OperationsCompute Target PC
Update Register
File
Indirect Address
ReadRead Memory
complete==0
complete==0
complete==0
Instruction Type==0
Instruction Type==1
Instruction Type==2
Invalid State
Store PC==0
Store PC==1
Memory Access Mode==3
Memory Access Mode==2
complete==0
Memory Access Mode==0Memory Access
Mode==1
Load==1
Load==0
complete==1
complete==1
complete==1
Execution of STI1. Fetch 2. Decode3. Compute
address4. Read Memory
for Indirect Address
5. Write to Memory 6. Update PC
1 2
3
4
5
6
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 26
Update PC
Compute Memory Address
Fetch Instruction Decode
Write Memory
ExecuteALU
OperationsCompute Target PC
Update Register
File
Indirect Address
ReadRead Memory
complete==0
complete==0
complete==0
Instruction Type==0
Instruction Type==1
Instruction Type==2
Invalid State
Store PC==0
Store PC==1
Memory Access Mode==3
Memory Access Mode==2
complete==0
Memory Access Mode==0Memory Access
Mode==1
Load==1
Load==0
complete==1
complete==1
complete==1
Execution of LEA1. Fetch 2. Decode3. Compute
address4. Update Register
File5. Update PC
1 2
3
4
5
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 27
How Good Is Our Micro-architecture?
What is the average number of cycles per instruction
Modern microprocessors get this number close to 1.0 for scalar machines and less than 1.0 for super-scalar and VLIW machines.
Take courses like ECE 463 & ECE 464 to learn how.
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 28
Today’s Lecture
Block-Diagram of the LC3
LC3 Controller State Machine
Control Signals» Controller» Fetch» Execute
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 29
Control Signal Tables It helps greatly in the debugging of the LC-3
System to have completed tables that give the values of various control signals, depending on the instruction that is being executed.
In this section, we will begin to fill out these tables.
The instruction-set specification is needed to complete these tables, and is included here for convenience.
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 30
ALU Operations
ADD
AND
NOT
15 12 11 9 8 6 5 4 3 2 0
0 0 0 1 DR SR1 0 0 0 SR2
0 1 0 1 DR SR1 0 0 0 SR2
0 0 0 1 DR SR1 1 imm5
0 1 0 1 DR SR1 1 imm5
1 0 0 1 DR SR1 111111
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 31
Control Instructions
BR JMP JSR JSRR RET RTI TRAP
0 0 0 0 NZP PCoffset9
15 12 11 9 8 6 5 4 3 2 0
1 1 0 0 000 BaseR 000000
0 1 0 0 000 BaseR 000000
0 1 0 0 1 PCoffset11
1 1 0 0 000 111 000000
1 0 0 0 000 000 000000
1 1 1 1 0000 Trapvect8
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 32
Load/Store Instructions
LD: LDR: LDI: LEA: ST: STR: STI:
0 1 1 0 DR BaseR Offset6
15 12 11 9 8 6 5 4 3 2 0
0 0 1 0 DR PCoffset9
1 0 1 0 DR PCoffset9
1 1 1 0 DR PCoffset9
0 0 1 1 SR PCoffset9
1 0 1 1 SR PCoffset9
0 1 1 1 SR BaseR Offset6
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 33
Complete the TableC_Control
Operation mode Instr. Type Store PC Mem. Access Mode loadADD 0
1
AND 0
1
NOT
BR
JMP/RET
JSR
JSRR
LD
LDR
LDI
LEA
ST
STR
STI
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 34
Fetch Inputs & Outputs Input Signals:
» clock – global system clock.» reset – when high, the PC should be synchronously set to
x3000» state – the state from the Controller block.» taddr[15:0] – the next value of the PC if a branch is taken.» br_taken – signal to indicate that a branch is taken.
Output Signals:» rd – signal to indicate to the Memory that a read is to be
performed, rather than a write. This signals should be high-impedence during the “Read Memory”, “Write Memory”, and “Indirect Address Read” states, because the MemAccess block will drive the shared bus during these cycles. In all other states, this signal should be high.
» pc – the current value of the program counter, but should be high-impedence at the same times that the rd signal is high-impedence.
» npc – should always be PC+1.
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 35
