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Spur Reduction in Wideband PLLs by Random Positioning of Chargepump Current Pulses 2010 International Symposium on Circuits and Systems, Paris Chembiyan Thambidurai Nagendra Krishnapura Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036, India 2 June 2010
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Spur Reduction in Wideband PLLs by Random

Positioning of Chargepump Current Pulses

2010 International Symposium on Circuits and Systems, Paris

Chembiyan Thambidurai

Nagendra Krishnapura

Department of Electrical EngineeringIndian Institute of Technology, Madras

Chennai, 600036, India

2 June 2010

Outline

• Reference spur in chargepump PLLs

• Randomization of chargepump current pulses

• Implementation details

• Spectrum after randomization

• Effect of non-idealities

• Simulation results

• Conclusions

Reference spurs

PFD

up

dn

CP

N

ref

div

R

Cz

Cp

20 MHz fouticp(t)fr =

fdiv

VCO

0 Tr 2Tr

icp(t)

Chargepump non-idealities

-IleakTr

Ift

-Ift

{ Trst

-Imis

Icp

Trst

{Icp

icp(t) icp(t)icp(t)

Tr

Tr

Vdd

Iup=Icp

Idn=Icp+

icp(t)

Cp

R

Cz

UP

DN

Ileak

Ift

-Ift

Imis

Reference spurs

PFD

up

dn

CP

N

ref

div

R

Cz

Cp

20 MHz fouticp(t)fr =

fdiv

VCO

fr 2fr

Icp(f)

fout fout+fr fout-fr

Sφ(f)

0

Spur vs bandwidth tradeoff

• The magnitude of the spur at a frequency offset fr (dBc)

Sφ(fr ) = 20 log

(

Icp(fr ) |Zlp(fr )|Kvco

2fr

)

• Low spur level ⇒ low bandwidth (large settling time)

(Loop filter with one pole and one zero assumed here)

Random pulse position modulation

0 Tr 2Tr 3Tr 4Tr 5Tr

-2fr -fr fr 2fr0f f

0

Time Domain

Frequency Domain

Random pulse

Periodic pulses

0 Tr 2Tr 3Tr 4Tr 5Tr

positioning

• Redistribute the spur energy to all frequencies.

Implementation

CPup

dn

Randomizer

Randomizer

upr

dnr

0 Tr 2Tr 0 Tr 2Tr

up(t) upr(t)

ir(t)

0 Tr 2Tr

ir(t)

• Chargepump current pulse position has to be randomized.

• Accomplished by randomizing up/dn pulses.

Randomizer

16 : 1

sel [3:0]

up

MUX

upr

}Td=Tr/n

1 2 n-2 n-1

• Randomly choose 1 of n delayed pulses

Random number generator

• The randomizing sequence sel [3 : 0] should have a

uniform distribution.

• Generated using PRBS(Pseudo Random Bit Sequence)

generator.

• A PRBS of longer length

• produces low in-band noise.• guarantees near uniform distribution.

• Length of PRBS chosen based on tolerable in-band noise.

PLL with random pulse positioning

PFD

up

dn

upr

dnr

RandomizerCP

N

ref

div

VCO

R

Cz

Cp

sel [3:0]

fr

fdiv

fout

Randomizer

ir(t)

• Control voltage not periodic

Mathematical analysis

• The periodic impulse train

x(t) =∞

k=−∞

δ(t − kTr )

• The randomized impulse train

r(t) =∞

k=−∞

δ(t − kTr −akTr

n)

(n: Number of possible pulse positions in a period)

Spectrum before and after randomization

• Power spectrum of a periodic impulse train

Sx(f ) =1

Tr2

∞∑

k=−∞

δ(f −k

Tr)

• Power spectrum of the randomized signal

Sr (f ) = Srd (f ) +1

Tr2

∞∑

k=−∞

δ(f − kn

Tr)

• Srd(f ) is the “redistributed noise”

Srd(f ) =1

nTr

[

(n − 1) −2

n

n−1∑

k=1

(n − k) cos(2πkfTrn

)

]

Simulated spectrum after randomization

0 1 2 3 4 5 6 7 8−80

−60

−40

−20

Ma

gn

itu

de

(d

B)

0 1 2 3 4 5 6 7 8−80

−60

−40

−20

Frequency (f/fr)

Ma

gn

itu

de

(d

B)

n=2

n=16

Noise shaping in the redistributed noise

0 0.5 1 1.5 2 2.5 3 3.5−80

−70

−60

−50

−40

−30

−20

Frequency (f/fr)

Magnitude (

dB

)

n=2n=16

Shaped noise

• The ‘redistributed noise’

is not white.

• For n=2 we can see that

Srd(f ) =1

Trsin2(

πfTr2

)

• Close-in phase noise

remains unaffected.

Delay sensitivity

• Delays prone to process variations (Td 6= Tr/n).

• Delay line may span more or less than a reference period

• The current after randomization (ir (t)) on an average can

be expressed as

ir (t) =1

n[icp(t) + icp(t − Td) + ..... + icp(t − (n − 1)Td)]

|Ir (f )| =sin(nπfTd)

sin(πfTd)|Icp(f )|

Delay sensitivity

• Thus the randomization behaves as a moving average filter

with frequency nulls at

fz =k

nTd

k ∈ [1, (n − 1)]

• If Td =Tr

n; nulls occur at reference harmonics.

• If Td 6=Tr

n; nulls do not occur at reference harmonics and

spurs appear at PLL output

Sensitivity to delay variations

−40 −30 −20 −10 0 10 20 30 40 50−25

−20

−15

−10

−5

Percentage variation in delay

Sp

ur

reje

ctio

n (

dB

)

n=2n=4n=8n=16n=32

Simulated PLL parameters

fref 20 MHz

fout 1 GHz

fBW 1 MHz

PFD Tri-state PFD

Charge-pump Icp = 50 µA

Loop-filter R = 21.7 k˙,Cz = 37.25 pF,Cp = 1.99 pF

VCO fvco = 1GHz, Kvco = 200MHz/V

Divider N=50

• 3-dB bandwidth of the PLL is ≈ 1 MHz.

• Charge pump current mismatch 10 %

• Charge pump and PFD: transistor level

• Other components: ideal

Simulation results

10−1

100

101

102

−180

−170

−160

−150

−140

−130

−120

−110

−100P

ha

se

no

ise

(d

Bc/H

z)

Frequency offset from carrier (MHz)

Before randomizationAfter randomization

19.9 20 20.1−140

−130

−120

20 dB

Effect of randomization at high frequencies

100

101

102

−180

−170

−160

−150

−140

−130

−120

−110

−100

Ph

ase

no

ise

(d

Bc/H

z)

Frequency offset from carrier (MHz)

Randomization noiseOpen loop VCO phase noiseVCO and resistor noise

10 MHz

< 20 dB

fb=1 MHz

Simulated sensitivity to delay variations

−40 −20 0 20 40 60−40

−35

−30

−25

−20

−15

−10

−5

0

Percentage delay variation

Sp

ur

reje

ctio

n (

dB

)

AnalyticalSimulated

Conclusions

• Pulse position randomization eliminates reference spur.

• Resulting spectrum shaped to high frequencies.

• Close-in phase noise remains unaffected.

• > 11.5 dB spur rejection for ±20% delay variation.

• Simple implementation.

References

Cicero.S.Vaucher, “An adaptive PLL tuning system architecture combining high spectral purity and fast

settling time.” IEEE Journal of Solid State Circuits, pp. 2131-2137, vol. 35, issue 4, April. 2000.

Che-Fu Liang et al., “Spur suppression techniques for frequency synthesizers,” IEEE Transactions on

Circuits and Systems-II:Express Briefs, pp. 653-657, vol. 54, issue 8, Aug. 2007.

Che-Fu Liang et al., “A digital calibration technique for charge pumps in phase-locked systems,” IEEE

Journal of Solid State Circuits, pp. 390-398, vol. 38, issue 2, Feb. 2008.

T. C. Lee, W. L. Lee, “A spur suppression technique for phase Locked frequency synthesizers.”, International

Solid State Circuits Conference, ISSCC 2006, pp.592-593.

Cameron T. Charles, David J Allstot, “A Calibrated Phase/Frequency Detector for Reference Spur Reduction

in Charge-Pump PLLs,” IEEE Transactions on Circuits and Systems-II:Express Briefs, vol. 53, issue 9, Sep.2006.

B. P. Lathi, Modern Digital and Analog Communication Systems., Third edition, New York:Oxford University

Press., 1998.

Mathematical representation

kTr

kTr+akTr/n

}

Tr/n(k+1)Tr

• The reference period (Tr ) is divided into equal time

intervals of Tr/n.

• The k th current pulse will appear at kTr + akTr/n instead of

kTr .

• ak is a uniform random integer ∈ [0, n − 1]

Random pulse positioning illustrated for n=4

a1=3

a2=1

0 Tr 2Tr

Tr+3Tr/4 2Tr+T

r/4

0 Tr 2Tr

{

Tr/4

x(t)

t

t

ak

(a)

(b)

a0=2

Tr+2Tr/4

,r(t)


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