1
SRAM DESIGN PROJECT PHASE 2
Nirav Desai4280229
VLSI DESIGN 2: Prof. Kia BazarganDept. of ECE
College of Science and EngineeringUniversity of Minnesota, Twin Cities
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SRAM CELL READ AND WRITE MARGIN FROM BUTTERFLY CURVE • NMOS inverter = 110nM PMOS inverter = 220nM NMOS Access = 90nM• NMOSinv/NMOSaccess = 1.2 PMOSinv/NMOSaccess=2.4 • Cbitline = 0.747fF for 512 cell array ( Interconnect Parasitics from ASU PTM Website )
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SRAM CELL READ AND WRITE MARGIN FROM BUTTERFLY CURVE • NMOS inverter = 150nM PMOS inverter = 555nM NMOS Access = 180nM• NMOSinv/NMOSaccess = 1.2 PMOSinv/NMOSaccess = 3 Cbitline = 0.747fF• Curve shows SRAM cell is close to write failure. • Bitline Precharge to less than 1.1V could be explored to increase SNM.
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Simulation Setup
• M0,M1,M3,M4 form the cross coupled inverter pair• M5,M6 are access transistors• C1, C2 is the bitline capacitance• M7 is the precharge switch for bitline ( bit ) - V3 precharges the bitline to 0.8V• V6 precharges bitbar and writes a 0 to the cell
V(write)
V(ic) V(word)
V(qbar)
V(q)
V(bitbar)V(bit)
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Timing Waveforms for Characterization
V(write) – Applied to source of M7 (precharge switch)
V(word) – Wordline Voltage
V(qbar)
V(q)
V(ic) – Enables the precharge switch M7
V(bitbar)
V(bit)
• V(write) precharges Cbit to 0.8V via M7• V(word) disables access transistors M5 and M6 during precharge .• V(qbar) and V(q) are used to generate the butterfly curves.• V(ic) enables M7 during precharge It could be implemented as NOT(V(word)).• V(bitbar) precharges to 0.8V, shows
charge pumping when M7 turns off and follows V(qbar) when wordline is enabled.
• V(bit) follows V(q) after word line is enabled.• V(bit) precharged to Vdd by V6
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PASS TRANSISTOR BASED TREE DESIGN
a0
a0
a1
a1
a1
a1
a2
a2
a2
a2
a2
a2
a2
a2
1:8 Row Decoder Tree
8 M
SB B
UFF
ERS
in
Similar Tree Decoder for 16 LSB Bits
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TREE DECODER DESIGN
From row buffer
From column buffer
To Word Line Buffer
24 = 16 LSB Bits for Word Line Address from Column Buffers
23 =
8 M
SB B
its fo
r Wor
d Li
ne A
ddre
ss fr
om R
ow B
uffer
s
Directions of Increasing bit number
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PASS TRANSISTOR BASED TREE DESIGN
IN OUT
CK
CK
50880
LW
Identical Sizing for NMOS and PMOS to minimize charge injection effects
0200
400600
8001000
12001400
16001800
20008090
100110120130140150160170
Series1; 158.9
118.55
98.889.3
84.86
Delay
Transistor Width (nM)
Dela
y (p
sec)
• Delay drops by ~40ps/2 for every Doubling of transistor widths• Delay drop saturates around 1000nM to 89ps• Used W/L of 880/50 for final tree
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TREE DECODER TIMING DIAGRAMS
The following waveforms were applied to the row and column selection inputs of the tree decoder
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TREE DECODER TIMING DIAGRAMS
It takes one cycle for initializing the tree decoder after which we get clean pulses for each row output
LSB pulse is wider than MSB pulse in bottom figure to allow the tree to clear present state before nextUniversity of Minnesota
TREE DECODER TIMING DIAGRAMS
The top waveforms shows the matrix point output where the row and column select inputs are highThe output node discharges when the input goes low
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SRAM TIMING CIRCUIT
220110
inSAE/Write Enable
Wordline Enable
Precharge
Read/Write Input PulsePrecharge Disable Pulse
Word Line Enable PulseRead/Write Output Pulse
Timing Sequence:1. Disconnect Precharge2. Enable Word Line3. SAE / Write Enable4. Wait for read/write
5. Disble SAE/Write Enable6. Disable Wordline7. Reconnect Precharge and discharge all word lines
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Sense Amplifier EnableWordline
Precharge
or1
or2
or1
or2
or1 or2
Predischarge Transistor for Output Node when no
Signal at the input
OUTWrite Driver Enable (WE)
WordlinePrecharge
Read Bit
Write Bit
Same circuit as above
right
Pass Transistors are used for combining the Wordline and Precharge Signals from
Read and Write instructions
2 copies of timing circuit from previous slide for read and write
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SRAM TIMING INTEGRATION CIRCUIT
READ WRITE CIRCUIT ( Design by Bong Jin )
Sense Amplifier Write Driver
Precharge Circuit
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READ WRITE CIRCUIT TEST SETUP
Bitline Capacitance estimate from ASU PTM Website
Cbit estimate for 512 rows
NMOS Switches to allow read without disabling write circuit
Single SRAM Cell for simulations
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READ / WRITE TIMING WAVEFORMS
Precharge Pulse ( Active Low )
Data Meant to be written to cell
Write Enable Pulse
Read Enable Pulse
Output of Write Buffer
Disable output buffer ( tristate logic )
Bitline
Bitline Bar
Data Output
Data Out Bar
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SRAM Cell Layout
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4X4 SRAM Array Layout
VDD
GND
GND
WORD 1
WORD 0
B0 B0BAR B1 B1BAR
This unit can be replicated in all directions without any changes. LVS check remainingArray Size = 3.7975umX2.4725um
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References
• Digital Integrated Circuits Jan Rabaey, Anantha Chandrakasan, Borivoje Nikolic ( SRAM Cell Design, Decoders, Read Write Circuits )• CMOS VLSI Design by Weste and Harris ( Butterfly Curves )• CMOS Circuit Design, Layout and Simulation Baker, Li, Boyce (Decoder Design)• Course slides of Prof. Kia Bazargan ( Precharge Techniques, Decoders, SRAM Cell Design )
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