1. 8 SRAM TECHNOLOGYOVERVIEWAn SRAM (Static Random Access Memory) is designed to fill two needs: to provide a directinterface with the CPU at speeds not attainable by DRAMs and to replace DRAMs in systemsthat require very low power consumption. In the first role, the SRAM serves as cache memory,interfacing between DRAMs and the CPU. Figure 8-1 shows a typical PC microprocessormemory configuration. SRAM DRAM External Cache (L2)Main Memory64KB to 1MB 4MB to 512MBMicroprocessorInternal Cache (L1) 8KB to 32KBSource: Micron/ICE, "Memory 1997"20812Figure 8-1. Typical PC Microprocessor Memory ConfigurationThe second driving force for SRAM technology is low power applications. In this case, SRAMsare used in most portable equipment because the DRAM refresh current is several orders of mag-nitude more than the low-power SRAM standby current. For low-power SRAMs, access time iscomparable to a standard DRAM. Figure 8-2 shows a partial list of Hitachis SRAM products andgives an overview of some of the applications where these SRAMs are found.HOW THE DEVICE WORKSThe SRAM cell consists of a bi-stable flip-flop connected to the internal circuitry by two accesstransistors (Figure 8-3). When the cell is not addressed, the two access transistors are closed andthe data is kept to a stable state, latched within the flip-flop.INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-1

2. SRAM Technology 100 Industrial/Peripheral Buffer Memory64Kbit Low-Power SRAM256Kbit 1Mbit512K x 8Low-Power SRAM Low-Power SRAMLow-Power SRAM50Mass Storage Buffer Memory32K x 81M x 4/512K x 8Asynchronous SRAM 128K x 8/64K x 16Asynchronous SRAMAccess Time (ns)20 Asynchronous SRAM1032K x 32/32K x 36PC Cache MemoryAsynchronous SRAM256K x 18/128K x 36 5 32K x 36 LVCMOS SSRAM LVCMOS/HSTL SSRAMNon PC Cache Memory 264Kbit 256Kbit 1Mbit4MbitDevice DensitySource: Hitachi/ICE, "Memory 1997"22607Figure 8-2. Hitachis SRAM Products Word LineBB To Sense AmplifierSource: ICE, "Memory 1997"20019 Figure 8-3. SRAM Cell The flip-flop needs the power supply to keep the information. The data in an SRAM cell is volatile (i.e., the data is lost when the power is removed). However, the data does not leak away like in a DRAM, so the SRAM does not require a refresh cycle. 8-2INTEGRATED CIRCUIT ENGINEERING CORPORATION 3. SRAM TechnologyRead/WriteFigure 8-4 shows the read/write operations of an SRAM. To select a cell, the two access transis-tors must be on so the elementary cell (the flip-flop) can be connected to the internal SRAM cir-cuitry. These two access transistors of a cell are connected to the word line (also called row or Xaddress). The selected row will be set at VCC. The two flip-flop sides are thus connected to a pairof lines, B and B. The bit lines are also called columns or Y addresses.Word LineWord Line Column DecodeColumn DecodeSense Amplifier (Voltage Comparator)Write CircuitryD Out D In READ OPERATIONWRITE OPERATIONSource: ICE, "Memory 1997" 19952Figure 8-4. Read/Write OperationsDuring a read operation these two bit lines are connected to the sense amplifier that recognizes ifa logic data 1 or 0 is stored in the selected elementary cell. This sense amplifier then transfersthe logic state to the output buffer which is connected to the output pad. There are as many senseamplifiers as there are output pads.During a write operation, data comes from the input pad. It then moves to the write circuitry.Since the write circuitry drivers are stronger than the cell flip-flop transistors, the data will beforced onto the cell.When the read/write operation is completed, the word line (row) is set to 0V, the cell (flip-flop)either keeps its original data for a read cycle or stores the new data which was loaded during thewrite cycle.INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-3 4. SRAM TechnologyData RetentionTo work properly and to ensure that the data in the elementary cell will not be altered, the SRAMmust be supplied by a VCC (power supply) that will not fluctuate beyond plus or minus five orten percent of the VCC.If the elementary cell is not disturbed, a lower voltage (2 volts) is acceptable to ensure that the cellwill correctly keep the data. In that case, the SRAM is set to a retention mode where the powersupply is lowered, and the part is no longer accessible. Figure 8-5 shows an example of how theVCC power supply must be lowered to ensure good data retention.,,,,Data Retention Mode 3.0V VDR 2V 3.0VVCCtCDRtR,,,, , , ,CESource: Cypress/ICE, "Memory 1997"22460Figure 8-5. SRAM Data Retention WaveformMEMORY CELLDifferent types of SRAM cells are based on the type of load used in the elementary inverter of theflip-flop cell. There are currently three types of SRAM memory cells : The 4T cell (four NMOS transistors plus two poly load resistors) The 6T cell (six transistorsfour NMOS transistors plus two PMOS transistors) The TFT cell (four NMOS transistors plus two loads called TFTs)4 Transistor (4T ) CellThe most common SRAM cell consists of four NMOS transistors plus two poly-load resistors(Figure 8-6). This design is called the 4T cell SRAM. Two NMOS transistors are pass-transistors.These transistors have their gates tied to the word line and connect the cell to the columns. Thetwo other NMOS transistors are the pull-downs of the flip-flop inverters. The loads of the invert-ers consist of a very high polysilicon resistor.This design is the most popular because of its size compared to a 6T cell. The cell needs room onlyfor the four NMOS transistors. The poly loads are stacked above these transistors. Although the4T SRAM cell may be smaller than the 6T cell, it is still about four times as large as the cell of acomparable generation DRAM cell.8-4 INTEGRATED CIRCUIT ENGINEERING CORPORATION 5. SRAM Technology W+V B B To Sense Amps Source: ICE, "Memory 1997"18470AFigure 8-6. SRAM 4T (Four-Transistor) CellThe complexity of the 4T cell is to make a resistor load high enough (in the range of giga-ohms) tominimize the current. However, this resistor must not be too high to guarantee good functionality.Despite its size advantage, the 4T cells have several limitations. These include the fact that each cellhas current flowing in one resistor (i.e., the SRAM has a high standby current), the cell is sensitiveto noise and soft error because the resistance is so high, and the cell is not as fast as the 6T cell.6 Transistor (6T) CellA different cell design that eliminates the above limitations is the use of a CMOS flip-flop. In thiscase, the load is replaced by a PMOS transistor. This SRAM cell is composed of six transistors, oneNMOS transistor and one PMOS transistor for each inverter, plus two NMOS transistors con-nected to the row line. This configuration is called a 6T Cell. Figure 8-7 shows this structure. Thiscell offers better electrical performances (speed, noise immunity, standby current) than a 4T struc-ture. The main disadvantage of this cell is its large size.Until recently, the 6T cell architecture was reserved for niche markets such as military or space thatneeded high immunity components. However, with commercial applications needing fasterSRAMs, the 6T cell may be implemented into more widespread applications in the future.Much process development has been done to reduce the size of the 6T cell. At the 1997 ISSCC con-ference, all papers presented on fast SRAMs described the 6T cell architecture (Figure 8-8).INTEGRATED CIRCUIT ENGINEERING CORPORATION8-5 6. SRAM Technology W +VB BTo Sense Amps Source: ICE , "Memory 1997"18471AFigure 8-7. SRAM 6T (Six Transistor) CellCell SizeDie Size DensityCompany Cell Type Process (m2)(mm2) 4Mbit NEC6T 12.770.25m 132 4Mbit IBM6T 18.770.3m1450.2m Leff 128Kbit Hitachi6T 21.670.35m5.34 Source: ICE, "Memory 1997"22459 Figure 8-8. 1997 ISSCC Fast SRAM ExamplesTFT (Thin Film Transistor) CellManufacturers have tried to reduce the current flowing in the resistor load of a 4T cell. As a result,designers developed a structure to change, during operating, the electrical characteristics of theresistor load by controlling the channel of a transistor.This resistor is configured as a PMOS transistor and is called a thin film transistor (TFT). It isformed by depositing several layers of polysilicon above the silicon surface. The source/chan-nel/drain is formed in the polysilicon load. The gate of this TFT is polysilicon and is tied to thegate of the opposite inverter as in the 6T cell architecture. The oxide between this control gate andthe TFT polysilicon channel must be thin enough to ensure the effectiveness of the transistor.The performance of the TFT PMOS transistor is not as good as a standard PMOS silicon transis-tor used in a 6T cell. It should be more realistically compared to the linear polysilicon resistorcharacteristics.8-6INTEGRATED CIRCUIT ENGINEERING CORPORATION 7. SRAM TechnologyFigure 8-9 shows the TFT characteristics. In actual use, the effective resistance would range fromabout 11 x 1013 to 5 x 109. Figure 8-10 shows the TFT cell schematic. 106 Vd = 4V 108 Drain Current, Id (A)Vg 1010Tox = 25nmTpoly = 38nm 1012L/W = 1.6/0.6m2 02 4 68Gate Voltage, Vg (V) Source: Hitachi/ICE, Memory 1997" 19953Figure 8-9. TFT (Thin Film Transistor) Characteristics Word LinePoly-SiPMOSBLBLSource: ICE, "Memory 1997" 19954Figure 8-10. SRAM TFT CellFigure 8-11 displays a cross-sectional drawing of the TFT cell. TFT technology requires the depo-sition of two more films and at least three more photolithography steps.INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-7 8. SRAM Technology 1st Metal (BIT Line) ,,,,,, ,,,,,, ,,,,,,3rd Poly-Si 4th Poly-Si,,,,,,,,,,,2nd Poly-Si,,,,,, (Gate Electrode,,,,,,,,,,,,,,,,,,,,,,(Channel of TFT),,,,,,,,,,,,,,,,,,,,,,,,,(Internal Connection)Contact,,,,,,,,,,,,,, of TFT),,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,(W-Plug),,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,,2nd Direct Contact ,,,,,,,,,, ,,,,,,, ,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,, ,,,,,,, ,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,, ,,,,,,,,,,IsolationN+ N+ N+ N+ Access N+ Diffusion TiSi2 Driver Transistor Region1st Poly-Si Transistor (GND Line) (Gate Electrode of Bulk Transistor)Source: IEDM 91/ICE, "Memory 1997" 18749Figure 8-11. Cross Section of a TFT SRAM CellDevelopment of TFT technology continues to be performed. At the 1996 IEDM conference, twopapers were presented on the subject. There are not as many TFT SRAMs as might be expected,due to a more complex technology compared to the 4T cell technology and, perhaps, due to poorTFT electrical characteristics compared to a PMOS transistor.Cell Size and Die SizeFigure 8-12 shows characteristics of SRAM parts analyzed in ICEs laboratory in 1996 and 1997.The majority of the listed suppliers use the conventional 4T cell architecture. Only two chips weremade with a TFT cell architecture, and the only 6T cell architecture SRAM analyzed was thePentium Pro L2 Cache SRAM from Intel.As indicated by the date code of the part and its technology, this study is a presentation of whatis the state-of-the-art today. ICE expects to see more 6T cell architectures in the future.Figure 8-13 shows the trends of SRAM cell size. Like most other memory products, there isa tradeoff between the performance of the cell and its process complexity. Most manufactur-ers believe that the manufacturing process for the TFT-cell SRAM is too difficult, regardlessof its performance advantages.8-8INTEGRATED CIRCUIT ENGINEERING CORPORATION 9. SRAM TechnologyCell Size Die Size Min Gate (N)Date Code Cell Type (m2) (mm2) (m) Toshiba9509 4T22 1440.654MbitSamsung 1995 4T14.2533 0.51Mbit Galvantech 9524 4T 16.531 0.4 1MbitHitachi 9539 4T19 64 0.451Mbit NEC9436 4T19 67 0.6 1MbitMotorola9443 4T40 1080.6 1Mbit Hualon 9523 4T3013.50.45 256KbitISSI9445 4T 27.550 0.5 1MbitMosel-Vitelic 9409 4T4494.70.65 1Mbit NEC9506 4T 15.7 42.50.5 1MbitSamsung 9606TFT 11.7 77.80.654Mbit Sony?TFT20 59 0.5 1Mbit TM Tech9530 4T20 35 0.351Mbit UMC9631 4T11.2541 0.3 2MbitWinbond 9612 4T10.15 32.50.5 1Mbit Intel 6T33 0.35Pentium Pro L2 Cache Source: ICE, "Memory 1997" 22461Figure 8-12. Physical Geometries of SRAMsFigures 8-14 and 8-15 show size and layout comparisons of a 4T cell and a 6T cell using the same technol-ogy generation (0.3m process). These two parts were analyzed by ICEs laboratory in 1996.One of the major process improvements in the development of SRAM technology is the so calledself aligned contact (SAC). This process suppresses the spacing between the metal contacts andthe poly gates and is illustrated in Figure 8-16.INTEGRATED CIRCUIT ENGINEERING CORPORATION8-9 10. SRAM Technology 1,000 100 Cell Size (m2) 6T Cell104T (and TFT) Cell 11 Micron0.8 Micron 0.5-0.6 Micron0.35 Micron0.25 Micron Technology Source: ICE, "Memory 1997"19989AFigure 8-13. Trend of SRAM Cell SizesCONFIGURATIONAs shown in Figure 8-17, SRAMs can be classified in four main categories. The segments are asyn-chronous SRAMs, synchronous SRAMs, special SRAMs, and non-volatile SRAMs. These arehighlighted below.Asynchronous SRAMsFigure 8-18 shows a typical functional block diagram and a typical pin configuration of an asyn-chronous SRAM. The memory is managed by three control signals. One signal is the chip select(CS) or chip enable (CE) that selects or de-selects the chip. When the chip is de-selected, the partis in stand-by mode (minimum current consumption) and the outputs are in a high impedancestate. Another signal is the output enable (OE) that controls the outputs (valid data or highimpedance). Thirdly, is the write enable (WE) that selects read or write cycles.Synchronous SRAMsAs computer system clocks increased, the demand for very fast SRAMs necessitated variations onthe standard asynchronous fast SRAM. The result was the synchronous SRAM (SSRAM).8-10 INTEGRATED CIRCUIT ENGINEERING CORPORATION 11. 8-11 INTEGRATED CIRCUIT ENGINEERING CORPORATIONhold the address and write data state throughout the entire cycle.SSRAM. Since the operations take place on the rising edge of the clock signal, it is unecessary toconfiguration. The RAM array, which forms the heart of an asynchronous SRAM, is also found intypically have a 32 bit output configuration while standard SRAMs have typically a 8 bit outputFigure 8-20 shows a typical SSRAM block diagram as well as a typical pin configuration. SSRAMsFigure 8-19 shows the trends of PC cache SRAM.chronous SRAMs is cache SRAM used in Pentium- or PowerPC-based PCs and workstations.and therefore can be used in very high-speed applications. An important application for syn-Synchronous SRAMs have their read or write cycles synchronized with the microprocessor clock Figure 8-15. 4T SRAM Cell 22171 Source: ICE, Memory 19974.5m @@@ @@@@@@@@ @@@@@@@@? @@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@? @@@@@@@@ @@?@@@@@? @@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@? g@@ @@? @@? g@@ g@@ @@? @@? g@@ g@@ @@? g@@ @@ @@ @@ @@ GND @@ @@ @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@@@ @@@@@@ @@ @@@@@@ @@ @@ @@ @@@@@@R2 @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@@@@@2 @@ @@ @@ @@@@@@ @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@3 @@ @@@@@@ @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@4 3 @@ @@@@@@ 2.5m @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@@@@@ @@ @@@@@@ @@ @@ @@ @@ @@ @@@@@@ @@ @@@@@@ @@ @@@@@@ @@ @@ @@ @@ @@ @@ @@ @@@@@@ @@ @@ @@ @@@@@@1 @@ @@2 @@ @@ @@ @@ @@ @@ BIT @@ @@ BIT @@ @@ @@ @@@@@@ @@ @@ @@ @@ @@ @@ @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@@@@@1 @@ @@ @@ @@@@@@ @@ @@ @@ @@R1 @@ @@ @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@@@@@ @@ @@ @@ @@@@@@ @@ @@?h@@ ?h@@ @@?h@@ @@ @@?h@@ @@R1 ?h@@ R2 @@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@?h@@ @@?e@@@@@@ @@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@?e@@@@@@@@4VCC WORDWORD Figure 8-14. 6T SRAM Cell 22172 Source: ICE, Memory 1997 6.35m@@@@@@@@? @@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@? @@@@@@@@@@@@@?@@@@@? @@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@? @@@@@@@@g@@@@?@@? g@@g@@@@?@@? g@@g@@@@? g@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 2@@@@ BIT@@@@N+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 5@@@@@@@@3@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@3N4N@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 2N@@@@1N@@@@@@@@@@@@ BIT BIT@@@@5.2mGND@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 6P@@@@5P@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@64@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ P+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ WORD@@@@@@@@@@@@@@@@@@@@@@@@@@@@ BIT@@@@@@@@@@@@1@@@@@@ N+@@@@@@@@@@@@@@@@@@POLYCIDE@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ SIDEWALL SPACER@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@?h@@@@@@?h@@?h@@@@@@?h@@?h@@@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@?h@@@@?e@@@@@@@@@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@e?@@@@@@@@?e@@@@@@@@?e@@@@@@@@SRAM Technology 12. SRAM Technology Standard Process Transistor Active Area GateMetal ContactMetal ContactMetal Line Metal LineContact to Poly SpacingSAC Process Transistor Active Area GateMetal Contact Metal Contact Metal Line Metal Line Contact to Poly Spacing Has Been EliminatedSource: EN/ICE, "Memory 1997" 22456 Figure 8-16. Self Aligned Contact (SAC) ProcessBurst ModeThe SSRAM can be addressed in burst mode for faster speed. In burst mode, the address for thefirst data is placed on the address bus. The three following data blocks are addressed by an inter-nal built-in counter. Data is available at the microprocessor clock rate. Figure 8-21 shows SSRAMtiming. Interleaved burst configurations may be used in Pentium applications or linear burst con-figurations for PowerPC applications.8-12 INTEGRATED CIRCUIT ENGINEERING CORPORATION 13. SRAM Technology SRAMs AsynchronousSynchronousSpecial Non-Volatile Low Speed Interleaved Versus Multiport Non-Volatile RAM Medium SpeedLinear Burst FIFO(NVRAM) High Speed Flow-Through Versus Cache Tag Battery-Back SRAMPipelined (BRAM) ZBT (Zero Bus Turnaround) Late-Write DDR (Double Data Rate) Dual PortSource: ICE, "Memory 1997"22454 Figure 8-17. Overview of SRAM TypesN.C. 1 32 VDDA152 31 A16A143 30 CS2A124 29 WE I/O0A75 28 A13 Input Buffer A66 27 A8 A10 I/O1 A57 26 A9A9 Row DecoderA8 I/O2A48 25 A11 Sense AmpsA7 A39 24 OEA6 I/O3 512 x 512 A21023 A10A5A4 Array I/O4A11122 CS1A3 A01221 I/O8A2 I/O5 I/O1 1320 I/O7 CEI/O6 I/O2 1419 I/O6Power WEColumn I/O3 1518 I/O5Down Decoder I/O7 VSS1617 I/O4OE A14 A13 A12 A11 A1A0 Logic Block Diagram Pin Configuration Source: Cypress/ICE, "Memory 1997"22458Figure 8-18. Typical SRAMFlow-Through SRAMFlow-through operation is accomplished by gating the output registers with the output clock. Thisdual clock operation provides control of the data out window.INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-13 14. SRAM Technology 64-bit CPU 32-bit CPU 16-bit CPUWith Cache StandardSRAMSync. Burst SRAM Non Cache 19871990199319961999Year Source: Mitsubishi/ICE, "Memory 1997" 20429AFigure 8-19. Trend of PC Cache SRAM/ADSC/ADSP Address 1513 15 /BWE/BW4 /BW3/BW2 /BW1/ADV /CE1/CE3 VDD CLK VSS/GWCE2/OE15 Registers A6A7 A8A9A0-A14 A0 A1 10099 989796 9594 9392 91 90 8988 8786858483 8281ADVD0 D1 A0+CLKBinary Q0N.C.180N.C. Counter279 A1+ I/O 17I/O 16 ADSCLoadQ1I/O 18 378I/O 15 ADSPVDDQ 477VDDQ8VSSQ 576VSSQ Byte 4Byte 4 8I/O 19 675I/O 14 Write Write I/O 20 774I/O 13Register Driver I/O 21 873I/O 12BW4 I/O 22 972I/O 118 VSSQ 10 71VSSQ Byte 3Byte 3 8 Write Write VDDQ 11 70VDDQRegister Driver32K x 32I/O 23 12 69I/O 10 MemoryI/O 24 13 68I/O 9BW3Array8 N.C.14 67VSS Byte 2Byte 2 8 VDD 15 66N.C. Write WriteN.C.16 65VDDRegister Driver VSS 17 64ZZBW2I/O 25 18 63I/O 88I/O 26 19 62I/O 7 Byte 1Byte 1 8VDDQ 20 61VDDQ Write Write VSSQ 21 60VSSQRegister Driver32 I/O 27 22 59I/O 6BW1 I/O 28 23 58I/O 5ChipSenseI/O 29 24 57I/O 4 Enable Amps I/O 30 25 56I/O 3CERegister VSSQ 26 55VSSQ CE232 32VDDQ 27 54VDDQ CE2 I/O 31 28 53I/O 2 OEOutputI/O 32 29 52I/O 1 BuffersN.C.30 51N.C.Input Data 3132 333435 3637 3839 40 41 4243 4445464748 4950 Registers32 /LBOA5 A4A3A2 A1A0 N.C.N.C. VSS VDD N.C.N.C. A10A11A12A13A14 N.C.N.C. 32DQ0-DQ35Logic Block DiagramPin ConfigurationSource: Hitachi/ICE, "Memory 1997"22457Figure 8-20. Typical SSRAM 8-14 INTEGRATED CIRCUIT ENGINEERING CORPORATION 15. SRAM Technology SYNCHRONOUS MODE CLOCK Address Output BURST MODE Address,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, OutputSource: ICE, "Memory 1997"19955A Figure 8-21. SSRAM TimingPipelined SRAMsPipelined SRAMs (sometimes called register to register mode SRAMs) add a register between thememory array and the output. Pipelined SRAMs are less expensive than standard SRAMs forequivalent electrical performance. The pipelined design does not require the aggressive manu-facturing process of a standard SRAM, which contributes to its better overall yield. Figure 8-22shows the architecture differences between a flow-through and a pipelined SRAM.Figure 8-23 shows burst timing for both pipelined and standard SRAMs. With the pipelinedSRAM, a four-word burst read takes five clock cycles. With a standard synchronous SRAM, thesame four-word burst read takes four clock cycles.Figure 8-24 shows the SRAM performance comparison of these same products. Above 66MHz,pipelined SRAMs have an advantage by allowing single-cycle access for burst cycles after the firstread. However, pipelined SRAMs require a one-cycle delay when switching from reads to writesin order to prevent bus contention.Late-Write SRAMLate-write SRAM requires the input data only at the end of the cycle.INTEGRATED CIRCUIT ENGINEERING CORPORATION8-15 16. SRAM TechnologyClockControlRegister Dout PIPELINEDControl DoutFLOW-THROUGHSource: ICE, "Memory 1997" 22608Figure 8-22. Pipelined Versus Flow-Through ArchitecturesClock 1 Clock 2 Clock3Clock 4 Clock 5 ClockAddress AA+1A+2A+3 DataData A Data A+1Data A+2Data A+3A 4-word burst read from pipelined SRAMsClock 1 Clock 2 Clock3Clock 4 Clock 5 ,,,,,, , ClockAddress AA+1A+2A+3 Data Data A Data A+1Data A+2 Data A+3 A 4-word burst read from synchronous SRAMsSource: Electronic Design/ICE, "Memory 1997" 20863Figure 8-23. Pipelined Versus Non-Pipelined Timings 8-16INTEGRATED CIRCUIT ENGINEERING CORPORATION 17. SRAM Technology 3.3V 32K x 832K x 32 Pipelined32K x 32 Non-PipelinedBusPerformancePerformancePerformance Frequency Speed CycleAccess Cycle Banks(ns)Read Write TimeRead WriteTimeTimeReadWrite5020 1 3-2-2-2 4-2-2-220 3-1-1-1 2-1-1-11220 2-1-1-1 2-1-1-16015 1 3-3-3-3 4-3-3-3 16.73-1-1-1 2-1-1-110 16.72-1-1-1 2-1-1-1 2 3-2-2-2 4-2-2-26612 1 3-3-3-3 4-4-4-415 3-1-1-1 2-1-1-19 15 2-1-1-1 2-1-1-115 2 3-2-2-2 4-2-2-27515 2 3-2-2-2 4-2-2-2 13.33-1-1-1 2-1-1-1913.33-2-2-2 3-2-2-28312 2 3-2-2-2 4-2-2-212 3-1-1-1 2-1-1-19 12 3-2-2-2 3-2-2-2 10010 2 3-2-2-2 4-2-2-210 3-1-1-1 2-1-1-19 10 3-2-2-2 3-2-2-2 12582 3-2-2-2 4-2-2-283-1-1-1 2-1-1-19 83-2-2-2 3-2-2-2Source: Micron/ICE, "Memory 1997"20864 Figure 8-24. SRAM Performance ComparisonZBT (Zero Bus Turn-around)The ZBT (zero bus turn-around) is designed to eliminate dead cycles when turning the bus aroundbetween read and writes and reads. Figure 8-25 shows a bandwidth comparison between thePBSRAM (pipelined burst SRAM), the late-write SRAM and the ZBT SRAM architectures. DeviceClock Speed Bus Bandwidth SRAMConfiguration (MHz) Utilization (Mbytes/sec) PBSRAM 128K x 36 bits 100 50%200Late-Write128K x 36 bits 100 67%268SRAMZBT SRAM128K x 36 bits 100100%400 Source: ICE, "Memory 1997"22609 Figure 8-25. SSRAM Bandwidth ComparisonDDR (Double Data Rate) SRAMsDDR SRAMs boost the performance of the device by transferring data on both edges of the clock.INTEGRATED CIRCUIT ENGINEERING CORPORATION 8-17 18. SRAM TechnologyCache Tag RAMsThe implementation of cache memory requires the use of special circuits that keep track of whichdata is in both the SRAM cache memory and the main memory (DRAM). This function acts like adirectory that tells the CPU what is or is not in cache. The directory function can be designed withstandard logic components plus small (and very fast) SRAM chips for the data storage. An alter-native is the use of special memory chips called cache tag RAMs, which perform the entire func-tion. Figure 8-26 shows both the cache tag RAM and the cache buffer RAM along with the mainmemory and the CPU (processor). As processor speeds increase, the demands on cache tag andbuffer chips increase as well. Figure 8-27 shows the internal block diagram of a cache-tag SRAM. Data Bus Processor MainMemoryCache Buffer RAMAddress Bus Cache Tag RAMSource: TI/ICE, "Memory 1997" 18472 Figure 8-26. Typical Memory System With CacheFIFO SRAMsA FIFO (first in, first out) memory is a specialized memory used for temporary storage, which aidsin the timing of non-synchronized events. A good example of this is the interface between a com-puter system and a Local Area Network (LAN). Figure 8-28 shows the interface between a com-puter system and a LAN using a FIFO memory to buffer the data.Synchronous and asynchronous FIFOs are available. Figures 8-29 and 8-30 show the block dia-grams of these two configurations. Asynchronous FIFOs encounter some problems when used inhigh-speed systems. One problem is that the read and write clock signals must often be speciallyshaped to achieve high performance. Another problem is the asynchronous nature of the flags. Asynchronous FIFO is made by combining an asynchronous FIFO with registers. For an equivalentlevel of technology, synchronous FIFOs will be faster.8-18INTEGRATED CIRCUIT ENGINEERING CORPORATION 19. SRAM Technology A0VCC 65,356-BitGND AddressMemory Decoder ArrayA12 RESETI/O0-78 I/O ControlWEControl Compa-OE rator Logic CSMatch (Open Drain) Source: IDT/ICE, "Memory 1997"20865 Figure 8-27. Block Diagram of Cache-Tag SRAMMicroprocessor LAN System BusDisk DriveFIFO Memory Source: IDT/ICE, "Memory 1997" 18804Figure 8-28. FIFO Memory Solution for File ServersINTEGRATED CIRCUIT ENGINEERING CORPORATION8-19 20. SRAM TechnologyWrite Data Write ClockWriteWrite Data Address Write EnableRegister Counter Write LatchFF FullWritePulseDual Port RAM Array Flag Gen 4096 Words x 18 Bits Logic EmptyFF Read Enable Read Address Read Data Read ClockCounter RegisterRead DataSource: Paradigm/ICE, "Memory 1997"20866Figure 8-29. Synchronous FIFO Block Diagram Write Data InhibitWrite ClockWrite Counter FullDual Port RAM Array Flag4096 Words x 18 Bits Logic EmptyRead Clock Read Counter Inhibit Read DataSource: Paradigm/ICE, "Memory 1997"20867Figure 8-30. Asynchronous FIFO Block DiagramMultiport SRAMsMultiport fast SRAMs (usually two port, but sometimes four port) are specially designed chipsusing fast SRAM memory cells, but with special on-chip circuitry that allows multiple ports(paths) to access the same data at the same time.8-20 INTEGRATED CIRCUIT ENGINEERING CORPORATION 21. SRAM TechnologyFigure 8-31 shows such an application with four CPUs sharing a single memory. Each cell in thememory uses an additional six transistors to allow the four CPUs to access the data, (i.e., a 10T cellin place of a 4T cell). Figure 8-32 shows the block diagram of a 4-port SRAM.CPU #1CPU #2 4-Port SRAMCPU #3CPU #4Source: IDT/ICE, "Memory 1997"18805Figure 8-31. Shared Memory Using 4-Port SRAMShadow RAMsShadow RAMs, also called NOVROMs, NVRAMs, or NVSRAMs, integrate SRAM and EEPROMtechnologies on the same chip. In normal operation, the CPU will read and write data to theSRAM. This will take place at normal memory speeds. However, if the shadow RAM detects thata power failure is beginning, the special circuits on the chip will quickly (in a few milliseconds)copy the data from the SRAM section to the EEPROM section of the chip, thus preserving the data.When power is restored, the data is copied from the EEPROM back to the SRAM, and operationscan continue as if there was no interruption. Figure 8-33 shows the schematic of one of thesedevices. Shadow RAMs have low densities, since SRAM and EEPROM are on the same chip.Battery-Backed SRAMsSRAMs can be designed to have a sleep mode where the data is retained while the power con-sumption is very low. One such device is the battery-backed SRAM, which features a small bat-tery in the SRAM package. Battery-backed SRAMs (BRAMs), also called zero-power SRAMs,combine an SRAM and a small lithium battery. BRAMs can be very cost effective, with retentiontimes greater than five years. Notebook and laptop computers have this sleep feature, but uti-lize the regular system battery for SRAM backup.INTEGRATED CIRCUIT ENGINEERING CORPORATION8-21 22. SRAM Technology R/WP1R/WP4CEP1CEP4OEP1OEP4 I/O0P1-I/O7P1ColumnColumnI/O0P4-I/O7P4I/O I/O Port 1 Port 4AddressAddressA0P1-A11P1A0P4-A11P4Decode Decode LogicLogicMemory Array Port 2 Port 3AddressAddressA0P2-A11P2A0P3-A11P3Decode Decode LogicLogicColumnColumn I/O0P2-I/O7P2I/O0P3-I/O7P3I/O I/OOEP2OEP3CEP2CEP3 R/WP2R/WP3 Source: IDT/ICE, "Memory 1997"20868Figure 8-32. Block Diagram of a 4-Port DRAMFigure 8-34 shows a typical BRAM block diagram. A control circuit monitors the single 5V powersupply. When VCC is out of tolerance, the circuit write protects the SRAM. When VCC fallsbelow approximately 3V, the control circuit connects the battery which maintains data and clockoperation until valid power returns.RELIABILITY CONCERNSFor power consumption purposes, designers have reduced the load currents in the 4T cell struc-tures by raising the value of the load resistance. As a result, the energy required to switch the cellto the opposite state is decreased. This, in turn, has made the devices more sensitive to alpha par-ticle radiation (soft error). The TFT cell reduces this susceptibility, as the active load has a lowresistance when the TFT is on, and a much higher resistance when the TFT is off. Due toprocess complexity, the TFT design is not widely used today.8-22 INTEGRATED CIRCUIT ENGINEERING CORPORATION 23. SRAM TechnologyNonvolatile EEPROM Memory ArrayA StoreRowSRAM Rows Select Memory ArrayArrayA RecallStoreControl Recall LogicColumnI/O CircuitsI/OInputData Column Select ControlI/OA ACSWESource: Xicor/ICE, "Memory 1997" 18479Figure 8-33. Block Diagram of the Xicor NOVRAM FamilyINTEGRATED CIRCUIT ENGINEERING CORPORATION8-23 24. SRAM Technology A0-A10 Lithium DQ0-DQ7 CellPower2K x 8Voltage Sense SRAM Array andSwitchingVPFDECircuitry W GVCCVSS Source: SGS-Thomson/ICE, "Memory 1997"20831A Figure 8-34. Block Diagram of a Typical BRAM8-24INTEGRATED CIRCUIT ENGINEERING CORPORATION