SRAm Write-Ability Improvement With Transient Negative Bit-Line Voltage

24 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 1, JANUARY 2011

SRAM Write-Ability Improvement With TransientNegative Bit-Line Voltage

Saibal Mukhopadhyay, Member, IEEE, Rahul M. Rao, Member, IEEE, Jae-Joon Kim, Member, IEEE, andChing-Te Chuang, Fellow, IEEE

Abstract—Increasing variations in device parameters signifi-cantly degrades the write-ability of SRAM cells in deep sub-100nm CMOS technology. In this paper, a transient negative bit-linevoltage technique is presented to improve write-ability of SRAMcell. Capacitive coupling is used to generate a transient negativevoltage at the low-going bit-line during Write operation withoutusing any on-chip or off-chip negative voltage source. Statisticalsimulations in a 45–nm PD/SOI technology show a �� reduc-tion in the Write-failure probability with the proposed method.

Index Terms—Capacitive coupling, SRAM, variation,write-ability.

I. INTRODUCTION

S RAM cells are known to be highly sensitive to processvariations due to the extremely small device sizes. Local

random variations in device characteristics can easily lead toRead disturb (cell flipping during Read), Write failure, or Readaccess failure (increase in Read delay resulting in incorrectsensing) in SRAM cells [1], [2]. Conflicting requirementsimposed by Read/Write operations and cell disturbs make itdifficult to simultaneously mitigate the various failures.

Fig. 1 shows a conventional 6 T SRAM cell with the nodestoring ‘1’. In order to write ‘0’ to the node , the voltage

at that node needs to be pulled down to the trip-point of in-verter associated with the node (i.e., – ) while theword-line (WL) is still enabled [2]. If becomes strongerand/or becomes weaker, due to process variations, the dis-charge of the node gets more difficult. Further, if and

become weaker and becomes stronger, the trip-pointof the – reduces. Hence, node may not drop belowthe trip-point of – , resulting in a Write failure. In gen-eral, stronger access devices and/or weaker pull-updevices improve the write-ability of the cell [2], [3].But stronger access or weaker pull-up device aggravates Readdisturb failures [2]. Therefore, dynamic modifications of cell

Manuscript received October 28, 2008; revised February 17, 2009 and Feb-ruary 17, 2009. First published October 30, 2009; current version published De-cember 27, 2010.

S. Mukhopadhyay is with the School of Electrical and Computer Engineering,Georgia Institute of Technology, Atlanta, GA USA (e-mail: [email protected]).

R. M. Rao and J.-J. Kim are with IBM T. J. Watson Research Center, York-town Heights, NY 10598 USA (e-mail: [email protected]; [email protected]).

C.-T. Chuang is with the National Chiao Tung University, Hscinchu, Taiwan(e-mail: [email protected]).

Digital Object Identifier 10.1109/TVLSI.2009.2029114

terminal voltages, depending on the type of operation, are moreflexible to simultaneously reduce all failure types.

Write-ability can be improved by dynamically altering theword-line or cell supply voltage using row-based or column-based control [4]–[8]. A higher word-line voltage (stronger ac-cess transistors), or reduced cell-supply voltage (weaker pull-updevices) during Write operation improves cell write-ability [5],[6]. However, row-based dynamic control of terminal voltagesduring Write increases Read disturb failures in the half-selectedcells (in unselected columns) along the selected row. This effectcan be avoided using column-based dynamic control of the cellsupply voltage [7], [8]. In this case, the supply voltage of theselected column is reduced during Write but that of unselectedcolumn is kept at nominal voltage. However, a lower supplyvoltage also reduces the trip-point of the inverter – andgain of the cross-coupled inverter pair which negatively impactcell write-ability.

In this paper, we propose a technique for reducing Write fail-ures by using a transient negative voltage at the low-going bit-line during Write. This preserves the column based control, andenhances the strength of the access transistor with no change inthe cross-coupled inverter. We further propose a capacitive-cou-pling based Transient Negative Bit-Line (Tran-NBL) voltagescheme to eliminate the need for on-chip generation of a smallnegative voltage. Simulation results in a 45-nm PD/SOI tech-nology show a reduction in Write failure and marginal re-ductions in access and disturb failure at a small (7%–9%) areaoverhead.

The rest of the paper is organized as follows. Section IIpresents the basic concept of the negative bit-line voltagescheme. Section III presents proposed Tran-NBL scheme.Section IV presents the mathematical analysis of the pro-posed idea. Section V analyzes its impact on performance andRead disturb failure. Section VI presents its implementation.Section VII evaluates the effectiveness of Tran-NBL throughstatistical simulations. Finally, Section VIII summarizes thepaper.

II. NEGATIVE BIT-LINE FOR IMPROVED WRITE-ABILITY

A. Basic Concept

If a small negative voltage at the low-going bit-line(instead of 0 V) is applied during Write, the write-ability can beimproved [9], [10]. A negative voltage at the low-going bit-line(BL in Fig. 1) increases the strength of the access transistorsas increases from to , where isthe word-line voltage. The negative voltage does not impact thestrength of the gain of the cross-coupled inverter. Further, this

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MUKHOPADHYAY et al.: SRAM WRITE-ABILITY IMPROVEMENT WITH TRANSIENT NEGATIVE BIT-LINE VOLTAGE 25

Fig. 1. SRAM cell illustrating Write condition and waveforms for correct and incorrect Write operations. � represents the voltage at node � and � representsthe voltage at node �.

Fig. 2. Effect of cell terminal voltages on: (a) Write failures and (b) active data-retention failure. The failure probabilities are normalized to the Write failureprobability at [� � � � � �, � �� , � �� ].

is a column based control thereby avoiding half-select stabilitydegradation.

B. Statistical Simulation

The Write failure probability of a typical 45-nm PD/SOISRAM cell is estimated with transient simulations and using fastMonte Carlo simulator presented in [11]. The threshold voltagesof all the cell devices are assumed to be independent Normalrandom variables. The “normal conditions” are defined as fol-lows: cell supply ; word-line voltage ;bit-line high voltage ; low bit-line voltage ; and2 GHz of target frequency. A negative bit-line voltage is consid-erably more effective than a lower cell supply voltage as it doesnot impact the cross-coupled inverters [Fig. 2(a)]. However, it isslightly less effective that higher word-line voltage since it onlyincreases the strength of while a higher word-line voltagemakes both and stronger. Thus, the effectiveness of thenegative bit-line is similar to word-line control (row-based),but it has the benefit of column-based control.

C. Effect on Data Retention

A column-based scheme can cause the unselected cells in theselected column to flip, resulting in a data retention failure (ac-tive data-retention failure). Note that during active data-reten-tion failure, one of the bit-lines is high, while other one is low.For dynamic supply control, the active data-retention failurescan increase due to lower supply voltage of the unselected cells.Active data-retention failures can occur in the negative bit-linescheme due to increased leakage through the access transistor

in the unselected cells. For similar re-duction in the cell supply and dc negative bit-line voltages, thefailure probability increases at a greater rate for the dc nega-tive bit-line scenario [Fig. 2(b) failures are normalized to Writefailure probability at nominal condition, ignore the TransientNegative Bit-Line case]. This constrains the maximum dc neg-ative bit-line voltage that can be used.

D. Measurement Results

The effect of reduced cell supply and dc negative bit-line onwrite-ability and active data retention was further verified byhardware measurement of an array of 120 cells, manufactured ina 45-nm SOI technology. The Write margin was obtained fromthe dc characteristics of the two inverters in the SRAM cell [12].The effect on active data retention was verified by measuringthe hold static noise margin [12], considering one bit-line atVDD and the other at zero or negative voltage. The measuredmean Write margin with dc negative bit-line is higher comparedto that with reduced supply voltage [Fig. 3(a)]. The mean holdnoise margin [Fig. 3(b)] is less with dc negative bit-line voltagescompared to reduced cell supply.

III. TRANSIENT NEGATIVE BIT-LINE TECHNIQUE

Along with increased active data-retention failure, DC nega-tive bit-line also requires a small negative voltage source (on-chip or off-chip). To eliminate these issues, we propose a ca-pacitive coupling based technique (Tran-NBL) for generating atransient negative pulse on the appropriate bit-line [13].

A. Basic Concept

A Write operation is essentially composed of two parts: a)Node storing ‘1’ (i.e., in Fig. 1) is discharged until the nodevoltage equals the voltage at the node with ‘0’ (i.e., in Fig. 1)and b) after voltage at the node, becomes lower than thatat the node , the cross-coupled inverters ensures that nodereaches ‘0’, and node reaches ‘1’ (Fig. 1). The discharging


Fig. 3. DC measurement data for the impact of cell terminal voltages on (a)Write margin and (b) active hold noise margin. Normalizations are performedwith respect to the condition [� � � � � �, � �� , � �� ].

time of a) is denoted as , and the cross-coupled inverter ac-tion time in b) is . Process imperfections increase be-yond the word-line turn-on duration leading to a Writefailure. Increased word-line voltage, lower cell supply voltage,and the negative bit-line voltage aim to expedite the dischargingprocess. If the node is discharged below node within ,a strong cross-coupled inverter action will most likely ensure theWrite operations. Lower cell supply increases while the othertwo schemes weakly impact . Hence, Write assist schemesprimarily need to ensure that the node voltage drops belowthe node voltage within after the rising edge ofthe word-line to allow sufficient time for cross-coupled inverteraction. The basic idea of our scheme is to create a transient neg-ative voltage at the low-going bit-line which causes a temporarydrop in the node voltage.

B. Proposed Transient Negative Bit-Line Scheme

The proposed Tran-NBL, shown in Fig. 4, includes twoboosting capacitors, and , connectedto bit-lines and , respectively. The other end of thecapacitors, which can be implemented using MOSFET gatecapacitances, is connected to the signal. The signal

is used for column selection. and aregenerated based on pre-charge signal (synchronizedwith word-line signal), Read/Write signal, and columnselect signals.

The timing diagram for circuit operation is illustratedin Fig. 4. In conventional Write operation, both pass-gates( , and ) along the bit-lines (BL and BR)

Fig. 4. The proposed Tran-NBL scheme.

are ON (i.e., remains “High”), and BL and BR areheld at ground (0) and (1) for the entire duration of the

pulse. In the proposed scheme, the andsignals are asserted along with the pulse, and de-assertedmidway through the pulse. This turns OFF the pass transis-tors , and , leaving bit-lines andfloating at 0 and 1, respectively. Next, the high-to-low transitionof causes an under-shoot at the bit-lines anddue to capacitive coupling through the boosting capacitors. Asthe bit-line is floating at 0, this causes a temporary negativevoltage at bit-line BL. The transient negative voltage atresults in a transient increase in the discharging current ofthe access transistor , thus facilitating the pull-down of thenode voltage . The latching action of the cross-coupledinverter pairs starts as soon as falls below the trip-pointof – . Even when the voltage of the BL returns to ‘0’after the latching action is kicked off, the Write operation getscompleted correctly.

A high-to-low transition at also results in a voltageundershoot at the other bit-line ( in Fig. 4). This can beavoided by connecting a small (minimum size) cross-coupledpMOS pair – between and (Fig. 4). Whenis pulled down low, pMOS would be turned on to holdbit-line “High” even after the pass-transistors areturned OFF. A negative transient voltage at further increasesthe strength of . Consequently, the high-to-low transition at

introduces only a negligible undershoot at and thevoltage level is quickly restored to “High”, thereby improvingthe effectiveness of the Tran-NBL scheme. The cross-coupledpMOS devices are already present in certain implementationsof SRAM Read/Write circuits [14].

IV. MATHEMATICAL ANALYSIS

A. Modeling Methodology

Consider the simple equivalent circuit diagram shown inFig. 5. Assume at time the low-going bit-line isheld at ‘0’. The high-to-low transition is applied at at


Fig. 5. Mathematical analysis framework.

. Assume at , the voltage at node is . Thetransient behavior of bit-line and node are governed by

(1a)

(1b)

where, is the bit-line voltage and is the voltageat ; is the discharging current through the accesstransistor (i.e., Write-current into ); is the bit-linecapacitance; and is the arrival time of the signal;

is the total capacitance at node ; and is the cur-rent through . For simplicity, we assume that the nodevoltage is constant until node is discharged to the trip-pointof the inverter – . To obtain an intuitive understanding ofTran-NBL scheme, we simplify the analysis: i) we analyze (1a)assuming a constant to obtain ; and ii) we con-sider (1b) with the obtained to analyze the impact on theWriting process.

B. Analytical Modeling of Bit-Line Transient

Depending on , will either be in saturationor linear region. Considering

these different regions and assuming is small ( 0.1–0.2 V)enough that can be neglected, we obtain the following:

Saturation region:

(2a)

Linear region:

(2b)

For simplicity, a linear change in can be given by

(3)

From (1)–(3) and considering boundary conditions: (a)at , and (b) at we obtain for

:

(4)where, . is the maximum negativebit-line voltage at .

C. Modeling Effect of Bit-Line Transient on Writing

Assume and are in linear region; resistance ofis constant (constant ); and resistance of

depends . Hence, from (1b)and considering at Solving (10) using thecondition we obtain

where

(5)

Note a negative reduces . From (4) into (5), we cananalyze the effect of Tran-NBL scheme. We approximate thatthe voltage at which node and node cross each other is

, where is a constant ( 0.2). Further, we ap-proximate that after node crosses node cross-couple inverteraction pushes node quickly to ‘0’, and the access transistorcurrent becomes negligible for convention case (i.e., ):

forfor (6)

D. Analysis of Maximum Negative Bit-Line Voltage

The maximum negative bit-line voltage is given by

(7a)

(7b)

Equation (7b) shows the simple case when is independentof (i.e., ). The second component in (7b) is the neg-


Fig. 6. Dependence of �� on (a) falling slew and boosting capacitanceand (b) � shift of the access device.

ative voltage induced by capacitive coupling. The first compo-nent shows the positive voltage induced by the Write current at

when the pulse arrives before the Write operation is com-pleted. This reduces the negative voltage drop at the bit-line.For a given bit-line capacitance , a higher boosting ca-pacitance increases the maximum negative voltage andreduces the positive voltage change due to the non-zero Writecurrent. A smaller reduces the positive voltage induced bythe Write current and makes more negative. Equation (7)also shows a key benefit of the proposed scheme. A smaller orlower (i.e., cells with lower Write current or weak Writecells) increases as both of them reduce the positive chargecontributed by the Write-current. Hence, instead of providingequal Write assist to all cells as in cases of dc-biasing schemes,the proposed technique provides more Write-assist (i.e., highernegative bit-line voltage) to weaker cells. The above observa-tions are summarized in Fig. 6. Fig. 6(a) shows that for a con-stant , , and , increasing and reducingincreases . An increase in the threshold voltageof the access device increases the maximum negative bit-linevoltage providing higher Write assistance [Fig. 6(b)].

E. Effect of Arrival Time of Pulse

The node voltage at (i.e., ) can be obtained as

(8)

From (8) we observe that a smaller results in a higher . Ahigher implies that, the reduction in due to the negative

transient may not be sufficient to enforce crossing of nodeand . Fig. 7 plots waveforms estimated using (8) which showstwo distinct regions. First, the bit-line voltage reduces and be-comes negative due to the high-to-low transition at .Once the transition is over, the floating bit-line voltagestarts increasing due to Write-current flowing into the bit-line. It

Fig. 7. Analysis of effect of arrival time of�� pulse on (a) correct Writeand (b) faulty Write.

arrives too early when is high, the negative changein is not sufficient to pull-down to . In Fig. 7(b), itdoes not correct the faulty operation. In Fig. 7(a), it makes acorrect Write operation faulty as the Write current (at high )would charge up the floating bit-line to hurt the Write opera-tion. However, if the pulse arrives later when is low, node

and are more likely to cross each other due to the negativetransient at the bit-line. Thus, an optimal choice is to have the

pulse arriving near the middle of the word-line cycle.

V. EFFECT ON PERFORMANCE AND READ DISTURB

A. Effect on Performance and Read Access Failures

During the Read operation, if is held at ‘0’ or ‘1’, theboosting capacitors add additional load to the bit-lines, resultingin a higher delay. A high-to-low transition at , how-ever, provides an additional transient current helping the bit-linedischarge [Fig. 8(a)], especially if the Read delay is high. Thisis illustrated in Fig. 8(b) as obtained from simulations for a45-nm PD/SOI SRAM cell. The proposed Tran-NBL schemecan clearly be seen to improve the Read delay under largevariation at low cell supply voltage thereby reducing Read ac-cess failure. The high-to-low transition for here needsto be at the beginning of the pulse, instead of at the middleof the pulse (as in case for Write) to negate the impact ofthe additional boosting capacitances.

The dynamic behavior of the bit-lines during Read operationwith the proposed scheme can be simplified as

and


Fig. 8. Read operations: (a) equivalent circuit and (b) simulation results withworst-case Vt variation.

Fig. 9. Analytical results of Read performance. Effects of (a) boosting capac-itance and (b) falling slew.

(9)

where is the Read current, and is the arrivaltime. For simplicity, we assume to be independent of .From (9) we can observe that (with at )

(10)

where and and canbe obtained from (10). From (10) we observe that the proposedscheme reduces the bit-line discharge before the arrival of the

pulse as . Hence, for the Read opera-tion, the pulse should arrive at the beginning of theword-line pulse. With , the time required to reduceto 0.5 (i.e., ) can be computed from (10). The aboveprovides an insight into the impact of the proposed scheme onRead performance (Fig. 9). First, the Tran-NBL scheme reducesaccess time for slower Read operations (i.e., lower ), con-sistent with the simulation results shown in Fig. 8. Second, alower and higher reduce the Read access time.Hence, the proposed scheme has a positive impact on the cellswith slower Read performance which are primarily responsiblefor Read access failures.

B. Effect on Read Disturb

Faster discharge of the low-going bit-line during Read oper-ation reduces the Read disturb voltage at the drain of the accessdevice connected to the node storing ‘0’ ( in Fig. 1), thusimproving the Read stability. However, if the high-to-low tran-sition is too fast, the negative voltage spike at the high bit-linecan reduce the voltage at node , thereby adversely affectingthe Read stability. The overall impact of the proposed schemeon Read disturb failure is expected to be small.

VI. IMPLEMENTATION

A. Control Logic: Generation of Signal

The generation of the signal is the key control logicin the proposed scheme. The and generationlogic are shown in Fig. 10(a) and (b), respectively, and theirtiming waveforms are presented in Fig. 10(c). The signal ,generated from and its delayed version, generates alow-to-high transition at the middle of the word-line cycle.For the selected column during Write operation ( ,

) is inverted to generate [Fig. 10(a)]. Ifor , the signal is inverted to generateto ensure transition is at the beginning of

the pulse. In the conventional case, signal can begenerated from and (e.g., using a two-input NOR

logic). In the proposed case, this logic is modified such thatis the same as signal for Write

operation . For Readoperation, is the same as for the

selected columns and is ‘0’ for unselected columns.

B. Implementation of Tran-NBL in SRAM Array

The and generation logic can be shared by allthe columns which are selected simultaneously. The area over-head due to the control logic (excluding the driving inverter)is not significant. However, the driver inverter in thegeneration needs to be reasonably large to drive the boosting ca-pacitors with sufficiently small slew. Further, the size of pMOSdevices in the NOR logic for generation also needs to beincreased to ensure the same rise time for the signal asin the conventional case. The boosting capacitors needs to beintroduced for each column and are the major component of thearea overhead.

VII. STATISTICAL SIMULATIONS

The functionality of the proposed Tran-NBL scheme is veri-fied with a 45-nm PD/SOI SRAM cell using transient simulationand fast Monte Carlo simulator presented in [11]. An SRAMarray with dual supply scheme (cell supply and word-line

, peripheral including bit-line ) and short bit-line(32 cells/column) architecture [14]–[16] is used. The boostingcapacitance is realized using MOS capacitors. The width of theboosting device per SRAM cell is used as a measureof the boosting capacitance, i.e., per cell 0.1 mcorresponds to 3.2 m of boosting device for a column of 32cells. The total interconnect capacitance per cell is estimated


Fig. 10. Control logic for Tran-NBL Scheme. (a) �� generation; (b)NSEL generation; and (c) waveform of operation.

Fig. 11. Write failure correction using the proposed scheme. (a) Faulty Writeand (b) corrected Write.

assuming 0.2 fF m of metal capacitance [17]. All simulationsare performed at 85 (i.e., at worst-case leakage condition foractive data-retention failure).

Fig. 11(a) shows a faulty Write operation of SRAM cell afterapplying variation for the worst-case. Fig. 11(b) shows thatfor the same amount of variation, the proposed scheme resultsin a correct Write operation.

A. Effects of Boosting Capacitance and Falling-Slew

Considering ideal and signals, we observethat larger boosting device width (and hence boosting capaci-tance) and smaller falling-slew increases the negative voltageunder-shoot and improves the effectiveness of the proposedscheme [Fig. 12(a), slew of 40 ps, Fig. 12(b),

per cell 0.1 m]. Fig. 12 verifies the predictionsin Fig. 6(a). As expected, the improvement is larger with the

cross-coupled pMOS devices. From Figs. 2 and 12, we canobserve that 0.1 m per cell and 40 ps fall slew pro-vides and 4X lower Write failures compared to nominalcondition and 0.1 V reduction, respectively. If isincreased to 0.15 m per cell, the proposed method provides

250X lower Write failure compared to supply voltage re-duction of 0.2 V. In the proposed scheme the delay differencebetween the low-to-high transition at and high-to-lowtransition at signal is designed to be 50% of word-linepulse width. Fig. 12(c) shows that the proposed scheme re-mains effective across a large range of variation of this delay.However, if the high-to-low transition of the signalarrives too early, the proposed scheme can result in a higherWrite failure (as explained in Section IV-E) If arrivestoo late, the proposed scheme approaches the conventionalscheme. The above results validate that arrival at themiddle of the word-line pulse is a good choice.

B. Simulations With and Generation Circuits

We have performed the statistical simulations including theand generation circuits to capture the effects

of a) the finite strength of the driving inverter, b) active data-retention failure, and c) process variation. Simulations resultsshow that even with the finite driver strength, larger boostingdevices reduces the Write failure probability with Tran-NBL[Fig. 13(a)]. In this simulation, the nMOS device of the driveris sized to achieve 40 ps slew for 0.1 m per cellwith 32 cell per columns. In the rest of the paper, we will onlyconsider the scheme with the cross-coupled PMOSs. For a fixedboosting device, a larger driver nMOS reduces falling-slew ofthe signal and results in a lower Write failure prob-ability [Fig. 13(b)]. The proposed scheme helps to marginallyimprove the Read access and Read disturb failure probabilities[Fig. 13(b)]. A larger driver size (i.e., smaller slew) marginallyimproves the Read access and Read disturb failure probability.The driver size indicated in Fig. 13(b) represents the size re-quired to drive the boosting devices associated with one column.Hence, increasing the driver size can significantly impact thearea penalty. Based on Fig. 13(b) and the above discussion, weconclude that driver nMOS device of twice the minimum width(per column) is a good choice.

The active data-retention failure in the Tran-NBL scheme ismuch smaller compared to the DC negative bit-line [Fig. 2(b),the transient negative bit-line case]. This is because the bit-linebecomes negative for only a very short duration. The designpoint of 0.1 m per cell results in a active data reten-tion failure less than nominal Write failure.

The variation in the delay-chain affects the arrival timeof with respect to the pulse (designed at ).A very early or very late arrival of the pulse can in-crease the Write failures. However, as seen from Fig. 13(c) (graycurve), even a large variation ( 200 mV) has a negli-gible impact. Next, we consider the effect of variation in thearrival time difference between and signal, dueto mismatch in the of the driver nMOS in gen-eration circuit [Fig. 10(a)] and the nMOS connected to inthe NOR gate in generation logic [Fig. 10(b)]. Ifsignal arrives too early relative to signal, the low-going


Fig. 12. Write failure reduction with Tran-NBL assuming ideal �� and �� signals. Effects of (a) boosting capacitance, (b) falling slew of �� signal, and (c) Effect of �� arrival on Write failure reduction. The failure probabilities are normalized to the Write failure probability at normal operation[� � �, � �� , � � � �].

Fig. 13. Simulations including�� and �� generation circuits: (a) Write failure reduction considering finite strength of the�� driver, (b) effect ofdriver nMOS size on failure probabilities, and (c) effect of process variations in control circuits The disturb, access, and Write failure probabilities are normalizedto their corresponding values at normal operation [� � �, � �� , � � � �].

Fig. 14. Effect of (a) reduced supply and word-line voltage on Write failures, (b) Read access and disturb failures at reduced voltage, and (c) effect of distributedRC of bit-line on voltage undershoot.

bit-line will be strongly held at ‘0’ when high-to-low transitionin arrives, thus reducing the negative undershoot inthe low-going bit-line. If arrives too late with respectto signal, the voltage for the (floating) low-going bit-linecan increase from ‘0’ due to the Write current flowing into it.Simulation results show that this effect is small even formismatch of 200 mV [Fig. 13(c), black curve].

Statistical simulation results show that the Write failures arereduced even at a lower peripheral and cell supplycompared with the conventional case for all com-binations [Fig. 14(a)]. The Write failure probability is a strongerfunction of with the proposed technique as a lowerimplies a reduced voltage swing during the high-to-low transi-tion of which reduces the transient negative voltageat the bit-line. Simulations also show that disturb failures (nor-malized to its value for conventional case at ) andRead access failures (normalized to its value for conventional

case at ) are lower with the proposed Tran-NBLscheme [Fig. 14(b)].

C. Analysis of Area Overhead

We assume that the area overhead of the andgeneration circuits is negligible, since these are shared by a largenumber of columns. The size of driver nMOS per column isalso small (2X the minimum width) and can easily be imple-mented within one SRAM cell pitch (assuming uni-directionalgate, which is necessary beyond 65-nm nodes). The major areapenalty is associated with the implementation of the boostingdevices. Based on SRAM cell pitch for 45-nm node (obtainedfrom [17]), it is possible to implement the per column boostingcapacitors in four poly pitches. Thus, for a column of 32 cells(each cell occupies two poly pitches) with at least one redundantcell in both sides, the overall area overhead is approximately fiveto six poly pitches or 7%–9%.


D. Effect of Bit-Line Height

The effect of distributed RC of the bit-line on the voltage un-dershoot at the cell furthest from the boosting capacitor is shownFig. 14(c). The 45-nm SOI technology values for resistance andcapacitance of wire is used in the simulation. As observed, fora fixed per cell increasing the bit-line height from 32 to512 reduces the voltage undershoot at the furthest cell by 25%.Although the reduction is not significant, we believe the pro-posed method is most suitable for short bit-line.

VIII. SUMMARY

In this paper, we have presented a low-overhead technique forimproving the write-ability of 6 T SRAM cell. A transient neg-ative pulse was generated using capacitive coupling and appliedto the low-going bit-line during Write operation. The transientnegative pulse enhanced the access device strength and assistedthe Write operation. The proposed scheme also provided mar-ginal improvement in Read access and Read disturb failures.Tran-NBL could achieve higher reduction in Write failure com-pared to lower cell supply voltage while preserving the benefitsof bit-line (or column) based control and eliminating the needfor additional voltage levels.

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[12] W. J. Dally and J. W. Poulton, Digital Systems Engineering. Cam-bridge, U.K.: Cambridge Univ. Press, 1998.

[13] S. Mukhopadhyay et al., “Capacitive coupling based transient nega-tive bit-line voltage (Tran-NBL) scheme for improving write-ability ofSRAM design in nanometer technologies,” in Proc. ISCAS, 2008, pp.384–387.

[14] R. Joshi et al., “A low power and high performance SOI SRAM circuitdesign with improved cell stability,” in Proc. IEEE SOI Conf. 2006, pp.4–7.

[15] J. Pille et al., “Implementation of the CELL broadband engine in a 65nm SOI technology featuring dual-supply SRAM arrays supporting 6GHz at 1.3 V,” in Proc. IEEE ISSCC 2007, pp. 322–323.

[16] J. Davis, D. Plass, P. Bunce, Y. Chan, A. Pelella, R. Joshi, A. Chen,W. Huott, T. Knips, P. Patel, K. Lo, and E. Fluhr, “A 5.6 GHz 64 kBdual-read data cache for the POWER6TM processor,” in Proc. IEEEISSCC 2006, pp. 2564–2565.

[17] International Technology Roadmap for Semiconductors (ITRS-2005)[Online]. Available: http://www.itrs.net

Saibal Mukhopadhyay (S’99–M’07) ) received theB.E. degree in electronics and telecommunicationengineering from Jadavpur University, Calcutta,India, in 2000 and the Ph.D. degree in electrical andcomputer engineering from Purdue University, WestLafayette, IN, in 2006.

He is currently an Assistant Professor with theSchool of Electrical and Computer Engineeringat the Georgia Institute of Technology, Atlanta.His research interests include analysis and designof low-power and robust circuits in nanometer

technologies. He has (co)authored over 80 papers.Dr. Mukhopadhyay has received the IBM Faculty Partnership Award for

2009, the SRC Technical Excellence Award in 2005, and the IBM Ph.D.Fellowship award for 2004–2005.

Rahul M. Rao (M’06) received the B.E. degreefrom the University of Mumbai, India, in 2000 andthe M.S. and Ph.D. degrees from the University ofMichigan in 2002 and 2004, respectively.

He is currently a Research Staff Member at theIBM Thomas J. Watson Research Center. He hasbeen involved in the design of sensors for processmonitoring, reliability, and aging characterizationand variability estimation. His research interests liein low power design, adaptive circuits, variabilitycharacterization and compensation systems, and

stable memory designs.

Jae-Joon Kim (S’02–M’04) received the B.S. andM.S. degrees in electronics engineering from theSeoul National University, Seoul, Korea, and thePh.D. degree from the School of Electrical andComputer Engineering of Purdue University, WestLafayette, IN, in 1994, 1998, and 2004, respectively.

He was a Custom Circuit Designer with TLI, Inc.Korea from 1998 to 1999. He has been a ResearchStaff Member with the IBM T. J. Watson ResearchCenter, Yorktown Heights, NY, since May 2004. Hiscurrent research interest includes 3D VLSI integra-

tion, robust SRAM design, and on-chip monitoring circuit design.

Ching-Te Chuang (S’78–M’82–SM’91–F’94) re-ceived the B.S.E.E. degree from the National TaiwanUniversity, Taipei, Taiwan, in 1975 and the Ph.D.degree in electrical engineering from the Universityof California, Berkeley, in 1982.

He worked for nearly 26 years at the IBM T. J.Watson Research Center, Yorktown Heights, NY,from 1982 to January 2008, holding technical andmanagement positions in areas ranging from bipolardevices, circuits, and technologies, bipolar VLSIdesign, bipolar/BiCMOS logic and memory, and

circuit design of IBM’s high-performance CMOS microprocessors. Since 1996,he has been leading the Technology Circuit Co-Design for scaled/emergingtechnologies. He took early retirement from IBM in February 2008 to jointhe National Chiao-Tung University, Hsinchu, Taiwan, as a Chair Professor inthe Department of Electronics Engineering. He has received the OutstandingScholar Award from Taiwan’s Foundation for the Advancement of OutstandingScholarship for 2008 to 2013. He holds 30 U.S. patents with another tenpending. He has authored or coauthored over 270 papers.

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SRAm Write-Ability Improvement With Transient Negative Bit-Line Voltage

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